DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 12/5/2025, responding to the Office action mailed on 9/5/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/23/2026 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 7, 15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen et al. (US 20210376091 A1).
Re Claim 1 Yang teaches a semiconductor structure (FIG. 19C) comprising:
a dielectric bar (110) [0106] arranged between and physically separating a first source drain region (SD1) [0095] from a second source drain region (SD2),
wherein a first sidewall (left side of 110 part between SD1 and SD2 in FIG. 19C) of the dielectric bar (110) directly contacts a sidewall of the first source drain region (SD1), wherein a second sidewall (right side of 110 part between SD1 and SD2 in FIG. 19C) of the dielectric bar (110) directly contacts a sidewall of the second source drain region (SD2), and wherein the first sidewall of the dielectric bar is opposite the second sidewall of the dielectric bar (FIG. 19C).
Yang does not teach a first silicide liner directly beneath the first source drain region; and
a second silicide liner directly beneath the second source drain region.
Chen teaches a first silicide liner (216 at bottom of 204(1) S/D Region) [0033] directly beneath the first source drain regions (FIG. 2B); and
a second silicide liner (216 at bottom of 204(2) S/D Region) [0041] directly beneath the second source drain regions (FIG. 2C),
The ordinary artisan would have been motivated to modify Chen in combination with Yang in the above manner for the motivation of using cobalt and nickel for the silicide source drain region liners to obtain optimal Schottky barrier height. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like, in order to reduce a Schottky barrier height between doped portion 210 and correspondingly MD contact structure 218 and BVD structure 222.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang.
Yang in view of Chen does not explicitly teach the first silicide liner is a different material than the second silicide liner.
Chen does teach using four possible materials for the silicide liners. For example, one can use nickel for the first silicide liner, and cobalt for the second silicide liner. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like…”
The ordinary artisan would have been motivated to modify Chen in combination with Yang in view of Chen in the above manner for the motivation of using nickel for the first silicide liner and cobalt for the second silicide liner to help the drain source regions function ideally as they may have different conductivity types. Cobalt is known to have superior thermal stability and strength compared to other semiconductor metals like nickel, so the source drain regions made with cobalt will be stronger than the source drain regions made of nickel giving them more flexibility to operate in high temperatures.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang in view of Chen.
Re Claim 3 Yang in view of Chen teaches the semiconductor structure according to claim 1, further comprising:
first backside source drain contacts (Chen, 222 under 204(1)) directly beneath and in electrical communication with the first source drain region (204(1), FIG. 2C, [0035]); and
second backside source drain contacts (Chen, 222 under 204(2)) directly beneath and in electrical communication with the second source drain region (204(1), FIG. 2C).
Re Claim 7 Yang in view of Chen teaches the semiconductor structure according to claim 1,
the first sidewall of the dielectric bar (Yang, left sidewall of 110 in FIG. 19C between SD1 and SD1) directly contacts a sidewall of the first silicide liner (SC over SD1 [0111]),
wherein sidewalls of the second source drain region (SD2) and the second silicide liner (SC over SD2) directly contact a second sidewall of the dielectric bar (110 between SD1 and SD2), and
wherein the first sidewall (left side of 110 between SD1 and SD2) of the dielectric bar (110) is opposite the second sidewall (right side of 110 between SD1 and SD2) of the dielectric bar (FIG. 19C).
Re Claim 15 Yang teaches a semiconductor structure (FIG. 19A-C) comprising:
n-type nanosheet devices (CH2) comprising n-type source drain regions (SD2) [0094];
p-type nanosheet devices (CH1) comprising p-type source drain regions (SD1) [0094];
a dielectric bar (110 between SD1 and SD2 in FIG. 19C) arranged between and directly contacting a vertical sidewall of the n-type source drain regions (SD2) and a vertical sidewall of the p-type source drain regions (SD1);
a first silicide liner (SC, on right, [0111]) around the n-type source drain regions (SD2); and
second silicide liner (SC on left [0111]) around the p-type source drain regions (SD1).
Yang does not teach a first silicide liner directly beneath the source drain regions; and
second silicide liner directly beneath the source drain regions.
Chen teaches a first silicide liner (216 at bottom of 204(1) S/D Region) [0033] directly beneath the source drain regions (204(1)); and
second silicide liner (216 at bottom of 204(2) S/D Region) [0041] directly beneath the source drain regions (FIG. 2C).
The ordinary artisan would have been motivated to modify Chen in combination with Yang in the above manner for the motivation of using cobalt and nickel for the silicide source drain region liners to obtain optimal Schottky barrier height. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like, in order to reduce a Schottky barrier height between doped portion 210 and correspondingly MD contact structure 218 and BVD structure 222.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang.
Yang in view of Chen does not explicitly teach the first silicide liner is a different material than the second silicide liner.
Chen does teach using four possible materials for the silicide liners. For example, one can use nickel for the first silicide liner, and cobalt for the second silicide liner. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like…”
The ordinary artisan would have been motivated to modify Chen in combination with Yang in view of Chen in the above manner for the motivation of using nickel for the first silicide liner and cobalt for the second silicide liner to help the drain source regions function ideally as they may have different conductivity types. Cobalt is known to have superior thermal stability and strength compared to other semiconductor metals like nickel, so the source drain regions made with cobalt will be stronger than the source drain regions made of nickel giving them more flexibility to operate in high temperatures.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang in view of Chen.
Re Claim 17 Yang in view of Chen teaches the semiconductor structure according to claim 15, further comprising:
first backside source drain contacts (Chen, 222 under 204(1)) directly beneath and in electrical communication with the n-type source drain regions (204(1), FIG. 2C, [0035]); and second backside source drain contacts (Chen, 222 under 204(2)) directly beneath and in electrical communication with the p-type source drain regions (204(1), FIG. 2C).
Re Claim 20 Yang in view of Chen teaches the semiconductor structure according to claim 15,
wherein sidewalls of the n-type source drain regions (Yang, SD2) and the first silicide liner (SC over SD2) directly contact a first sidewall of the dielectric bar (right side of 110 between SD1 and SD2),
wherein sidewalls of the p-type source drain regions (SD1) and the second silicide liner (SC over SD1) directly contact a second sidewall of the dielectric bar (left side of 110 between SD1 and SD2) and wherein the first sidewall of the dielectric bar is opposite the second sidewall of the dielectric bar (FIG. 19C).
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen et al. (US 20210376091 A1) as applied to claims 1 and 15 above, and further in view of Chiu et al. (US 20220384590 A1).
Re Claim 2 Yang in view of Chen teaches the semiconductor structure according to claim 1, but does not teach:
a first silicide arranged between and directly contacting the first source drain region and the first silicide liner; and
a second silicide arranged between and directly contacting the second source drain region and the second silicide liner.
Chiu teaches a first silicide (132, FIG. 2E) arranged between and directly contacting the first source drain region (110, [0013], FIG. 2E) and the first silicide liner (134) [0014]; and
a second silicide (132, FIG. 2E, parts can be reused as shown in FIG. 1B) arranged between and directly contacting the second source drain region (110, [0013], FIG. 2E) and the second silicide liner (134) [0014].
The ordinary artisan would have been motivated to modify Chiu in combination with Yang in view of Chen in the above manner for the motivation of silicide semiconductors include improved device performance and increased durability in microelectronics, such as integrated circuits and transistors. A silicide is a compound of silicon and metal that serve as low-resistance electrical contacts, gates, and interconnects within silicon-based devices allowing the semiconductor structure a to function optimally. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chiu into the structure of Yang in view of Chen.
Re Claim 16 Yang in view of Chen teaches the semiconductor structure according to claim 15, with an N-type source drain region (Yang, SD2) and a P-type source drain regions (SD1).
Yang in view of Chen does not teach a first silicide arranged between and directly contacting the n-type source drain regions and the first silicide liner; and
a second silicide arranged between and directly contacting the p-type source drain regions and the second silicide liner.
Chiu teaches a first silicide (132, FIG. 2B) arranged between and directly contacting the source drain regions (110 above first silicide, FIG. 2B) and the first silicide liner; and
a second silicide (132, FIG. 2B) arranged between and directly contacting source drain regions (110 above first silicide, FIG. 2B) and the second silicide liner.
The ordinary artisan would have been motivated to modify Chiu in combination with Yang in view of Chen in the above manner for the motivation of silicide semiconductors include improved device performance and increased durability in microelectronics, such as integrated circuits and transistors. A silicide is a compound of silicon and metal that serve as low-resistance electrical contacts, gates, and interconnects within silicon-based devices allowing the semiconductor structure a to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chiu into the structure of Yang in view of Chen.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen et al. (US 20210376091 A1) as applied to claim 1 above, and further in view of Huang (US 20210407999 A1).
Re Claim 4 Yang in view of Chen teaches the semiconductor structure according to claim 1, further comprising:
Huang teaches first backside source drain contacts (353) [0061] directly beneath and in electrical communication with the first source drain region (316 on right in FIG. 8, [0057]), wherein bottommost surfaces of the first backside source drain contacts (353) are substantially flush with a bottommost surface of the dielectric bar (308, [0056], FIG. 8); and
second backside source drain contacts (form a second 353 below 316 on left in FIG. 8, [0061] states, “Referring to part (b) of FIG. 8, in the source or drain locations, one or more lower source or drain contacts 353 is formed.”) directly beneath and in electrical communication with the second source drain region (316 on left), wherein bottommost surfaces of the second backside source drain contacts (form second 353 under 316 on left in FIG. 8) are substantially flush with a bottommost surface of the dielectric bar (308, FIG. 8).
The ordinary artisan would have been motivated to modify Huang in combination with Yang in view of Chen in the above manner for the motivation of optimally integrating contacts under the source and drain regions to allow for the device to be as small as possible as the industry continues to scale down still allowing the device to function at a peak level. [0002] states, “For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Huang into the structure of Yang in view of Chen.
Claims 5-6 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chen et al. (US 20210376091 A1) as applied to claims 1 and 15 above, and further in view of Liu et al. (US 20220367625 A1).
Re Claim 5 Yang in view of Chen teaches the semiconductor structure according to claim 1, but does not teach a distance between the first source drain region and the second source drain region is less than 10 nm.
Liu teaches in [0070] “In some embodiments, the width W.sub.1 of the main layers 98B between opposing liner layers 98A is in the range of 3 nm to 50 nm.” The left 98 [0070] region in FIG. 14A is the first source drain region, and the right 98 is the second source drain region. The distance between the 2 98B regions is slightly less or close to the width of each 98B region. Therefore the distance between the first and second source drain regions is roughly 3 nm to 50 nm or slightly less. Therefore, a distance between the first source drain region (FIG. 14A, 98 on left) and the second source drain region (98 on right) is less than 10 nm.
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chen in the above manner for the motivation of finding the ideal distance between the source drain regions to enable the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chen.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal width between source drain regions.
Re Claim 6 Yang in view of Chen and Liu teaches the semiconductor structure according to claim 1, but does not explicitly teach a lateral width of the dielectric bar is less than 10 nm.
Liu teaches a dielectric bar (88, [0042] Fig. 14A) between the first source drain region (98 on left) and the second source drain region (98 on right). As established in claim 5, the distance between the first and second source drain regions is 3 nm to 50 nm or slightly less. Therefore, the dielectric bar (88) will be less than 3 nm to 50 nm.
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chen and Liu in the above manner for the motivation of finding the ideal lateral width of the dielectric bar in between the drain source regions to allow the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chen and Liu.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal dielectric lateral width.
Re Claim 18 Yang in view of Chen teaches the semiconductor structure according to claim 15, but does not teach a distance between each of the n-type source drain regions and each of the p-type source drain regions is less than 10 nm.
Liu teaches a distance between each of the n-type source drain regions and each of the p-type source drain regions is about 3nm to 50nm. ([0070] states, “As a result, the width W.sub.1 of the main layers 98B between opposing liner layers 98A may be controlled. In some embodiments, the width W.sub.1 of the main layers 98B between opposing liner layers 98A is in the range of 3 nm to 50 nm.”).
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chen in the above manner for the motivation of finding the ideal distance between the source drain regions to enable the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chen.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal width between source drain regions.
Re Claim 19 Yang in view of Chen teaches the semiconductor structure according to claim 8, but does not teach a lateral width of the dielectric bar is less than 10 nm.
Liu teaches a dielectric bar (88, Fig. 23A) between the source drain region (98) and the distance between the source drain regions will be 3 nm to 50 nm [0070]. The dielectric bar will be the less width between the source drain regions since 124 is also in between the source drain regions (Figure. 23A).
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chen in the above manner for the motivation of finding the ideal lateral width of the dielectric bar in between the drain source regions to allow the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chen.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal dielectric lateral width.
Claims 8, 10, 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chi et al. (CN 115602686 A) and Chen et al. (US 20210376091 A1).
Re Claim 8 Yang teaches a semiconductor structure (FIG. 19A-C) comprising:
first nanosheet devices (CH1 in FIG. 19A, [0145]) comprising first channel nanosheets and first source drain regions (SD1) [0146];
second nanosheet devices (CH2 in FIG. 19B, [0145]) comprising second channel nanosheets and second source drain regions (SD2) [0147];
a dielectric bar (110 between SD1 and SD2, FIG. 19C) [0106] directly contacts sidewalls of the first source drain regions (SD1);
first silicide liners (SC) [0111] around the first source drain regions (SD1); and
second silicide liners (SC) around the second source drain regions (SD2, FIG. 19A and B).
Yang does not teach the dielectric bar arranged between the first nanosheet devices and the second nanosheet devices, wherein a first sidewall of the dielectric bar directly contacts sidewalls of the first channel nanosheets.
Chi teaches the dielectric bar (110, page 19 last par) arranged between the first nanosheet devices (120N, page 19 par 4) and the second nanosheet devices (130P), wherein a first sidewall (left side) of the dielectric bar (110) directly contacts sidewalls of the first channel nanosheets (FIG. 19).
The ordinary artisan would have been motivated to modify Chi in combination with Yang in the above manner for the motivation of integrating a dielectric bar between the channel regions to build a transistor capable of improving gate controllability. Parge 2 par 2 states, “Various embodiments of the present invention provide a semiconductor device capable of improving gate controllability and a method for manufacturing the same.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chi into the structure of Yang.
Yang in view of Chi does not teach silicide liners directly beneath the source drain regions.
Chen teaches a silicide liners (216 at bottom of 204(1) and 204(2) S/D Regions) [0033] directly beneath the first source drain regions (FIG. 2B and 2C).
The ordinary artisan would have been motivated to modify Chen in combination with Yang in view of Chi in the above manner for the motivation of using cobalt and nickel for the silicide source drain region liners to obtain optimal Schottky barrier height. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like, in order to reduce a Schottky barrier height between doped portion 210 and correspondingly MD contact structure 218 and BVD structure 222.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang in view of Chi.
Yang in view of Chi and Chen does not explicitly teach the first silicide liners are a different material than the second silicide liners.
Chen does teach using four possible materials for the silicide liners. For example, one can use nickel for the first silicide liner, and cobalt for the second silicide liner. [0036] states, “…bottom silicide layer 216 includes titanium, nickel, cobalt, or erbium, or the like…”
The ordinary artisan would have been motivated to modify Chen in combination with Yang in view of Chi and Chen in the above manner for the motivation of using nickel for the first silicide liner and cobalt for the second silicide liner to help the drain source regions function ideally as they may have different conductivity types. Cobalt is known to have superior thermal stability and strength compared to other semiconductor metals like nickel, so the source drain regions made with cobalt will be stronger than the source drain regions made of nickel giving them more flexibility to operate in high temperatures.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chen into the structure of Yang in view of Chi and Chen.
Re Claim 10 Yang in view of Chi and Chen teaches the semiconductor structure according to claim 8, further comprising:
first backside source drain contacts (Chen, 222 under 204(1)) directly beneath and in electrical communication with each of the first source drain regions (204(1), FIG. 2C, [0035]); and
second backside source drain contacts (Chen, 222 under 204(2)) directly beneath and in electrical communication with each of the second source drain regions (204(1), FIG. 2C).
Re Claim 12 Yang in view of Chi and Chen teaches the semiconductor structure according to claim 8, but does not explicitly teach a distance between each of the first source drain regions and each of the second source drain regions is less than 10 nm.
Liu teaches a distance between each of the first source drain regions and each of the second source drain regions is about 3nm to 50nm. ([0070] states, “As a result, the width W.sub.1 of the main layers 98B between opposing liner layers 98A may be controlled. In some embodiments, the width W.sub.1 of the main layers 98B between opposing liner layers 98A is in the range of 3 nm to 50 nm.”).
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chi and Chen in the above manner for the motivation of finding the ideal distance between the source drain regions to enable the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chi and Chen.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal width between source drain regions.
Re Claim 13 Yang in view of Chi and Chen teaches the semiconductor structure according to claim 8, but does not explicitly teach a lateral width of the dielectric bar is less than 10 nm.
Liu teaches a dielectric bar (88, Fig. 23A) between the source drain region (98, Fig,1) and the distance between the source drain regions will be 3 nm to 50 nm [0070]. The dielectric bar will be the less width between the source drain regions since 124 is also in between the source drain regions (Figure. 23A).
The ordinary artisan would have been motivated to modify Liu in combination with Yang in view of Chen in the above manner for the motivation of finding the ideal lateral width of the dielectric bar in between the drain source regions to allow the semiconductor structure to function optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Liu into the structure of Yang in view of Chen.
Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal dielectric lateral width.
Re Claim 14 Yang in view of Chen teaches the semiconductor structure according to claim 8,
wherein the first sidewall of the dielectric bar (Yang, left sidewall of 110 in FIG. 19C between SD1 and SD1) directly contacts sidewalls of the first silicide liners (SC over SD1 [0111]),
wherein a second sidewall (right side of 110) of the dielectric bar directly contacts sidewalls of the second source drain regions (SD2) and sidewalls of the second silicide liners (SC on right, FIG. 19C), and
wherein the first sidewall of the dielectric bar (left of 110 between SD1 and SD2) is opposite the second sidewall of the dielectric bar (right side of 110).
Yang in view of Chen does not teach a second sidewall of the dielectric bar directly contacts sidewalls of the second channel nanosheets.
Chi teaches a second sidewall (right side) of the dielectric bar (110) directly contacts sidewalls of the second channel nanosheets (130P, page 7 par 2, FIG. 19).
The ordinary artisan would have been motivated to modify Chi in combination with Yang in view of Chen in the above manner for the motivation of integrating a dielectric bar between the channel regions to build a transistor capable of improving gate controllability. Parge 2 par 2 states, “Various embodiments of the present invention provide a semiconductor device capable of improving gate controllability and a method for manufacturing the same.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chi into the structure of Yang in view of Chen.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chi et al. (CN 115602686 A) and Chen et al. (US 20210376091 A1) as applied to claim 8 above, and further in view of Chiu (US 20220384590 A1).
Re Claim 9 Yang in view of Chi and Chen teaches the semiconductor structure according to claim 8, but does not teach:
a first silicide arranged between and directly contacting the first source drain region and the first silicide liner; and
a second silicide arranged between and directly contacting the second source drain region and the second silicide liner.
Chiu teaches a first silicide (132, FIG. 2E) arranged between and directly contacting the first source drain region (110, [0013], FIG. 2E) and the first silicide liner (134) [0014]; and
a second silicide (132, FIG. 2E, parts can be reused as shown in FIG. 1B) arranged between and directly contacting the second source drain region (110, [0013], FIG. 2E) and the second silicide liner (134) [0014].
The ordinary artisan would have been motivated to modify Chiu in combination with Liu in view of Chi and Chen in the above manner for the motivation of silicide semiconductors include improved device performance and increased durability in microelectronics, such as integrated circuits and transistors. A silicide is a compound of silicon and metal that serve as low-resistance electrical contacts, gates, and interconnects within silicon-based devices allowing the semiconductor structure a to function optimally. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chiu into the structure of Liu in view of Chi and Chen.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20210134785 A1) in view of Chi et al. (CN 115602686 A) and Chen et al. (US 20210376091 A1) as applied to claim 8 above, and further in view of Huang et al. (US 20210407999 A1).
Re Claim 11 Yang in view of Chi and Chen teaches the semiconductor structure according to claim 8, but does not teach:
first backside source drain contacts directly beneath and in electrical communication with each of the first source drain regions, wherein bottommost surfaces of the first backside source drain contacts are substantially flush with a bottommost surface of the dielectric bar; and
second backside source drain contacts directly beneath and in electrical communication with each of the second source drain regions, wherein bottommost surfaces of the second backside source drain contacts are substantially flush with a bottommost surface of the dielectric bar.
Huang teaches first backside source drain contacts (353) [0061] directly beneath and in electrical communication with each of the first source drain regions (316 on right in FIG. 8, [0057]), wherein bottommost surfaces of the first backside source drain contacts (353) are substantially flush with a bottommost surface of the dielectric bar (308, [0056], FIG. 8); and
second backside source drain contacts (form a second 353 below 316 on left in FIG. 8, [0061] states, “Referring to part (b) of FIG. 8, in the source or drain locations, one or more lower source or drain contacts 353 is formed.”) directly beneath and in electrical communication with each of the second source drain regions (316 on left), wherein bottommost surfaces of the second backside source drain contacts (form second 353 under 316 on left in FIG. 8) are substantially flush with a bottommost surface of the dielectric bar (308, FIG. 8).
The ordinary artisan would have been motivated to modify Huang in combination with Liu in view of Chi and Chen in the above manner for the motivation of optimally integrating contacts under the source and drain regions to allow for the device to be as small as possible as the industry continues to scale down still allowing the device to function at a peak level. [0002] states, “For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Huang into the structure of Liu in view of Chi and Chen.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 4/21/26
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