DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to an Application filed on 06/21/2023.
Currently, claims 1-20 are examined as below.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 06/21/2023. The IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 is indefinite, because the limitation “the via” in line 4 is not mentioned before. Only a “conductive via” in recited in the intervening claim 7. There is insufficient antecedent basis.
Claim 17 is indefinite, because the limitation “the staircase interconnect structure” in line 5 is not mentioned before. Only a “interconnect structure” is recited earlier in the claim. There is insufficient antecedent basis.
Note the dependent claims 10-16 and 18 necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2023/0138478 A1 to Choi et al. (“Choi”).
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Regarding independent claim 1, Choi in Fig. 2 and Annotated Fig. 2 teaches an integrated circuit (IC) device 100 (Fig. 1 & ¶ 22, semiconductor device 100 is a functional memory device, and a memory device is an IC device), comprising:
a substrate 101 (¶ 28, first substrate 101);
a device layer DL (Annotated Fig. 2) over or at least partially in the substrate 101, the device layer DL comprising a plurality of transistors 120 (¶ 30, circuit devices 120 including transistors); and
an interconnect layer CELL (¶ 22, memory cell region CELL), wherein the device layer DL is between the substrate 101 and the interconnect layer CELL (Annotated Fig. 2), the interconnect layer CELL includes a first conductive line 230A (Annotated Fig. 2, ¶ 35, the lowermost gate electrode 230A) and a second conductive line 230B (Annotated Fig. 2) stacked above the first conductive line 230A, a first end (Annotated Fig. 2, right end) of the first conductive line 230A is substantially aligned with a first end (Annotated Fig. 2, right end) of the second conductive line 230B along a plane perpendicular to the substrate 101, and a second end (Annotated Fig. 2,, left end) of the first conductive line 230A is closer to the plane than a second end (Annotated Fig. 2, left end) of the second conductive line 230B.
Regarding claim 2, Choi in Annotated Fig. 2 further teaches an insulator material 220 (¶ 35, interlayer insulating layer 220) between the first conductive line 230A and the second conductive line 230B.
Regarding claim 3, Choi in Fig. 2 and Annotated Fig. 2 further teaches the interconnect layer CELL is at least a part of a metallization stack (Fig. 2, ¶ 31, ¶ 33-¶ 35, ¶ 63, ¶ 65, a collective of interconnection lines 137, 277, gate electrodes 230, lower capping layer 190 including insulating layers, upper capping layer 290 including insulating layers and interlayer insulating layers 220) of the IC device 100, and wherein the first conductive line 230A and the second conductive line 230B are in different metal layers 230 (Annotated Fig. 2, ¶ 31, ¶ 34, ¶ 54, ¶ 63, gate electrodes 230 include metal material) of the metallization stack.
Regarding claim 4, Choi in Annotated Fig. 2 further teaches a third conductive line 230C (Annotated Fig. 2) stacked above the second conductive line 230B, a first end (Annotated Fig. 2, right end) of the third conductive line 230C is substantially aligned with the first end of the second conductive line 230B along the plane, and the second end of the second conductive line 230B is closer to the plane than a second end (Annotated Fig. 2, left end) of the third conductive line 230C.
Regarding claim 5, Choi in Annotated Fig. 2 further teaches an insulator material 220 (¶ 35, interlayer insulating layer 220) between the second conductive line 230B and the second third conductive line 230C.
Regarding claim 6, Choi in Fig. 2 and Annotated Fig. 2 further teaches the interconnect layer CELL is at least a part of a metallization stack (Fig. 2, ¶ 31, ¶ 33-¶ 35, ¶ 63, ¶ 65, a collective of interconnection lines 137, 277, gate electrodes 230, lower capping layer 190 including insulating layers, upper capping layer 290 including insulating layers and interlayer insulating layers 220) of the IC device 100, and wherein the first conductive line 230A, the second conductive line 230B, and the third conductive line 230C are in different metal layers 230 (Annotated Fig. 2) of the metallization stack.
Regarding claim 7, Choi in Fig. 2 and Annotated Fig. 2 further teaches a conductive via 252 (Annotated Fig. 2, ¶ 34, contact plug 252) extending from a portion of the first conductive line 230A that is closer to the second end of the first conductive line 230A than to the first end of the first conductive line 230A (Annotated Fig. 2), the conductive via 252 comprising a first portion (Fig. 2, upper portion) and a second portion (Fig. 2, lower portion), wherein:
the first portion (i.e., upper portion) of the conductive via 252 is closer to the first conductive line 230A than the second portion (i.e., lower portion) of the conductive via 252 (Annotated Fig. 2), and
a width of the first portion of the conductive via 252 is smaller than a width of the second portion of the conductive via 252 (Fig. 2, ¶ 58).
Regarding claim 8, Choi in Fig. 2 and Annotated Fig. 2 further teaches the conductive via 252 is a first conductive via 252 (Annotated Fig. 2, ¶ 34, contact plug 252 contacting the first conductive line 230A), and the IC device 100 further includes a second conductive via 252 (Annotated Fig. 2, ¶ 34, contact plug 252 contacting the second conductive line 230B) extending from a portion of the second conductive line 230 that is closer to the second end (i.e., left end) of the second conductive line 230 than to the first end (i.e., right end) of the second conductive line 230B (Annotated Fig. 2), the second conductive via 252 comprising a first portion (Fig. 2, upper portion) and a second portion (Fig. 2, lower portion), wherein:
the first portion of the second conductive via 252 is closer to the second conductive line 230B than the second portion of the second conductive via 230B (Annotated Fig. 2), and
a width of the first portion (i.e., upper portion) of the second conductive via 252 is smaller than a width of the second portion (i.e., lower portion) of the second conductive via 252 (Fig. 2, ¶ 58).
Regarding claim 9, Choi in Fig. 2 and Annotated Fig. 2 further teaches a bonding interface 184, 186, 284, 286 (Fig. 2, ¶ 32, ¶ 64, a collective of lower bonding pad 184, lower bonding insulating layer 186, upper bonding pad 284 and upper bonding insulating layer 286) between the interconnect layer CELL and the device layer DL, wherein:
the bonding interface 184, 186, 284, 286 includes a bonding contact 184, 284 (Fig. 2, ¶ 32, a collective of lower bonding pad 184 and upper bonding pad 284) and a bonding dielectric 186, 286 (Fig. 2, ¶ 32 a collective of lower bonding insulating layer 186 and upper bonding insulating layer 286), and
the via 252 is in conductive contact with the bonding contact 184, 284 (Fig. 2, ¶ 27, ¶ 32, ¶ 34).
Regarding claim 10, Choi in Fig. 2 further teaches the bonding contact 184, 284 is a direct bonding contact (Fig. 2, ¶ 32, copper-to-copper bonding, and the direct contact (i.e., bonding) between the layers 184, 284).
Regarding claim 11, Choi in Fig. 2 further teaches the bonding contact 184, 284 is a hybrid bonding contact (Fig. 2, ¶ 32, hybrid bonding uses both Cu-to-Cu bonding and dielectric-to-dielectric bonding).
Regarding claim 12, Choi in Fig. 2 and Annotated Fig. 2 further teaches at least one contact 135 (Annotated Fig. 2, ¶ 31, lower contact plug 135) of the device layer DL is in conductive contact with the bonding contact 184, 284 (Fig. 2, ¶ 27, ¶ 32).
Regarding claim 13, Choi in Annotated Fig. 2 further teaches the at least one contact 135 of the device layer DL is one of contact to a source region 128 (Annotated Fig. 2, ¶ 29, source/drain region 128) of the at least one transistor 120, or a contact to a drain region 128 (Annotated Fig. 2, ¶ 29, source/drain region 128) of the at least one transistor 120.
Regarding claim 14, Choi in Annotated Fig. 2 further teaches the at least one contact 135 of the device layer DL is a conductive via 135 (Annotated Fig. 2, ¶ 31, lower contact plug 135) of the device layer DL.
Regarding claim 15, Choi in Fig. 2 and Annotated Fig. 2 further teaches a metallization stack 137, 135 (Annotated Fig. 2, ¶ 87, ¶ 89, a collective of lower interconnection lines 137, lower contact plugs 135 and lower capping layer 190 above the device layer DL, in which the lower capping layer 190 includes insulating layers) comprising a plurality of metal layers 137 (Fig. 2, ¶ 31, lower interconnection lines 137 are formed of metal materials), wherein the metallization stack 137, 135, 190 is between the device layer DL and the bonding interface 184, 186, 284, 286 (Annotated Fig. 2), and at least one interconnect structure 137 (Fig. 2, the uppermost interconnection line 137) of a metal layer 137 of the plurality of metal layers 137 that is closest to the bonding interface 184, 186, 284, 286 is in conductive contact with the bonding contact 184, 284 (Fig. 2, ¶ 32).
Regarding claim 16, Choi in Fig. 2 further teaches the at least one interconnect structure 137 of the metal layer 137 is a conductive line 137 (¶ 31, lower interconnection line 137).
Regarding independent claim 17, Choi in Figs. 1-2 teaches an integrated circuit (IC) device 100 (Fig. 1 & ¶ 22, semiconductor device 100 is a functional memory device, and a memory device is an IC device), comprising:
a die PERI (Figs. 1-2, ¶ 23, ¶ 28, peripheral circuit region PERI is a block of material including an integrated circuit comprising electronic components i.e., transistors. That is, the region PERI is a die) having a surface (Fig. 2, upper surface), wherein the die PERI includes conductive contacts 184 (Fig. 2, ¶ 32, lower bonding pad 184) at the surface;
an interconnect structure CELL (¶ 22, memory cell region CELL) comprising a stack 230, 220 (Fig. 2) of conductive lines 230 (Fig. 2, ¶ 35, gate electrodes 230) separated by an insulator material 220 (¶ 35, interlayer insulating layer 220); and
a bonding interface 184, 186, 284, 286 (Fig. 2, ¶ 32, ¶ 64, a collective of lower bonding pad 184, lower bonding insulating layer 186, upper bonding pad 284 and upper bonding insulating layer 286) between the surface and the staircase interconnect structure CELL,
wherein the conductive lines 230 of the stack 230, 220 are in a staircase arrangement with a longest one of the conductive lines 230 being further away from the bonding interface 184, 186, 284, 286 than a shortest one of the conductive lines 230 (Fig. 2).
Regarding claim 18, Choi in Fig. 2 further teaches conductive vias 252 (Fig. 2, ¶ 34, contact plug 252) extending from individual ones of the conductive lines 230, wherein the conductive vias 252 taper down as the conductive vias 252 extend further away from the bonding interface 184, 186, 284, 286 (Fig. 2, ¶ 58).
Regarding independent claim 19, Choi in Figs. 1-2, 17-18 and Annotated Fig. 2 teaches an integrated circuit (IC) package 2003a or 2003A (Figs. 17-18, ¶ 135-¶ 136 & ¶ 143, semiconductor package 2003a or 2003A having a semiconductor chip 2200a including the semiconductor device 100 of Figs. 1-2; Figs. 1-2 & ¶ 22, semiconductor device 100 is a functional memory device, and a memory device is an IC device), comprising:
an IC die PERI (Figs. 1-2, ¶ 23, ¶ 28, peripheral circuit region PERI is a block of material including an integrated circuit comprising electronic components i.e., transistors. That is, the region PERI is an IC die); and
a further component 2200a (Fig. 18, ¶ 141, the other semiconductor chip 2200a), coupled to the IC die PERI,
wherein the IC die PERI includes a device layer DL (Annotated Fig. 2) and an interconnect layer CELL (Figs. 1-2, ¶ 22, memory cell region CELL), the interconnect layer CELL includes a stack of conductive lines 230 (Fig. 2, ¶ 35, gate electrodes 230) separated by an insulator material 220 (¶ 35, interlayer insulating layer 220), and the conductive lines 230 of the stack 230, 220 (Fig. 2) are in a staircase arrangement with a longest one of the conductive lines 230 being further away from the device layer DL than a shortest one of the conductive lines 230 (Annotated Fig. 2).
Regarding claim 20, Choi the further component 2200a is a further IC die 2200a (Fig. 18, ¶ 141, the other semiconductor chip 2200a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0021449 A1 to Choi et al. relates to a semiconductor device including circuit devices on a first substrate, a lower interconnection structure electrically connected to the circuit devices, a lower bonding structure connected to the lower interconnection structure, an upper bonding structure on the lower bonding structure, an upper interconnection structure connected to the upper bonding structure, a second substrate on the upper interconnection structure, gate electrodes between the upper interconnection structure and the second substrate, channel structures penetrating the gate electrodes and each including a channel layer, via patterns on the second substrate, a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode, and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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