DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 21, 2023; May 9, 2024; April 7, 2025; and November 21, 2025 were considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, and 17-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Dokania et al. (US 11,696,451 B1) (“Dokania”).
Regarding claim 1, Dokania teaches at least in figure 5A, 7A, and 9B:
a transistor (MN) over a support structure (301),
the transistor (MN) having a region (detailed below),
wherein the region (detailed as follows) is either a source region or a drain region (342);
a first plateline (PL0_1) and a second plateline (PLO_2_;
a first capacitor (Cfe1),
wherein a first capacitor electrode (sn1) of the first capacitor (Cfe1) is coupled to the region (342), and
a second capacitor electrode (PL0_1 connected to Cfe1) of the first capacitor (Cfe1) is coupled to the first plateline (PL0_1); and
a second capacitor (Cfe2),
wherein a first capacitor electrode of the second capacitor is coupled to the region (both capacitors first capacitor electrodes are coupled to sn1 which is coupled to 342), and
a second capacitor electrode of the second capacitor is coupled to the second plateline (Cfe2’s second capacitor electrode is coupled to PL0_2),
wherein the first plateline (PL_01) is between the support structure (301) and the second plateline (PL0_2) (based upon the embodiment shown in figure 7A; If an argument is presented that this is not inherent in Dokania then it would have been obvious based upon the cited figures and the disclsoure), and
the first capacitor electrode of the first capacitor is materially continuous with the first capacitor electrode of the second capacitor (figure 5A shows that all the first capacitor electrodes are connected together).
Regarding claim 2, Dokania teaches at least in figure 5A, 7A, and 9B:
wherein the second plateline (PL0_2) is stacked above the first plateline (PL0_1) above the support structure (see figure 7A).
Regarding claim 3, Dokania teaches at least in figure 5A, 7A, and 9B:
wherein a projection of the second plateline onto a plane parallel to the support structure at least partially overlaps with a projection of the first plateline onto the plane (this is shown in figure 7A).
Regarding claim 4, Dokania teaches at least in figure 5A, 7A, and 9B:
wherein a projection of the first capacitor electrode of the second capacitor onto a plane parallel to the support structure at least partially overlaps with a projection of the first capacitor electrode of the first capacitor onto the plane
Regarding claim 5, Dokania teaches at least in figure 5A, 7A, and 9B:
further comprising (detailed below)
a conductive via (Via0) having a first end and a second end (detailed below),
wherein the first end of the conductive via is coupled to the region (Via0 is coupled to source contact), and
the second end of the conductive via (Via0) is coupled to an electrically conductive material (detailed below) extending away from the support structure (342),
wherein a first portion of the electrically conductive material is the first capacitor electrode (sn1) of the first capacitor (PL0_1) and
a second portion of the electrically conductive material (sn1)is the first capacitor electrode of the second capacitor (PL0_2).
Regarding claim 6, Dokania teaches at least in figure 5A, 7A, and 9B:
wherein the first portion and the second portion are materially continuous portions of the electrically conductive material (sn1 is a materially continuous portion of the electrically conductive material as shown in figure 5A and 7A. This is because in the end device they are a monolithic structure.).
Regarding claim 17, Dokania teaches at least in figure 5A, 7A, 9B, and 13B:
Claim 17 is different than claim 1 in that claim 17 is claiming a second set of capacitors with the same structure as the first set of capacitors in claim 1. Dokania teaches this in figure 5A. Where the circuit diagram of figure 5A teaches claim 1. The second set of capacitors in figure 5A come from a second memory bit-cells 5010,0 in the array 501. Therefore, while only one set of capacitors is shown in figure 5A in the circuit diagram it would be inherent, or obvious, that the entire figure 5A shows a second set of capacitors in the manner claimed. Therefore, claim 17 is rejected for the reasons stated in at least one of claims 1-6, and the rational above.
Regarding claim 18,
Claim 18 is rejected for the same reasons as claim 17 above.
Claim Rejections - 35 USC § 103
Claim(s) 7-16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dokania.
Regarding claims 7-16, Dokania teaches at least in figure 5A, 7A, 9B, and 13B:
Claims 7-16 are a duplication of the structure described in claims 1-6 above. Under MPEP 2144.04(VI)(B) the mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Here Applicant is merely duplicating the capacitors of claims 1-6 above. There are no unexpected results arising from this mere duplication.
Regarding claim 19,
Claim 19 is rejected for at least the same reasons as at least one of claims 1-18 above. In addition, Dokania teaches in figures 15-16 that the memory array is formed on a die. Further, forming a memory array on a die is extremely obvious in the art.
Regarding claim 20,
Claim 20 is rejected for at least the same reasons as at least one of claims 1-19 above.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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