Prosecution Insights
Last updated: April 19, 2026
Application No. 18/338,869

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Final Rejection §103§112
Filed
Jun 21, 2023
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
711 granted / 1052 resolved
At TC average
Strong +30% interview lift
Without
With
+29.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
110 currently pending
Career history
1162
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
43.9%
+3.9% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
20.7%
-19.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1052 resolved cases

Office Action

§103 §112
DETAILED ACTION This office action is in response to amendment filed 1/19/2026. Claims 1-19 and 21 are pending. Claim 20 has been canceled. Claim 21 is new. Claims 7, 9-13, and 15-19 have been withdrawn. Claims 1, 9, and 15 have been amended. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6, 8, 14, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 reciting “the lower buried portion not substantially overlapping with the source area and the drain area” renders the claim indefinite. It is unclear what constitutes “substantially overlapping” and thus what is intended to be excluded by “not substantially overlapping”. It is unclear how much overlap between the lower buried portion and the source/drain area is allowed by “not substantially overlapping”. The metes and bounds of the claim is indefinite. Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 8, 14, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. US 2016/0172488 A1 (OH) in view of Zhang et al. US 2022/0352340 A1 (Zhang). PNG media_image1.png 512 626 media_image1.png Greyscale In re claim 1, as best understood, OH teaches (e.g. FIGs. 1-2) a semiconductor device comprising: a substrate 101 including a trench 105, a source area 117, and a drain area 118, the source area 117 and the drain area 118 being spaced apart from each other with the trench 105 between the source area and the drain area; a gate insulating layer 106 in the trench; and a gate electrode 107 in the trench 105, the gate electrode 107 including a lower buried portion 108 and an upper buried portion 112 in contact with the gate insulating layer 106, the lower buried portion 108 “not substantially overlapping with the source area 117 and the drain area 118” (108 is positioned below 117,118 without lateral overlap, furthermore there is also no vertical overlap between 108 and 117,118), including a first conductive layer 108, the first conductive layer 108 contacting the gate insulating layer 106, the upper buried portion 112 at least partially overlapping with the source area 117 and the drain area 118, including a work function liner layer 113 and a second conductive layer 115, the work function liner layer 113 contacting the gate insulating layer 106 in the trench, the second conductive layer 115 contacting the work function liner layer 113 and the first conductive layer 108, the second conductive layer 115 including a transition metal (titanium or tungsten, ¶ 57), and the work function liner layer 113 including a low work function material (¶ 50). OH discloses the second conductive layer 115 include tungsten (¶ 57) adjacent to a low work function liner layer 113. OH does not explicitly teach the work function liner layer 113 is a two-dimensional (2D) material layer including a chalcogen compound of a transition metal that is identical to the transition metal in the second conductive layer 115. However, Zhang teaches (e.g. FIGs. 3-7) a gate electrode comprising a work function liner layer 205 and a conductive layer 202, wherein the work function liner layer 205 is a 2D material layer (layer of atomic crystals, e.g. WSe2 atomic crystals, ¶ 33), wherein the work function can be adjusted by changing the thickness of the atomic crystals (¶ 37,43). Zhang further discloses the conductive layer 202 includes transition metal tungsten to obtain good bonding strength between the WSe2 work function layer and the W layer (¶ 43). A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the work function layer can be formed of WSe2 for the purpose of tuning the work function. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of obtaining a work function layer with desired work function. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the work function liner layer 113 of OH using WSe2 to obtain a low work function layer by changing the thickness of the layer according to the desired work function according to known methods to yield the predictable result of a gate layer with desired work function as taught by Zhang. As such, the work function liner layer is a two-dimensional (2D) material layer WSe2 including a chalcogen compound (Se2) of a transition metal (W) that is identical to the transition metal (W) in the second conductive layer 115. In re claim 2, OH discloses (e.g. FIGs. 2A-2B) wherein the first conductive layer 108 includes a transition metal 111 (W) that is identical to the transition metal (W) in the second conductive layer (¶ 57). In re claim 3, OH discloses (e.g. FIGs. 2A-2B) wherein the transition metal in the second conductive layer 115 includes at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W). ¶ 57, e.g. tungsten In re claim 4, Zhang discloses (e.g. FIG. 3) wherein the 2D material layer 205 (e.g. WSe2, ¶ 53) -includes at least one of sulfur (S), selenium (Se), and tellurium (Te). In re claim 5, OH discloses (e.g. FIGs. 2A-2B) further comprising: a capping layer 116 on the gate electrode 107. In re claim 8, Zhang discloses wherein the 2D material layer (WSe2 atomic crystals) has an island form or has a non-uniform thickness. The atoms of each crystal layer of WSe2 constitute islands. In re claim 14, OH discloses (e.g. FIG. 13) a memory device 500 comprising: a capacitor 525 (¶ 250); and the semiconductor device 506,516,517 of claim 1 electrically connected with the capacitor 525. In re claim 21, OH discloses (e.g. FIGs. 2A-2B) wherein the lower buried portion 108 and the upper buried portion 112 have different contact structures with the gate insulating layer 106, so that the first conductive layer 108 is in direct contact with the gate insulating layer 106, and the second conductive layer 115 is not in direct contact with the gate insulating layer 106, the first conductive layer 108 is a single layer containing at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W) (no specific “single layer” has been claimed that would distinguish over Oh’s “single layer” 108 which “contains” Ti or W, ¶ 57; direct contact between the claimed metals and the gate insulating layer 106 is not required), the 2D material layer 113 (obvious to be WSe2 as taught by Zhang) directly contacts the gate insulating layer 106 in the trench, the second conductive layer 115 directly contacts the 2D material layer 113, the 2D material layer 113 is between the gate insulating layer 106 and the second conductive layer 115. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of OH and Zhang as applied to claim 1 above, and further in view of Cheung et al. US 2023/0063549 A1 (Cheung). In re claim 6, OH teaches the claimed invention having the gate insulating layer 106 includes a lower area surrounding the first conductive layer 108 and an upper area surround the work function layer 113 which can be 2D material as taught by Zhang. OH does not explicitly disclose the lower area has a first permittivity, and the upper area has a second permittivity that is less than the first permittivity. However, Cheung discloses (e.g. FIG. 2) a semiconductor device comprising a trench gate 18 between source/drain 24,26, a gate insulating layer 20a lines the trench, and a gate electrode 18 filling in the trench including a lower buried portion forming a first conductive layer and an upper buried portion forming a second conductive layer, wherein the gate insulating layer 20a includes a lower area 32a surrounding the first conductive layer (lower portion of 18 below 33) and an upper area 30 surrounding the upper portion of 18 (above 33), the lower area 32a (high-k material, ¶ 20) has a first permittivity, and the upper area 30 (low-k material) has a second permittivity that is less than the first permittivity (¶ 16). Cheung discloses the invention structure reduces gate-induced-drain-leakage (¶ 24). A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the gate insulating layer can be modified with a composite structure having a high-k layer surrounding lower gate portion and a low-k layer surrounding upper gate portion for the purpose of reducing gate-induced-drain-leakage. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of reduced gate-induced-drain-leakage. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify OH’s gate insulating layer 106 for a composite structure of Cheung including a high-k layer surrounding lower gate portion and a low-k layer surrounding upper gate portion according to known methods to yield the predictable result of reducing gate-induced-drain-leakage as taught by Cheung. Response to Arguments Applicant's arguments filed 1/19/2026 have been fully considered but they are not persuasive. Applicant argues modifying Oh’s non-metal work function material 113 with Zhang’s 2D material would “violate the core design principle” of Oh (Remark, page 13). This is not persuasive. Oh’s device design relies on the work function material 113 to include a low work function material (¶ 50). While the second work function liner 113 “may” include a non-metal material as the low work function material, the invention is not understood to be operable only using non-metal material. Rather, a non-metal material is merely an exemplary material choice for a low work function layer. The desired device characteristic can be achieved with any low work function material so long as the work function requirement is met. Zhang teaches using layer of WSe2 atomic crystals (¶ 33), a layer of 2D material, as work function liner layer 205, wherein the work function can be adjusted by changing the thickness of the atomic crystals (¶ 37,43). As such, a low work function material layer can be obtained using Zhang’s WSe2 2D material layer with adequate thickness. As such, it would be obvious to a person of ordinary skill in the art to form OH’s low work function metal liner 113 using WSe2 adjusted to a thickness that obtains the desired work function as taught by Zhang. Applicant further argues Zhang fails to teach the spatial arrangement of the overlap between the source/drain area and the gate material (Remark, page 13). This is not persuasive. Zhang was cited for teaching the use of WSe2 2D material as a low work function material in a gate electrode. The spatial arrangement and overlap of the source/drain area and the gate is taught by OH. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Applicant further argues impermissible hindsight on the combination of OH and Zhang (Remark, page 13). In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). As detailed above, Oh teaches a need of a low work function material layer 113. Zhang teaches WSe2 2D material being a known work function material where the work function value can be tuned based on the thickness of the atomic crystals (¶ 37,43). Therefore, forming OH’s low work function metal liner 113 using WSe2 adjusted to a thickness that obtains the desired work function as taught by Zhang would be obvious. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
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Prosecution Timeline

Jun 21, 2023
Application Filed
Oct 17, 2025
Non-Final Rejection — §103, §112
Dec 27, 2025
Interview Requested
Jan 09, 2026
Applicant Interview (Telephonic)
Jan 09, 2026
Examiner Interview Summary
Jan 19, 2026
Response Filed
Mar 20, 2026
Final Rejection — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.9%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 1052 resolved cases by this examiner. Grant probability derived from career allow rate.

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