DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/28/2026 has been entered.
Claims 1-19 and 21 are pending. Claim 20 has been canceled. Claims 7, 9-13, and 15-19 have been withdrawn. Claims 1 and 21 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 8, 14, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites “the upper surface of the single layer directly contacts 2D material layer” renders the claim indefinite due to lack of proper correspondence. It is unclear if “2D material layer” is intended to previously recited 2D material layer.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 14, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2022/0077154 A1 (Kim) in view of Morris et al. US 2019/0019793 A1 (Morris).
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In re claim 1, as best understood, Kim teaches (e.g. FIGs. 5-6) a semiconductor device comprising:
a substrate 101 including a trench GT, a source area 105 (e.g. on left of GT shown in FIG. 5A), and a drain area 105 (e.g. on right of GT shown in FIG. 5A, ¶ 20),
the source area 105 (left) and the drain area 105 (right) being spaced apart from each other in a first direction (W direction) with the trench GT between the source area and the drain area in the first (W) direction (see FIG. 5A);
a gate insulating layer 120 in the trench GT; and
a gate electrode GEe,GEg (FIGs. 6A & 6C) in the trench GT,
the gate electrode GEe,GEg including a lower buried portion 131e,131g and an upper buried portion 133e+134e+135e or 134g+135g in contact with the gate insulating layer 120,
the lower buried portion 131e,131g not overlapping with the source area 105 and the drain area 105 in the first (W) direction (see FIG. 5A, 131d is positioned below 105 and does not overlap in W direction), the lower buried portion 131e,131g including a first conductive layer (first metal layer, ¶ 51,54,56), the first conductive layer 131e,131g contacting the gate insulating layer 120,
the upper buried portion 133e+134e+135e or 134g+135g at least partially overlapping with the source area 105 and the drain area 105 (¶ 20), including a two-dimensional (2D) material layer 134e,134g (graphene layer, ¶ 28,54,56) and a second conductive layer 133e+135e,135g, the 2D material layer 134e,134g contacting the gate insulating layer 120 in the trench GT, and the second conductive layer 133e+135e,135g contacting (e.g. electrically or physically) the 2D material layer 134e,134g and the first conductive layer 131e,131g,
the second conductive layer 133e+135e,135g including a transition metal (e.g. W, Ti, ¶ 51), and
the 2D material layer 134e,134g including a graphene (¶ 28,54,56), wherein
the first conductive layer 131e,131g is in direct contact with the gate insulating layer 120 (see FIGs. 6A & 6C), and the second conductive layer 133e+135e,135g is not in direct contact with the gate insulating layer 120 (separated by 134e,134g),
the first conductive layer 131e,131g is a single layer of a same conductive material,
a width of an upper surface of the single layer 131e,131g in the first (W) direction is greater than a width of a lower surface of the second conductive layer (lower surface of 133e or 135g in FIGs. 6A & 6C) in the first (W) direction (as shown in FIGs. 6A & 6C, upper surface of 131e,131g is wider than lower surface of 133e,135g),
the upper surface of the single layer 131e,131g directly contacts “the 2D material layer” 134e,134g, and
the width of the upper surface of the single layer 131e,131g in the first (W) direction is at a same level as an interface between the upper surface of the single layer 131e,131g and the 2D material layer 134e,134g.
Kim discloses the 2D material layer 134e,134g includes graphene and helps adjust the work function together with layer 135e,135g (¶ 50,54,56). Kim does not explicitly disclose the 2D material layer including a chalcogen compound of a transition metal that is identical to the transition metal in the second conductive layer 133e+135e,135g (e.g. W, Ti, ¶ 51).
However, Morris teaches (e.g. FIGs. 1-2) a gate electrode 102,202 comprising a work function material layer 212,120 and a conductive layer 122, wherein the work function liner layer 212,120 includes a 2D material layer including graphene or transition metal dichalcogenide (e.g. WTe2 or TiSe2, ¶ 17,27).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Kim’s 2D material layer using a transition metal dichalcogenide (e.g. WTe2 or TiSe2) instead of graphene as taught by Morris as suitable alternative to graphene for adjusting the work function of the gate electrode.
As such, the two-dimensional (2D) material layer is formed of WTe2 or TiSe2 and includes a chalcogen compound (Te2 or Se2) of a transition metal (W or Ti) that is identical to the transition metal (W, Ti) in the second conductive layer 133e+135e,135g.
In re claim 2, Kim discloses (e.g. FIGs. 6A & 6C) wherein the first conductive layer 131e,131g includes a transition metal (e.g. Ti, W) that is identical to the transition metal (e.g. Ti, W) in the second conductive layer 133e+135e,135g (¶ 51).
In re claim 3, Kim discloses (e.g. FIGs. 6A & 6C) wherein the transition metal in the second conductive layer 133e+135e,135g includes at least one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W). ¶ 51, e.g. Ti, W.
In re claim 4, Morris (e.g. FIGs. 1-2) discloses (e.g. FIGs. 1-2) wherein the 2D material layer 212,120 (e.g. WTe2, TiSe2, ¶ 17,27) -includes at least one of sulfur (S), selenium (Se), and tellurium (Te).
In re claim 5, Kim discloses (e.g. FIGs. 6A & 6C) further comprising: a capping layer 128 on the gate electrode GEe,GEg.
In re claim 8, Morris discloses wherein the 2D material layer (WTe2, TiSe2 atomic crystals, ¶ 17) has an island form or has a non-uniform thickness. The atoms of each crystal layer of WTe2, TiSe2 constitute islands.
In re claim 14, Kim discloses (e.g. FIG. 5A) a memory device comprising:
a capacitor CAP (¶ 40); and
the semiconductor device (transistor in region B) of claim 1 (see FIGs. 6A & 6C) electrically connected with the capacitor CAP.
In re claim 21, Kim discloses (e.g. FIGs. 5A & 6A & 6C) wherein
the lower buried portion 131e,131g and the upper buried portion 133e+134e+135e,134g+135g have different contact structures with the gate insulating layer 120,
the single layer of the first conductive layer 131e,131g contains one of molybdenum (Mo), ruthenium (Ru), rhodium (Rh), titanium (Ti), cobalt (Co), tantalum (Ta), and tungsten (W) (¶ 51),
the 2D material layer 134e,134g directly contacts the gate insulating layer 120 in the trench GT,
the second conductive layer 133e+135e,135g directly contacts the 2D material layer 134e,134g,
the 2D material layer 134e,134g is between the gate insulating layer 120 and the second conductive layer 133e+135e,135g.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kim and Morris as applied to claim 1 above, and further in view of Cheung et al. US 2023/0063549 A1 (Cheung).
In re claim 6, Kim teaches (e.g. FIGs. 6A & 6C) the claimed invention having the gate insulating layer 120 includes a lower area surrounding the first conductive layer 131e,131g and an upper area surrounding the 2D material layer 134e,134g.
Kim does not explicitly disclose the lower area has a first permittivity, and the upper area has a second permittivity that is less than the first permittivity.
However, Cheung discloses (e.g. FIG. 2) a semiconductor device comprising a trench gate 18 between source/drain 24,26, a gate insulating layer 20a lines the trench, and a gate electrode 18 filling in the trench including a lower buried portion forming a first conductive layer and an upper buried portion forming a second conductive layer, wherein the gate insulating layer 20a includes a lower area 32a surrounding the first conductive layer (lower portion of 18 below 33) and an upper area 30 surrounding the upper portion of 18 (above 33), the lower area 32a (high-k material, ¶ 20) has a first permittivity, and the upper area 30 (low-k material) has a second permittivity that is less than the first permittivity (¶ 16). Cheung discloses the invention structure reduces gate-induced-drain-leakage (¶ 24).
A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the gate insulating layer can be modified with a composite structure having a high-k layer surrounding lower gate portion and a low-k layer surrounding upper gate portion for the purpose of reducing gate-induced-drain-leakage. Furthermore, a person of ordinary skill in the art would have been able to carry out the modification. Finally, the modification achieves the predictable result of reduced gate-induced-drain-leakage. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim’s gate insulating layer 120 for a composite structure of Cheung including a high-k layer surrounding lower gate portion and a low-k layer surrounding upper gate portion according to known methods to yield the predictable result of reducing gate-induced-drain-leakage as taught by Cheung.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 8, 14, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights