DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-15) in the reply filed on 12/23/25 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/23/25. Claims 11-15 are further withdrawn since claims 11-15 include the limitation “a through silicon via in the logic chip”, which is a feature found exclusively in non-elected Species II.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 thru 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Adkisson et al. US 7,361,989 B1 in view of Lee et al. US 2023/0238411 A1. Adkisson discloses (see, for example, FIG. 7) an image sensor package comprising a package substrate 46, logic chip 32, image sensor chip 28, and bonding wire 52. The logic chip 32 is mounted on the package substrate 46, and the logic chip 32 includes a central region with the image sensor chip 28 being mounted on the central region of the logic chip 32, and the logic chip 32 also including an edge region with connection pads 54. Adkisson does not disclose a dam structure disposed in the edge region of the logic chip and covering a portion of the bonding wire; a cover glass disposed on the dam structure; and an encapsulation structure encapsulating the bonding wire on the package substrate. However, Lee discloses (see, for example, FIG. 4) an image sensor package 100 comprising a sensor chip 2, dam structure 4, cover glass 5, and an encapsulation structure 6. It would have been obvious to one of ordinary skill in the art to have a dam structure disposed in the edge region of the logic chip and covering a portion of the bonding wire; a cover glass disposed on the dam structure; and an encapsulation structure encapsulating the bonding wire on the package substrate in order to protect the top of the image sensor and have an optical element for maintaining light transmission to the image sensor chip.
Regarding claim 2, see, for example, FIG. 7 wherein Adkission discloses a first area of the logic chip 32 being larger than a second area of the image sensor chip 28.
Regarding claim 3, see, for example, FIG. 7 of Adkisson and FIG. 4 of Lee wherein Adkission in view of Lee discloses the third area of the dam structure 4 being larger than the second area of the image sensor chip 28.
Regarding claim 4, see, for example, FIG. 7 of Adkisson and FIG. 4 of Lee wherein Adkission in view of Lee discloses the fourth area of the cover glass 5 being larger than the second area of the image sensor chip 28.
Regarding claim 5, see, for example, FIG. 7 of Adkisson and FIG. 4 of Lee wherein Adkission in view of Lee discloses the encapsulation structure 6 contacts the outer walls of the logic chip 32, outer walls of the dam structure 4, and outer walls of the cover glass 5.
Regarding claim 6, see, for example, FIG. 7 of Adkisson and FIG. 4 of Lee wherein Adkission in view of Lee discloses the encapsulation structure 6 not contacting the image sensor chip 28.
Regarding claim 7, see, for example, FIG. 7 wherein Adkission discloses a connection pad 54 disposed on the edge portion of the logic chip 32, wherein the bonding wire 52 is bonded to the connection pad 54. In FIG. 4, Lee discloses the dam structure 4 covers a connection pad 213.
Regarding claim 8, see, for example, FIG. 7 wherein Adkisson discloses the logic chip 32 and the image sensor chip 28 being electrically connected to each other by a solder ball 40 disposed therebetween.
Regarding claim 9, see, for example, FIG. 7 of Adkisson and FIG. 4 of Lee wherein Adkission in view of Lee discloses the dam structure 4 and the image sensor chip 28 being spaced apart from each other, wherein sidewalls of the dam structure 4 face sidewalls of the image sensor chip 28, and wherein a vertical level of a top surface of the dam structure 4 being higher than a vertical level of a top surface of the image sensor chip 28.
Regarding claim 10, Adkisson in view of Lee does not expressly disclose the dam structure comprises glass attach glue; however, it would have been obvious to one of ordinary skill in the art to have glass attach glue in order to improve stability between the cover glass and the dam structure.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Eugene Lee
January 3, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815