DETAILED ACTION
This Office Action is in response to Amendment filed April 17, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 2, 4-6 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contain subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Regarding claim 1, Applicant did not enable one of ordinary skill in the art to obtain the claimed configuration in the newly added limitation “an epitaxial layer in the first-type window and the second-type window, wherein the epitaxial layer fills up the first-type window and the second-type window (emphasis added)” recited on lines 15-16 for the following reasons:
(A) The breath of the claims: Applicant does not define exactly what the phrase “fills up” implies, and therefore, the phrase “fills up” should be interpreted to be “fills 100%”, “fills entirely” or “fills completely”, which appears to be Applicant’s arguments in the Response filed July 21, 2026;
(B) The nature of the invention; Applicant claims that the epitaxial layer 21 fills up or completely fills the empty space formed by the first-type mask layer 11 and the second-type mask layer 12 shown in Fig. 11 of current application, which suggests that the epitaxial layer 21 is in complete contact with all the side, top and bottom surfaces of the first-type mask layer 11 shown in Fig. 11 of current application, and with the inner lateral surfaces of the second-type mask layer 12 shown in Fig. 11 of current application, and also suggests that there is no empty space inside the epitaxial layer 21 below the top surface level of the second-type mask layer 12;
(C) The state of the prior art: One of ordinary skill in the art understands that an epitaxial growth of a semiconductor layer using a dielectric mask layer would create numerous defects that involve empty spaces inside the epitaxially grown semiconductor layer;
(C-1) For example, Fig. 2C of D’Evelyn et al. (US 11,721,549) shows creation of threading dislocations 214, which include empty spaces since threading dislocations are line defects inside a single crystalline lattice structure, between patterned mask layers 111 due to the dissimilar material compositions of the substrate and the epitaxially grown semiconductor layer as illustrated below;
PNG
media_image1.png
156
688
media_image1.png
Greyscale
(C-2) Fig. 3C of D’Evelyn et al. (US 11,721,549) also shows creation of voids 225 between patterned mask layers 111 due to an imperfect and/or incomplete epitaxial growth 221 caused by a growth of a semiconductor material on the side and bottom surface of the patterned mask layers 111 as shown in Fig. 3B of D’Evelyn et al. as illustrated below;
PNG
media_image2.png
248
618
media_image2.png
Greyscale
(C-3) Therefore, one of ordinary skill in the art would readily recognize that there would be a portion of an epitaxial layer grown on the side and bottom surfaces of the first-type mask layer 11 and second-type mask layer 12 shown in Fig. 11 of current application, resulting in voids similar to the voids 225 shown in Fig. 3C of D’Evelyn et al., in which case, the epitaxial layer cannot fill up the first-type window and the second-type window;
(C-4) Also, as Figs. 7 and 10-13 of Beaumont et al. (“Mg-enhanced lateral overgrowth of GaN on patterned GaN/sapphire substrate by selective Metal Organic Vapor Phase Epitaxy,” MRS Internet Journal of Nitride Semiconductor Research 3 (1998) 20), and Figs. 2, 4 and 6 of Zhao et al. (“Optical properties evolution of GaN film grown via lateral epitaxial overgrowth,” Applied Surface Science 513 (2020) 145816) show, voids are commonly formed when an epitaxial growth is performed in conjunction with a dielectric mask layer;
(C-5) Therefore, one of ordinary skill in the art would readily recognize that there would be voids in the epitaxial layer 21 inside the first-type mask layer 11 and the second-type mask layer 12 shown in Fig. 11 of current application similar to the voids disclosed by Beaumont et al. and Zhao et al., in which case, the epitaxial layer cannot fill up the first-type window and the second-type window;
(D) The level of one of ordinary skill: while one of ordinary skill knows how to grow an epitaxial semiconductor layer by using the claimed first- and second-type mask layer, one of ordinary skill in the art would not know how to completely prevent dislocations and voids from forming in the epitaxial layer 21 shown in Fig. 11 of current application;
(E) The level of predictability in the art: epitaxial growth of a semiconductor material has been commonly performed in conjunction with a dielectric mask layer in semiconductor research and industry, and thus there is a high predictability in epitaxial growth of a semiconductor material when it comes to creation of defects;
(F) The amount of direction provided by the inventor; Applicant did not originally disclose any detailed parameters or growth conditions for forming the epitaxial layer 21 shown in Fig. 11 of current application beyond a simple statement in paragraph [0090] of current application that “The formation process of the epitaxial layer 21 may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or a combination thereof”;
(G) The existence of working examples: there is no existence of apparently working examples in the original specification, because (a) Applicant simply used the phrase “fills up” without defining the phrase in the original specification, and (b) the only basis of Applicant’s claiming that “the epitaxial layer fills up the first-type window and the second-type window” appears to be the overly simplified illustrations of current application, which Applicant did not originally disclose to be exactly to the scale;
(H) The quantity of experimentation needed to make or use the invention based on the content of the disclosure: it would require undue experimentation to obtain the claimed configuration where “the epitaxial layer fills up the first-type window and the second-type window”, especially when the claimed invention appears to be directed to an overly simplified illustration or an inventive concept without any detailed microscopic structures of the claimed epitaxial layer rather than an actual semiconductor structure on which Applicant actually measured the quality, crystallinity and defects.
Claims 2, 4-6 and 17 depend on claim 1, and therefore, claims 2, 4-6 and 17 also fail to comply with the Enablement requirement.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakahata et al. (US 7,473,315)
Cheng (US 2023/0080538)
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 August 14, 2026
Prosecution Insights