DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 16 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujita (US 2020/0275558).
Regarding claim 1, Fujita discloses, in at least figures 1-2 and related text, an integrated circuit (IC) package comprising:
a semiconductor die (302, [102]);
a glass layer (10, [45]); and
a capacitor (11, [46]) electrically coupled to the semiconductor die (302, [102], at least one side of the capacitor (11, [46]) enclosed by the glass layer (10, [45]), the capacitor (11, [46]) positioned closer to the glass layer (10, [45]) than the semiconductor die (302, [102]) is to the glass layer (10, [45]).
Regarding claim 2, Fujita discloses the IC package of claim 1 as described above.
Fujita further discloses, in at least figures 1-2 and related text, a dielectric material (6, [47]) separating the glass layer (10, [45]) and the semiconductor die (302, [102]).
Regarding claim 3, Fujita discloses the IC package of claim 1 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the glass layer (10, [45]) includes a through glass via (TGV) (3, [45]) extending between first and second surfaces of the glass layer (10, [45]), the first surface facing towards the semiconductor die (302, [102]), the semiconductor die (302, [102]) electrically coupled to the TGV (3, [45]).
Regarding claim 5, Fujita discloses the IC package of claim 1 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the capacitor (11, [46]) is a metal-insulator-metal (MIM) capacitor ([90], [93]).
Regarding claim 6, Fujita discloses the IC package of claim 5 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the MIM capacitor (11, [46]) includes a first plate (4b/2, [45], [46], [90]) and a second plate (9a, [90]), the first plate (4b/2, [45], [46], [90]) positioned closer to the glass layer (10, [45]) than the second plate (9a, [90]) is to the glass layer (10, [45]).
Regarding claim 7, Fujita discloses the IC package of claim 6 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the MIM capacitor (11, [46]) further includes a dielectric layer (8, [93]) separating the first plate (4b/2, [45], [46], [90]) and the second plate (9a, [90]).
Regarding claim 8, Fujita discloses the IC package of claim 6 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the first plate (4b/2, [45], [46], [90]) is to contact a surface of the glass layer (10, [45]).
Regarding claim 9, Fujita discloses the IC package of claim 8 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the first plate (4b/2, [45], [46], [90]) extends along the surface of the glass layer (10, [45]).
Regarding claim 16, Fujita discloses, in at least figures 1-2, 4(a)-4(i), and related text, a method for forming a semiconductor package comprising:
providing a through glass via (TGV) (3, [45]) extending between first (upper surface of 10, figures) and second (lower surface of 10, figures) surfaces of a glass substrate (10, [45]), the first surface (upper surface of 10, figures) opposite the second surface (lower surface of 10, figures);
positioning a capacitor (11, [46]) on the first surface (upper surface of 10, figures) of the glass substrate (10, [45]);
adding a dielectric material (6/13, [48]), the capacitor (11, [46]) to be enclosed between the glass substrate (10, [45]) and the dielectric material (6/13, [48]); and
mounting a semiconductor die (302, [102]) to the dielectric material (6/13, [48]), the semiconductor die (302, [102]) electrically coupled to the capacitor (11, [46]).
Regarding claim 18, Fujita discloses the method of claim 16 as described above.
Fujita further discloses, in at least figures 1-2, 4(a)-4(i), and related text, depositing a first layer of metal (layer of 4b, [90], figures) on the glass substrate (10, [45]), the first layer of metal (layer of 4b, [90], figures) corresponding to a first electrode (4b, [90]) of the capacitor (11, [46]);
depositing a dielectric layer (8, [93]) on the first layer of metal (layer of 4b, [90], figures); and
depositing a second layer of metal (layer of 9a, [90]) on the glass substrate (10, [45]), the second layer of metal (layer of 9a, [90]) corresponding to a second electrode (9a, [90]) of the capacitor (11, [46]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita (US 2020/0275558) in view of Kamgaing (US 2022/0406523).
Regarding claim 10, Fujita discloses the IC package of claim 1 as described above.
Fujita does not explicitly disclose the capacitor is a trench capacitor.
Kamgaing teaches, in at least figure 2 and related text, the device comprising the capacitor (201, [33]) is a trench capacitor, for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Fujita and Kamgaing are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujita with the specified features of Kamgaing because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Fujita to have the capacitor being a trench capacitor, as taught by Kamgaing, for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14], Kamgaing).
Regarding claim 11, Fujita in view of Kamgaing discloses the IC package of claim 10 as described above.
Kamgaing further teaches, in at least figure 2 and related text, the trench capacitor (201, [33]) includes at least one branch embedded in the glass layer (202, [33]), the at least one branch including a first electrode (206, [34]) and a second electrode (210, [34]), the first electrode (206, [34]) surrounding the second electrode (210, [34]), the first (206, [34]) and second (210, [34]) electrodes separated by a dielectric (208, [32]), for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Regarding claim 12, Fujita in view of Kamgaing discloses the IC package of claim 11 as described above.
Kamgaing further teaches, in at least figure 2 and related text, the at least one branch is positioned in a cavity (204, [34]) of the glass layer (202, [33]), for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Regarding claim 13, Fujita discloses, in at least figures 1-2 and related text, an integrated circuit (IC) package comprising:
a package substrate (10, [45]) having a glass core, the package substrate (10, [45]) supporting a semiconductor die (302, [102]); and
first (4b, [90]) and second (9a, [90]) electrodes separated by a dielectric material (8, [93]), the second electrode (9a, [90]) positioned closer to the semiconductor die (302, [102]) than the first electrode (4b, [90]) is to the semiconductor die (302, [102]), the first (4b, [90]) and second (9a, [90]) electrodes electrically coupled to the semiconductor die (302, [102]).
Fujita does not explicitly disclose the first electrode in contact with the glass core; the first and second electrodes at least partially enclosed by a surface of the glass core.
Kamgaing teaches, in at least figure 2 and related text, the device comprising the first electrode (206, [34]) in contact with the glass core (202, [33]); the first (206, [34]) and second (210, [34]) electrodes at least partially enclosed by a surface of the glass core (202, [33]), for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Fujita and Kamgaing are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujita with the specified features of Kamgaing because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Fujita to have the first electrode in contact with the glass core; the first and second electrodes at least partially enclosed by a surface of the glass core, as taught by Kamgaing, for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14], Kamgaing).
Regarding claim 14, Fujita in view of Kamgaing discloses the IC package of claim 13 as described above.
Kamgaing further teaches, in at least figure 2 and related text, the glass core (202, [33]) includes a cavity (204, [34]) on the surface of the glass core (202, [33]), portions of at least one of the first (206, [34]) or second (210, [34]) electrodes extending into the cavities (204, [34]), for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Regarding claim 15, Fujita in view of Kamgaing discloses the IC package of claim 13 as described above.
Fujita further discloses, in at least figures 1-2 and related text, the first electrode (4b, [90]) includes a first metal film, the first metal film extending along the surface of the glass core (10, [45]), and the second electrode (9a, [90]) includes a second metal film, the second metal film extending in a same direction (horizontal direction, figures) as the first metal film (figures).
Regarding claim 20, Fujita discloses the method of claim 18 as described above.
Fujita does not explicitly disclose the first layer of metal, the dielectric layer, and the second layer of metal are deposited across a planar surface of the glass substrate, the planar surface corresponding to the first surface of the glass substrate.
Kamgaing teaches, in at least figure 2 and related text, the method comprising the first layer of metal (206, [32]), the dielectric layer (208, [32]), and the second layer of metal (210, [32]) are deposited across a planar surface of the glass substrate (202, [33]), the planar surface corresponding to the first surface (upper surface of 202, figure) of the glass substrate (202, [33]), for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14]).
Fujita and Kamgaing are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujita with the specified features of Kamgaing because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Fujita to have the first layer of metal, the dielectric layer, and the second layer of metal being deposited across a planar surface of the glass substrate, the planar surface corresponding to the first surface of the glass substrate, as taught by Kamgaing, for the purpose of providing deep trenches within the glass core to enhance capacitance density ([14], Kamgaing).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujita (US 2020/0275558) in view of Duong (US 2023/0091666).
Regarding claim 19, Fujita discloses the method of claim 18 as described above.
Fujita does not explicitly disclose providing a cavity in the glass substrate, the cavity spaced apart from the TGV, the first layer of metal, the dielectric layer, and the second layer of metal deposited within the cavity.
Duong teaches, in at least figures 2, 3E, and related text, the method comprising providing a cavity (opening for 210/304, [32], [35], figures) in the glass substrate (202, [30]), the cavity (opening for 210, [32], figures) spaced apart from the TGV (234, [33]), the first layer of metal (252 (352), [31], [37]), the dielectric layer (254 (354), [31], [38]), and the second layer of metal (256 (356), [31], [40]) deposited within the cavity (opening for 210/304, [32], [35], figures), for the purpose of increasing capacitance density within a package while reducing the overall footprint of a package ([15]).
Fujita and Duong are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujita with the specified features of Duong because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Fujita to have the providing a cavity in the glass substrate, the cavity spaced apart from the TGV, the first layer of metal, the dielectric layer, and the second layer of metal deposited within the cavity, as taught by Duong, for the purpose of increasing capacitance density within a package while reducing the overall footprint of a package ([15], Duong).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1, 3, and 4 that recite "a patch antenna on the second surface, the patch antenna electrically coupled to the semiconductor die via the TGV" in combination with other elements of the base claims 1, 3, and 4.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 16 and 17 that recite "positioning a patch antenna on the first surface of the glass substrate, the semiconductor die and the patch antenna electrically coupled via the TGV" in combination with other elements of the base claims 16 and 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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