DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 18-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 18, the limitations “one or more second nanosheets stacked above the substrate, the one or more second nanosheets forming second channels, a number of second channels being N-M, 1≤M<N… a number of second nanosheets is N, a lower most N-M second nanosheets forming the second channels” is unclear and vague.
The limitations “one or more second nanosheets stacked above the substrate, the one or more second nanosheets forming second channels, a number of second channels being N-M “ is contradictory to “a number of second nanosheets is N”.
The limitations already established that the one or more second nanosheet formed are second channels (second nanosheets above the substrate = second channels). Therefore with this limitations N-M cannot be the same as N. The applicant needs to clarify the channels if its all the nanosheets as described in lines 18-19 or the limitations in line 29. For examination purposes, the limitation will be interpreted and examined as “a plurality of second nanosheets stacked above the substrate, one or more second nanosheets forming second channels, a number of second channels being N-M… a number of second nanosheets is N, a lower most N-M second nanosheets forming the second channels”” Correction is requested.
Claims 2-9 and 19-24 are also rejected as being dependent on claim 1 and claim 18 respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-8, 18-20, 22-24, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al (US Publication No. 2018/0090624).
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Regarding claims 1 and 18, as best understood, Cheng discloses a gate-all-around (GAA) device and a method of fabricating a GAA device, comprising: a substrate Fig 16, 102; a first nanosheet (NS) structure formed above a first logic area of the substrate Fig 16, Nano device stack II; and a second nanosheet (NS) structure formed above a second logic area of the substrate Fig 16, Nano device stack I different from the first logic area Fig 16, Nano device stack II, wherein the first NS structure comprises: a plurality of first nanosheets Fig 16, 108 stacked above the substrate, the plurality of first nanosheets forming first channels ¶0059, a number of first channels being N, N≥2 Fig 16; a first source Fig 16, 1202 on the substrate on a first source side of the first channels Fig 16, the first source being electrically coupled with the first channels Fig 16; a first drain Fig 16, 1202 on the substrate on a first drain side of the first channels opposite the first source side Fig 16, the first drain being electrically coupled with the first channels Fig 16; a first gate Fig 16, 1602 on the substrate in a first gate region between the first source and the first drain Fig 16, the first gate surrounding each of the first channels Fig 16; and a first dielectric between the first channels and the first gate ¶0048, 0058-0059, the first dielectric surrounding each of the first channels in the first gate region¶0048, 0058-0059, wherein the second NS structure Fig 16, Nano device stack I comprises: plurality of second nanosheets Fig 16, 108 stacked above the substrate, the one or more second nanosheets Fig 16, 108 forming second channels, a number of second channels being N-M Fig 16, 108 (108aI/108bI/108cI), 1≤M<N; a second source Fig 16, 1202 on the substrate on a second source side of the second channels, the second source being electrically coupled with the second channels Fig 16; a second drain Fig 16, 1202 on the substrate on a second drain side of the second channels opposite the second source side, the second drain being electrically coupled with the second channels Fig 16; a second gate Fig 16, 1602 on the substrate in a second gate region between the second source and the second drain, the second gate ¶0048, 0058-0059 surrounding each of the second channels; and a second dielectric between the second channels and the second gate ¶0048, 0058-0059, the second dielectric surrounding each of the second channels in the second gate region ¶0048, 0056, 0058-0059, and wherein a number of first nanosheets is N (108aII/108bII/108cII/108dII), and a number of second nanosheets is N108aI/108bI/108cI/108dI, a lower most N-M second nanosheets forming the second channels Fig 16.
Regarding claim 2, as best understood, Cheng discloses wherein an upper surface of the first gate and an upper surface of the second gate are coplanar Fig 16.
Regarding claims 3 and 19, as best understood, Cheng discloses wherein the first NS structure further comprises first inner spacers Fig 17, 1102 formed between the first source and the first gate and formed between the first drain Fig 17, 1202 and the first gate, and the second NS structure further comprises second inner spacers Fig 16, 1102 formed between the second source Fig 16, 1202 and the second gate and formed between the second drain and the second gate Fig 16-17.
Regarding claims 4 and 20, as best understood, Cheng discloses wherein the first NS structure further comprises first upper spacers Fig 16, 802 formed above an upper most first channel and formed on the first source and drain sides of the first gate Fig 16-17, and the second NS structure further comprises second upper spacers Fig 16, 802 formed above an upper most second channel and formed on the second source and drain sides of the second gate Fig 16-17.
Regarding claims 6 and 22, as best understood, Cheng discloses wherein an upper surface of the first gate and upper surfaces of the first upper spacers are at a same first height, or an upper surface of the second gate and upper surfaces of the second upper spacers are at a same second height, or both Fig 16-17.
Regarding claims 7 and 23, as best understood, Cheng discloses wherein upper most M second nanosheets are floating Fig 15-16.
Regarding claim 8, as best understood, Cheng discloses wherein second upper spacers are formed on the second source and drain sides of the upper most M second nanosheets, and the second upper spacers are formed above and in direct contact with upper most second inner spacers Fig 12-15.
Regarding claim 24, as best understood, Cheng discloses wherein providing the substrate, forming the first NS structure Fig 3, and forming the second NS structure comprise: providing a nanosheet wafer with N nanosheets and N dummy layers alternatively stacked above the substrate Fig 3; forming a first dummy gate on an upper most nanosheet of the first gate region Fig 4; forming a second dummy gate on an upper most nanosheet of the second gate region Fig 4; etching the second logic area of the nanosheet wafer Fig 7, wherein upper most M nanosheets are removed on the second source side and on the second drain side while none of the nanosheets are removed in second gate region Fig 8; forming first upper spacers on the first source and the first drain sides of the first dummy gate Fig 8; forming second upper spacers on the second source and the second drain sides of the second dummy gate Fig 8; etching the first source and the first drain sides of the first logic area to expose the substrate Fig 11; etching the second source and the second drain sides of the second logic area to expose the substrate Fig 11; forming first inner spacers in the first gate region vertically below the first upper spacers Fig 11, the first inner spacers alternatively stacked with the nanosheets in the first gate region Fig 11; forming second inner spacers in the second gate region vertically below the second upper spacers Fig 11, the second inner spacers alternatively stacked with the nanosheets in the second gate region Fig 11; growing the first source on the first source side in the first gate region Fig 13; growing the second source on the second source side in the second gate region Fig 13; stripping the dummy layers and the first dummy gate in the first gate region Fig 14; stripping the dummy layers and the second dummy gate in the second gate region Fig 14; forming the first gate in the first gate region in place of the first dummy gate and the dummy layers Fig 16; and forming the second gate in the second gate region in place of the second dummy gate and the dummy layers Fig 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication No. 2018/0090624) in view of Sung et al (US Patent No. 10,170,484).
Regarding claims 5 and 21, as best understood, Cheng discloses wherein a dielectric constant of the first inner spacers is different from a dielectric constant of the first upper spacers, or a dielectric constant of the second inner spacers is different from a dielectric constant of the second upper spacers, or both ¶0046, 0050-0051.Cheng disclose all the limitations but silent on the inner spacers’ dielectric constant to be lower than the first upper spacer. Whereas Sung discloses wherein a dielectric constant of the first inner spacers is lower than from a dielectric constant of the first upper spacers, or a dielectric constant of the second inner spacers is lower than a dielectric constant of the second upper spacers, or both (column 11, lines 4-20 and column 12 lines 1-18). Cheng and Sung are analogous art because they are directed to semiconductor devices having GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the material used for the sidewall spacers and incorporate the teachings of Sung since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Claims 10-16, 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication No. 2018/0090624) in view of Tseng et al (US Publication No. 2019/0221639).
Regarding claims 10 and 25, Cheng discloses a gate-all-around (GAA) device and a method of fabricating a GAA device, comprising: a substrate Fig 16, 102; a first nanosheet (NS) structure formed above a first logic area of the substrate Fig 16, Nano device stack II; and a second nanosheet (NS) structure formed above a second logic area of the substrate Fig 16, Nano device stack I different from the first logic area Fig 16, Nano device stack II, wherein the first NS structure comprises: a plurality of first nanosheets Fig 16, 108 stacked above the substrate, the plurality of first nanosheets forming first channels ¶0059, a number of first channels being N, N≥2 Fig 16; a first source Fig 16, 1202 on the substrate on a first source side of the first channels Fig 16, the first source being electrically coupled with the first channels Fig 16; a first drain Fig 16, 1202 on the substrate on a first drain side of the first channels opposite the first source side Fig 16, the first drain being electrically coupled with the first channels Fig 16; a first gate Fig 16, 1602 on the substrate in a first gate region between the first source and the first drain Fig 16, the first gate surrounding each of the first channels Fig 16; and a first dielectric between the first channels and the first gate ¶0048, 0058-0059, the first dielectric surrounding each of the first channels in the first gate region¶0048, 0058-0059, wherein the second NS structure Fig 16, Nano device stack I comprises: one or more second nanosheets Fig 16, 108 (108aI/108bI/108cI/108dI) stacked above the substrate, forming second channels Fig 16, 108 (108aI/108bI/108cI), a second source Fig 16, 1202 on the substrate on a second source side of the second channels, the second source being electrically coupled with the second channels Fig 16; a second drain Fig 16, 1202 on the substrate on a second drain side of the second channels opposite the second source side, the second drain being electrically coupled with the second channels Fig 16; a second gate Fig 16, 1602 on the substrate in a second gate region between the second source and the second drain, the second gate ¶0048, 0058-0059 surrounding each of the second channels; and a second dielectric between the second channels and the second gate ¶0048, 0058-0059, the second dielectric surrounding each of the second channels in the second gate region ¶0048, 0058-0059,
second inner spacers Fig 16, 1102 formed between the second source and the second gate and formed between the second drain and the second gate; and second upper spacers Fig 16, 802 formed above an upper most second channel and formed on the second source and drain sides of the second gate, a dielectric constant of the second inner spacers being different from a dielectric constant of the second upper spacers¶0046, 0050-0051, and wherein a portion of the second inner spacers is formed above the upper most second channel Fig 16-17.Cheng discloses all the limitation but silent on one or more second nanosheets stacked above the substrate, the one or more second nanosheets forming second channels and the number of second channel being N-M. Whereas Tseng discloses one or more second nanosheets stacked above the substrate Fig 4 and Fig 12, the one or more second nanosheets forming second channels and the number of second channels being N-M Fig 12, 104 ¶0010, 0025, 1≤M<N. Cheng and Tseng are analogous art because they are directed to semiconductor devices having GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the channel region and incorporate the teachings of Tseng to provide a alternative device different function in an integrated structure.
Regarding claim 11, Cheng discloses wherein an upper surface of the first gate and an upper surface of the second gate are coplanar Fig 16.
Regarding claims 12 and 26, Cheng discloses wherein the first NS structure further comprises first inner spacers Fig 17, 1102 formed between the first source and the first gate and formed between the first drain Fig 17, 1202 and the first gate, and the second NS structure further comprises second inner spacers Fig 16, 1102 formed between the second source Fig 16, 1202 and the second gate and formed between the second drain and the second gate Fig 16-17.
Regarding claims 14 and 28, Cheng discloses wherein an upper surface of the first gate and upper surfaces of the first upper spacers are at a same first height, or an upper surface of the second gate and upper surfaces of the second upper spacers are at a same second height, or both Fig 16-17.
Regarding claim 15, Tseng discloses wherein a number of first nanosheets is N, and a number of second nanosheets is N-M Fig 12 ¶0010, 0025.
Regarding claim 16, Cheng discloses wherein the second upper spacers are formed on the second source and drain sides of the second gate above the upper most second nanosheet, and the second upper spacers are formed above and in direct contact with upper most second inner spacers Fig 12-15.
Regarding claim 29, Cheng discloses wherein providing the substrate, forming the first NS structure Fig 3, and forming the second NS structure comprise: providing a nanosheet wafer with N nanosheets and N dummy layers alternatively stacked above the substrate Fig 3; forming a first dummy gate on an upper most nanosheet of the first gate region Fig 4; forming a second dummy gate on an upper most nanosheet of the second gate region Fig 4; etching the second logic area of the nanosheet wafer Fig 7, wherein upper most M nanosheets are removed on the second source side and on the second drain side while none of the nanosheets are removed in second gate region Fig 8; forming first upper spacers on the first source and the first drain sides of the first dummy gate Fig 8; forming second upper spacers on the second source and the second drain sides of the second dummy gate Fig 8; etching the first source and the first drain sides of the first logic area to expose the substrate Fig 11; etching the second source and the second drain sides of the second logic area to expose the substrate Fig 11; forming first inner spacers in the first gate region vertically below the first upper spacers Fig 11, the first inner spacers alternatively stacked with the nanosheets in the first gate region Fig 11; forming second inner spacers in the second gate region vertically below the second upper spacers Fig 11, the second inner spacers alternatively stacked with the nanosheets in the second gate region Fig 11; growing the first source on the first source side in the first gate region Fig 13; growing the second source on the second source side in the second gate region Fig 13; stripping the dummy layers and the first dummy gate in the first gate region Fig 14; stripping the dummy layers and the second dummy gate in the second gate region Fig 14; forming the first gate in the first gate region in place of the first dummy gate and the dummy layers Fig 16; and forming the second gate in the second gate region in place of the second dummy gate and the dummy layers Fig 16. While Tseng discloses wherein the first are has N-M nanosheet and N-M+1 dummy layers alternatively stacked above the substrate in the second area Fig 4-5.
Regarding claim 30, Tseng discloses wherein providing the nanosheet wafer with N nanosheets and N dummy layers alternatively stacked above the substrate in the first logic area and with N-M nanosheets and N-M+1 dummy layers alternatively stacked above the substrate in the second logic area comprises: providing the nanosheet wafer with N nanosheets and N dummy layers alternatively stacked above the substrate; etching the second logic area of the nanosheet wafer, wherein upper most M nanosheets are removed in the second logic area; forming temporary spacers on sides of etched space of the second logic area; and growing a dummy layer within the etched space of the second logic area, the dummy layer being coplanar with upper most nanosheet Fig 4-11.
Claims 13 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication No. 2018/0090624) in view of Tseng et al (US Publication No. 2019/0221639) and Sung et al (US Patent No. 10,170,484).
Regarding claims 13 and 27, Cheng discloses wherein a dielectric constant of the first inner spacers is different from a dielectric constant of the first upper spacers¶0046, 0050-0051. Cheng disclose all the limitations but silent on the inner spacers’ dielectric constant to be lower than the first upper spacer. Whereas Sung discloses wherein a dielectric constant of the first inner spacers is lower than from a dielectric constant of the first upper spacers, or a dielectric constant of the second inner spacers is lower than a dielectric constant of the second upper spacers, or both (column 11, lines 4-20 and column 12 lines 1-18). Cheng and Sung are analogous art because they are directed to semiconductor devices having GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the material used for the sidewall spacers and incorporate the teachings of Sung since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication No. 2018/0090624) in view of Sung et al (US Patent No. 10,170,484) in further view of Mehadru et al (US Publication No. 2023/0317808).
Regarding claims 9 and 17, Cheng discloses all the limitation but silent on the use of the GAA device. Whereas Mehadru discloses wherein the GAA device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle ¶0161. Cheng and Mehadru are analogous art because they are directed to semiconductor devices having GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the use of the device of Cheng and incorporate the teachings of Mehadru as an alternative function and use Cheng’s device.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US Publication No. 2018/0090624) in view of Tseng et al (US Publication No. 2019/0221639) and Sung et al (US Patent No. 10,170,484) and in further view of Mehadru et al (US Publication No. 2023/0317808).
Regarding claims 9 and 17, Cheng discloses all the limitation but silent on the use of the GAA device. Whereas Mehadru discloses wherein the GAA device is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle ¶0161. Cheng and Mehadru are analogous art because they are directed to semiconductor devices having GAA devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Cheng because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the use of the device of Cheng and incorporate the teachings of Mehadru as an alternative function and use Cheng’s device.
Response to Arguments
Applicant's arguments filed 1/12/2026 have been fully considered but they are not persuasive.
In response to applicants’ argument (Pages 16-20) that the prior art of record does not teach the first dielectric layer and second dielectric layer between the channels, the examiner disagrees and find the argument unpersuasive. Cheng discloses the claimed limitations as described in Paragraph 0056-0059. See below.
[0056] Removal of the dummy gates exposes the nano device stack and, as shown in FIG. 15, enables the sacrificial layers to be selectively removed from the nano device stacks. The ends of the active layers (e.g., nano-sheets/wires—see above) are supported by the source and drain regions 1202. As provided above, by removing the sacrificial layers from the nano device stacks, the active layers are fully suspended which permits the replacement gate to be formed fully surrounding at least a portion of each of the active layers. This configuration is also referred to herein as a gate-all-around or GAA configuration.
[0058] Replacement gates 1602 are then formed in the trenches 1402. See FIG. 16. In the example shown, the replacement gates 1602 fully surround a portion of each of the active layers in a GAA configuration. According to an exemplary embodiment, the replacement gates 1602 are metal gates. Prior to depositing the metal gate, a gate dielectric (not shown) is typically deposited (e.g., conformally) on the active layers (e.g., nano-sheets/wires—see above) within the trenches 1402, such that the gate dielectric separates the active layers from the replacement gate. Suitable gate dielectrics for a replacement metal gate process include, but are not limited to, hafnium oxide (HfO.sub.2) or lanthanum oxide (La.sub.2O.sub.3). By way of example only, one possible configuration of the replacement gate includes a workfunction setting metal layer on the gate dielectric, and a filler gate metal layer on the workfunction setting metal layer. Suitable n-type workfunction setting metals include, but are not limited to, titanium nitride (TiN) and tantalum nitride (TaN). Suitable p-type workfunction setting metals include, but are not limited to, tungsten (W). Suitable filler gate metals include, but are not limited to, aluminum (Al). The portions of the active layers surrounded by the replacement gate serve as a channel region of the respective devices.
The applicant’s argument that the prior art mentioned that the gate dielectric is “not shown” suggest that the prior art’s figure does not illustrate (not show) the gate dielectric layer. It does not suggest that the gate dielectric layer is not present in the device. Also, the applicant is reminded that the replacement gate structure in a GAA configuration includes a gate dielectric layer as an insulation between the metal gate and the active region (nanowires/sheets/suspended channel).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
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