DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/22/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 11-12 are objected to because of the following informalities:
Claim 11 line 2 and claim 12 line 2 recites the limitations “the semiconductor chip” should change to “the semiconductor chips”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2014/0091344).
As for claim 1, Wang et al. disclose in Fig. 11 a method of manufacturing a semiconductor package, the method comprising:
disposing semiconductor chips 200 over a substrate 100 [0024];
forming a dam 300/492/496 surrounding the semiconductor chips [0024], the dam providing a reservoir (groove portion where 500b formed in) in a perimeter region of the substrate 100 (Fig. 11); and
forming a molding layer 500 encapsulating the semiconductor chips on the substrate (Fig. 11),
wherein extrusion 500b flowing out from the molding layer is contained in the reservoir while being blocked by the dam (Fig. 11, [0063]).
As for claim 2, Wang et al. disclose the method of claim 1, wherein the reservoir of the dam has a shape of a concave groove (Fig. 11).
As for claim 3, Wang et al. disclose the method of claim 1, wherein the dam includes: an inner dam 492/496; and an outer dam (vertical outer portion of 300) located apart from the inner dam (Fig. 11), wherein the reservoir is provided as a spacing between the inner dam and the outer dam (Fig. 11).
As for claim 5, Wang et al. disclose the method of claim 3, wherein each of the inner dam 492/496 and the outer dam 300 includes resin, a photoresist material, or a dielectric material ([0037] and [0061]).
As for claim 11, Wang et al. disclose the method of claim 1, wherein the semiconductor chip includes: at least one semiconductor die 200; and first connectors 600 connecting the semiconductor die to the substrate 100, and wherein the molding layer 500 fills a space between the at least one semiconductor die 200 and the substrate 100 and extends to separate the first connectors from each other (Fig. 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Im et al. (US 10,367,123).
As for claim 4, Wang et al. disclosed the method of claim 3, except each of the inner dam and the outer dam has a shape of a ring extending along a perimeter region of the substrate.
Im et al. teach in Fig. 8-9 and the related text each of the inner dam 230 and the outer dam 240 has a shape of a ring extending along a perimeter region of the substrate 200/201.
Wang et al. and Im et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by Im et al. in order to achieving uniform luminance characteristics.
Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Liu (US 2021/0384134).
As for claims 12 and 13, Wang et al. disclosed the method of claim 1, except the semiconductor chip includes: stacked semiconductor dies; and second connectors located between the semiconductor dies and connecting the semiconductor dies to each other, and wherein the molding layer fills a space between the semiconductor dies and extends to separate the second connectors from each other.
Liu teaches in Fig. 14 and the related text a plurality of stacked semiconductor dies 1402a/b/c/d; and second connectors (via connects between two dies) located between the semiconductor dies and connecting the semiconductor dies to each other (Fig. 14), and wherein the molding layer 405 fills a space between the semiconductor dies and extends to separate the second connectors from each other (Fig. 14).
Wang et al. and Liu are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by Liu et al. in order to increase density and reduce size of device.
Claim(s) 10 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. in view of Lin (2008/0054441).
As for claims 10 and 14, Wang et al. disclosed the method of claim 1, except the substrate comprises a semiconductor substrate, a wafer-type substrate, a panel-type substrate, or a printed circuit board (PCB); and the molding layer includes epoxy mold compound (EMC).
Lin et al. teaches in Fig. 10A-10B and the related text a substrate 56 comprises a semiconductor substrate [0124], a wafer-type substrate, a panel-type substrate, or a printed circuit board (PCB); and a molding layer 60 includes epoxy mold compound ([0126]-[0127]).
Wang et al. and Lin are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Wang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Wang et al. to include the limitations as taught by Lin et al. in order to provide suitable material for the substrate and encapsulation.
Allowable Subject Matter
Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: “forming the molding layer 140 includes: introducing a molding material in a molding cavity of a lower mold chase; loading the substrate over the lower mold chase so that the semiconductor chips face the molding cavity of the lower mold chase and an end surface of the dam is in contact with a portion of a surface of the lower mold chase; and flowing the molding material to cover the semiconductor chips”, as recited in claim 6.
Claims 7-9 depend among objected claim 6.
Conclusion
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/TRANG Q TRAN/ Primary Examiner, Art Unit 2811