DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: The word “effect” in the opening paragraph of the specification in the phrase “...effect the properties of the deposited oxide” is misused. The correct word is “affect”.
Appropriate correction is required.
Claim Objections
Claim 9 objected to because of the following informalities: In the phrase “...following the fusion bonding the smooth silicon surface...”, the word “of” should be inserted to read ” “...following the fusion bonding of the smooth silicon surface...”. Appropriate correction is required.
Claim 13 objected to because of the following informalities: “...growing the thermal silicon dioxide layer on the first later of silicon” with “later” instead of “layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 recites the limitation "the first structure" in the fourth line of the claim. There is insufficient antecedent basis for this limitation in the claim. For purpose of compact prosecution, “first structure” will be interpreted as “initial structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13, 15, 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Beyer et al (US 5,366,923 A, hereinafter “Beyer”).
Regarding Claim 13 – Beyer discloses a method for manufacturing an item (100, Beyer col. 5, lines 33-36) that exhibits a heat dissipating property (Beyer col. 6, lines 50-55), the method comprising: forming an initial structure (Beyer col. 5, lines 33-67, B in Fig. 4) that has a smooth silicon surface (132 overcomes the roughness of the diamond layer, Beyer col. 5, lines 41-43) and comprises a first layer of silicon (132, Beyer col. 5, lines 43-48) and a diamond layer (130, Beyer col. 5, lines 41-43), wherein the forming of the first structure comprises depositing the first layer of silicon on the diamond layer (Beyer col. 5, lines 36-39, Fig. 4); forming an intermediate structure that comprises the initial structure (substrate A, Beyer Fig. 4) and a layer of thermal silicon dioxide (126b, Beyer col. 6, lines 6-9) that has a smooth surface of thermal silicon dioxide (same function as 26b, Beyer col. 4, lines 40-42); wherein the forming of the intermediate layer comprises growing the thermal silicon dioxide layer on the first la(y)er of silicon Beyer col. 6, lines 3-4); wherein the method comprises protecting the diamond backside from oxidation during the growing (128 protects the back of 130, Beyer Fig. 4); and fusion bonding a substrate (120, Beyer col. 6, lines 12-14) to the smooth thermal silicon dioxide surface to provide the item (100, Beyer col. 6, lines 32-35, Fig. 6).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8, and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Lee et al (WO 2016007088 A1, hereinafter “Lee”).
Regarding Claim 1 – Beyer discloses a method for manufacturing an item (100, Beyer col. 5, lines 33-36) that exhibits a heat dissipating property (Beyer col. 6, lines 50-55), the method comprising: forming a first structure (Beyer col. 5, lines 33-67, B in Fig. 4) that has a smooth silicon surface (132 overcomes the roughness of the diamond layer, Beyer col. 5, lines 41-43) and comprises a first layer of silicon (132, Beyer col. 5, lines 43-48) and a diamond layer (130, Beyer col. 5, lines 41-43), wherein the forming of the first structure comprises depositing the first layer of silicon on the diamond layer (Beyer col. 5, lines 36-39, Fig. 4); forming a second structure (120, Beyer col. 6, lines 11-13) that has a smooth thermal silicon dioxide surface (same as 26a, Beyer col. 3, line 66 to col. 4, line 1) and comprises a layer of thermal silicon dioxide (126a, Beyer col. 6, lines 13-14) and a second layer of silicon (124, Beyer col. 6, lines 13-14), wherein the forming of the second structure comprises growing the layer of thermal silicon dioxide on the second layer of silicon (Beyer col. 6, lines 13-15); forming a third structure (100, Beyer col. 6, lines 31-34), wherein the forming of the third structure comprises fusion bonding the smooth silicon surface to the smooth thermal silicon dioxide surface (100, Beyer Fig. 6).
Beyer fails to disclose forming a fourth structure, wherein the forming of the fourth structure comprises removing the second layer of silicon from the third structure; and fusion bonding a substrate to the smooth thermal silicon dioxide surface to provide the item.
However, Lee discloses removing the second layer of silicon (256, Lee page 11, lines 26-30) from the third structure (shown in step 204, Lee Fig. 2b); and fusion bonding a substrate (260, Lee page 14, lines 6-9) to the smooth thermal silicon dioxide surface (254, Lee page11, lines 30-35) to provide the item (268, Lee page 15, lines 18-20, Fig. 2d).
Lee relates to Beyer as they are both in the field of bonding diamond layers to semiconductor substrates. Lee teaches removal of the handle substrate and bonding of a new substrate to enable integration of III-V compound semiconductors with silicon CMOS devices on a common platform (Lee page 3, lines 23-26). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to remove a handle substrate and bond a new substrate to the diamond-containing substrate.
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Regarding Claim 2 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the substrate comprises at least one material out of silicon, silicon carbide, indium phosphide, gallium nitride, gallium arsenide or silicon germanium (260 may comprise GaN, InGaP, AIGaAs, InGaAsP, InGaN, AIGaN, GaAs, InGaAs for example, on Si, Lee page 14, lines 16-21).
Lee teaches integration of III-V compound substrates for the advantage of enabling higher-power and/or higher-speed circuits than using silicon CMOS alone. (Lee page 2, lines 15-19). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using III-V compound substrates for the advantage of higher-power and/or higher-speed circuits.
Regarding Claim 3 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the substrate is a semiconductor substrate (260 may comprise GaN, InGaP, AIGaAs, InGaAsP, InGaN, AIGaN, GaAs, InGaAs for example, on Si, Lee page 14, lines 16-21).
Lee teaches integration of III-V compound substrates for the advantage of enabling higher-power and/or higher-speed circuits than using silicon CMOS alone. (Lee page 2, lines 15-19). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using III-V compound substrates for the advantage of higher-power and/or higher-speed circuits.
Regarding Claim 4 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses a smooth surface of the smooth thermal silicon dioxide surface and the smooth silicon surface exhibits a roughness that does not exceed 0.5 nanometer (less than 1 nm, Lee page 14, lines 14-16; this is an example of prima facie obviousness of an overlapping range, See MPEP 2144.05(I)).
Lee teaches causing the surface roughness to be smaller than 1 nm to facilitate fusion bonding (Lee page 14, lines 14-16). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to make the surface roughness less than 1 nm to facilitate fusion bonding.
Regarding Claim 6 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the forming of the first structure comprises polishing the first layer of silicon to provide the smooth silicon surface (Beyer col. 5, lines 65-67).
Regarding Claim 8 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the depositing the first layer of silicon on the diamond layer comprises at least one out of sputtering, Plasma-Enhanced Chemical Vapor Deposition (PECVD), or low pressure Chemical Vapor Deposition (LPCVD) (Beyer col. 5, lines 48-52).
Regarding Claim 10 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the removing of the second layer of silicon from the third structure comprises etching the second layer of silicon (Lee page 13, lines 23-31).
Lee teaches removal of silicon from the oxide surface to ensure removal of any remaining portions of the substrate material (Lee page 13, lines 23-26). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to include etching in the removal of the substrate material for the well-known benefit of complete removal.
Regarding Claim 11 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the removing of the second layer of silicon roughens the smooth thermal silicon dioxide surface to provide a rough thermal silicon dioxide surface, wherein the method comprises smoothing the rough thermal silicon dioxide surface (Lee page 17, line 29 to page 18, line 4).
Lee teaches smoothing the oxide surface by CMP to remove pinholes and cleaning in RCA solution (Lee page 17, line 31 to page 18, line 4. Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to remove pinholes from the oxide the benefit of solving pinholes in the oxide layer.
Regarding Claim 12 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee further discloses the substrate is a bare substrate or a patterned that comprises structures (Shown as bare substrate in Beyer Fig. 4-6).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Lee et al (WO 2016007088 A1, hereinafter “Lee”), and further in view of Enquist (WO 0126137 A2, hereinafter “Enquist”).
Regarding Claim 5 – Beyer modified by Lee discloses all the limitations of claim 3.
The combination of Beyer and Lee fails to disclose the forming of the first structure comprises polishing the first layer of silicon to provide the smooth silicon surface only when a roughness of the first layer exceeds 0.5 nanometers.
However, Enquist discloses the forming of the first structure comprises polishing the first layer of silicon to provide the smooth silicon surface only when a roughness of the first layer exceeds 0.5 nanometers (less than 5 Å most preferred, Enquist page 9, lines 9-10).
Enquist is analogous to Beyer and Lee because it is in the field of attaching a diamond layer to a semiconductor substrate by way of direct bonding. Enquist teaches the roughness of the bonding layer on the diamond is preferably less than 5 Å to enhance the bonding properties of the film (Enquist page 9, lines 9-10). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the roughness of the bonding layer on diamond less than 0.5 nm for the benefit of enhancing the bonding properties of the film.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Lee et al (WO 2016007088 A1, hereinafter “Lee”), and further in view of Tachibana et al (US 20060175293 A1, hereinafter “Tachibana”).
Regarding Claim 7 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee fails to disclose a thickness of the layer of thermal silicon dioxide when having the smooth thermal silicon dioxide surface, ranges between 100 and 200 nanometers.
However, Tachibana discloses the silicon dioxide layer thickness for such a direct bonding layer is about 200 nanometers (Tachibana [0043] ; this is an example of prima facie obviousness of an overlapping range, See MPEP 2144.05(I)).
Tachibana is analogous to Beyer and Lee in the field of direct bonding of materials incorporating a diamond layer. Tachibana discloses a silicon dioxide film of 200 nm for the purpose of direct bonding two silicon layers (Tachibana [0044]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using a silicon dioxide layer of about 200 nm to bond two silicon layers together.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Lee et al (WO 2016007088 A1, hereinafter “Lee”), and further in view of Tong et al (WO 0161743 A1, hereinafter “Tong”).
Regarding Claim 9 – Beyer modified by Lee discloses all the limitations of claim 1.
The combination of Beyer and Lee fails to disclose the fusion bonding of the smooth silicon surface to the smooth thermal silicon dioxide surface is executed at room temperature, wherein the method comprises annealing at 200 °C, following the fusion bonding the smooth silicon surface to the smooth thermal silicon dioxide surface.
However, Tong discloses the fusion bonding of the smooth silicon surface to the smooth thermal silicon dioxide surface is executed at room temperature, wherein the method comprises annealing below 200 °C, following the fusion bonding the smooth silicon surface to the smooth thermal silicon dioxide surface (Tong page 11, lines 9-11; this is an example of prima facie obviousness of an overlapping range, See MPEP 2144.05(I)).
Tong is in the field of direct bonding silicon surfaces with silicon dioxide, as are Beyer and Lee. Tong teaches a low temperature anneal below 200 °C to increase the bonding strength (Tong page 11, line 9). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to anneal below 200 °C after bonding for the well-known benefit of improving bonding strength.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Tachibana et al (US 20060175293 A1, hereinafter “Tachibana”).
Regarding Claim 14 – Beyer discloses all the limitations of claim 13.
Beyer fails to disclose the thermal silicon dioxide layer has thickness that ranges between 150-300 nanometers.
However, Tachibana discloses the silicon dioxide layer thickness for such a direct bonding layer is about 200 nanometers (Tachibana [0043]; this is an example of prima facie obviousness of an overlapping range, See MPEP 2144.05(I)).
Tachibana is analogous to Beyer and Lee in the field of direct bonding of materials incorporating a diamond layer. Tachibana discloses a silicon dioxide film of 200 nm for the purpose of direct bonding two silicon layers (Tachibana [0044]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider using a silicon dioxide layer of about 200 nm to bond two silicon layers together.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of MPEP 2144.05(I).
Regarding Claim 15 – Beyer discloses all the limitations of claim 13.
Beyer further discloses the first silicon layer has thickness that ranges between 70-150 nanometers (greater than 0.1 um, Beyer col. 5, lines 63-66; this is an example of prima facie obviousness of an overlapping range, See MPEP 2144.05(I)).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Caballero (US 5,164,220 A, hereinafter “Caballero”).
Regarding Claim 16 – Beyer discloses all the limitations of claim 13.
Beyer fails to disclose the forming of the initial structure comprises cleaning a surface of the diamond that interfaces with the first layer of silicon.
However, Caballero discloses the forming of the initial structure comprises cleaning a surface of the diamond that interfaces with the first layer of silicon (Caballero col. 3, lines 40-65).
Caballero is also concerned with deposition of silicon on diamond. Caballero teaches cleaning diamond before deposition of silicon to eliminate impurities (Caballero col. 3, lines 40-42). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to clean diamond before silicon deposition for the well-known benefit of eliminating impurities.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Beyer et al (US 5,366,923 A, hereinafter “Beyer”), in view of Kanakamedala (US 20160035742 A1, hereinafter “Kanakamedala”).
Regarding Claim 17 – Beyer discloses all the limitations of claim 13.
Beyer fails to disclose the growing of the thermal silicon dioxide layer is executed by applying a dry oxidation process.
However, Kanakamedala teaches oxidation of silicon can either be wet or dry (Kanakamedala [0039]).
Kanakamedala and Beyer both seek to form a silicon dioxide layer for further processing. Kanakamedala teaches that dry oxidation can be used two grow a thermal silicon dioxide layer directly from a silicon layer (Kanakamedala [0039]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use dry oxidation of silicon for the well-known benefit of producing thermal silicon dioxide from an exposed silicon surface.
Regarding Claim 18 – Beyer discloses all the limitations of claim 13.
Beyer fails to disclose the growing of the thermal silicon dioxide layer is executed by applying a wet oxidation process.
However, Kanakamedala teaches oxidation of silicon can either be wet or dry (Kanakamedala [0039]).
Kanakamedala and Beyer both seek to form a silicon dioxide layer for further processing. Kanakamedala teaches that wet oxidation can be used two grow a thermal silicon dioxide layer directly from a silicon layer (Kanakamedala [0039]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use wet oxidation of silicon for the well-known benefit of producing thermal silicon dioxide from an exposed silicon surface.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898