Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, with traverse, of claims 8-12 in the “Response to Restriction Requirement” filed on 10/31/2025 is acknowledged and entered by the Examiner.
Applicant’s arguments, in “Applicant Arguments/Remarks Made” with the reply “Response to Election / Restriction Filed” filed on 10/31/2025”, see “In the present case, the scope of claims 1-7 overlaps the scope claims 8-12. Said differently, the combination (claims 1-7) requires all the particulars of the subcombination (claims 8-12). As such, the two-way test for distinctness fails and restriction is not necessary” (remarks on page 4) have been fully considered.
The examiner has found the Applicant’s arguments to be persuasive. Therefore, the restriction requirement as set forth in the Office action mailed on 06/15/2016 is hereby withdrawn.
In view of the above noted withdrawal of the restriction requirement, applicant is advised that if any claim presented in a combination or divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once a restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 122, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
This office action consider claims 1-20 pending for prosecution, wherein claims 13-20 are withdrawn from further consideration, and claims 1-12 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hekmatshoartabari et al. (US 20210349691 A1; hereinafter Hekmatshoartabari).
Regarding claim 1, Hekmatshoartabari teaches a semiconductor device (see the entire document, specifically Fig. 1a; [0005+], and as cited below), comprising:
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a metal insulator metal capacitor (MIM capacitor) ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) between adjacent stacked nanosheet field effect transistors (Fig. 22b; see [0085, 0097-0099, 0110]; see Annotated Fig. 22b, above).
Regarding claim 2, Hekmatshoartabari teaches all of the features of claim 1.
Hekmatshoartabari further teaches wherein the adjacent stacked nanosheet field effect transistors (Fig. 22b; see [0085, 0097-0099, 0110]; see Annotated Fig. 22b, above) each comprise: a first nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) on a substrate comprising alternating layers of a first work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact) and a semiconductor channel material ({131/133}; Fig. 22b; see [0097-0099, 0110]) vertically aligned and stacked one on top of another.
Regarding claim 3, Hekmatshoartabari teaches all of the features of claim 2.
Hekmatshoartabari further teaches wherein the adjacent stacked nanosheet field effect transistors (Fig. 22b; see [0085, 0097-0099, 0110]; see Annotated Fig. 22b, above) each comprise: a second nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) comprising alternating layers of a second work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact) and the semiconductor channel material ({131/133}; Fig. 22b; see [0097-0099, 0110]) vertically aligned and stacked one on top of another, wherein the second nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) vertically aligned and stacked on top of the first nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above).
Regarding claim 4, Hekmatshoartabari teaches all of the features of claim 3.
Hekmatshoartabari further comprising: a top electrode (see electrode connection on Fig. 23f connected to 330; Fig. 23f; see [0091-0093, 0110]) of the MIM capacitor connected to an inner plate ({330}; Fig. 22b, 23f; see [0091-0093, 0110]) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]), wherein a horizontal upper surface of the top electrode (see electrode connection on Fig. 23f connected to 330; Fig. 23f; see [0091-0093, 0110]) is vertically aligned with an upper horizontal surface of a contact to a second source drain (253; Fig. 22b, 23f; see [0091-0093, 0110]) of the second nanosheet stack.
Regarding claim 5, Hekmatshoartabari teaches all of the features of claim 3.
Hekmatshoartabari further comprising: a lower electrode ({310}; Fig. 22b, 23f; see [0091-0093, 0110]) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) connected to an outer plate (100; [0059]; silicon substrate with interconnects) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]), wherein a lower horizontal surface of the lower electrode is vertically aligned with a contact to a first source drain (256; Fig. 22b, 23f; see [0091-0093, 0110]) of the first nanosheet device.
Regarding claim 6, Hekmatshoartabari teaches all of the features of claim 1.
Hekmatshoartabari further teaches wherein a height of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) is greater than a height of the adjacent stacked nanosheet field effect transistors (see Fig. 22b).
Regarding claim 7, Hekmatshoartabari teaches all of the features of claim 2.
Hekmatshoartabari further comprising: a liner ({240}; Fig. 22b; see [0083]) separating the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) from the first work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact).
Regarding claim 8, Hekmatshoartabari teaches a semiconductor device (see the entire document, specifically Fig. 1a; [0005+], and as cited below), comprising:
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a metal insulator metal capacitor (MIM capacitor) ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) between adjacent stacked nanosheet field effect transistors (Fig. 22b; see [0085, 0097-0099, 0110]; see Annotated Fig. 22b, above),
wherein the adjacent stacked nanosheet field effect transistors (Fig. 22b; see [0085, 0097-0099, 0110]; see Annotated Fig. 22b, above) each comprise:
a first nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) on a substrate comprising alternating layers of a first work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact) and a semiconductor channel material ({131/133}; Fig. 22b; see [0097-0099, 0110]) vertically aligned and stacked one on top of another; and
a second nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) comprising alternating layers of a second work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact) and the semiconductor channel material ({131/133}; Fig. 22b; see [0097-0099, 0110]) vertically aligned and stacked one on top of another, wherein the second nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above) vertically aligned and stacked on top of the first nanosheet stack ({131/133, 350}; Fig. 22b; see [0097-0099, 0110]; see Annotated Fig. 22b, above).
Regarding claim 9, Hekmatshoartabari teaches all of the features of claim 8.
Hekmatshoartabari further comprising: a top electrode (see electrode connection on Fig. 23f connected to 330; Fig. 23f; see [0091-0093, 0110]) of the MIM capacitor connected to an inner plate ({330}; Fig. 22b, 23f; see [0091-0093, 0110]) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]), wherein a horizontal upper surface of the top electrode (see electrode connection on Fig. 23f connected to 330; Fig. 23f; see [0091-0093, 0110]) is vertically aligned with an upper horizontal surface of a contact to a second source drain (253; Fig. 22b, 23f; see [0091-0093, 0110]) of the second nanosheet stack.
Regarding claim 10, Hekmatshoartabari teaches all of the features of claim 8.
Hekmatshoartabari further comprising: a lower electrode ({310}; Fig. 22b, 23f; see [0091-0093, 0110]) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) connected to an outer plate (100; [0059]; silicon substrate with interconnects) of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]), wherein a lower horizontal surface of the lower electrode is vertically aligned with a contact to a first source drain (256; Fig. 22b, 23f; see [0091-0093, 0110]) of the first nanosheet device.
Regarding claim 11, Hekmatshoartabari teaches all of the features of claim 8.
Hekmatshoartabari further teaches wherein a height of the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) is greater than a height of the adjacent stacked nanosheet field effect transistors (see Fig. 22b).
Regarding claim 12, Hekmatshoartabari teaches all of the features of claim 8.
Hekmatshoartabari further comprising: further comprising: a liner ({240}; Fig. 22b; see [0083]) separating the MIM capacitor ({310, 320, 330}; Fig. 22b, 23f; see [0091-0093, 0110]) from the first work function metal ({350}; Fig. 22b; see [0097-0099, 0110]; see [0098], where layer 350 comprises of a gate dielectric, a work function metal and a metal contact).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898