Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on November 7, 2023, May 30, 2024, November 27, 2024, June 18, 2025, and May 14, 2026, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed May 14, 2026 has been entered. Claims 1, 4-12, 14-18, 29-32, & 34-36 remain pending in the application. Claims 1, 4, 6, 9, 16, 29, & 30-31 have been amended. Claims 2-3, 13, 19-28, & 33 remain cancelled. Claims 34-36 are new. Applicant’s amendments to the Claims have overcome each and every 35 U.S.C. § 112(b) rejections previously set forth in the Non-Final Office Action mailed February 23, 2026, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments filed May 14, 2026, please refer to Applicant’s remarks pp. 11-26, have been entered and fully considered. In light of the amendments, the Applicant has presented a set of arguments pointing out their rationale of how the prior art reference(s) made of record in the most recent Non-Final Office Action, mailed February 23, 2026, do not teach, suggest, and/or disclose the currently recited claim limitations. Applicant’s arguments have been fully considered but they are not persuasive.
Applicant in their submitted response, please refer to pp. 11-18 of Applicant’s remarks, presents the argument that the prior art reference(s) Khamesra et al. (US2024/0280645A1), in view of Abdesselam (US2023/0014264A1), and further in view of Djenguerian et al. (US2014/0204624A1), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination the amended limitation(s), “detect whether an error is present in the system, and (iii) in response to detecting the error, report the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold, wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding, and wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer.”, recited in amended independent claim 1.
In light of the amendments in independent claim 1, new ground(s) of rejection(s) is/are made over Khamesra, in view of Abdesselam, in view of Djenguerian, in view of Kim et al. (US9825543B1), and further in view of Wong et al. (US2019/0348920A1). The Examiner respectfully disagrees with the Applicant’s contentions that Khamesra, in view of Abdesselam, in view of Djenguerian, now in light of new prior art reference(s) Kim, and further in view of Wong, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s) for the above stated amendments in independent claim 1. The prior art references further disclose the additional limitations that have been amended and included in independent claim 1, and meet these requirements. Therefore, Applicant’s arguments are unconvincing and the rejection(s) of amended independent claim 1, and dependent claims 4-8 & 34-35, which depend from and incorporate the limitations of amended independent claim 1, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Applicant in their submitted response, please refer to pp. 18-20 of Applicant’s remarks, presents the argument that the motivation to combine rationale for obviousness ”does not satisfy the requirement to provide articulated reasoning with a rational underpinning to support the legal conclusion…”, further expanding into six different reasonings and explanations.
The Examiner appreciates the reasonings and explanations provided, but respectfully disagrees. The motivation to combine rationales provided in the previous Non-Final Office Action, pp. 14-15 & 17-20, were based on MPEP 2143(A), 2143(C), 2143(D), 2143(E), 2143(G), and MPEP 2143.02. In light of the amendments in independent claim 1, the motivation to combine rationales have been updated with the newly included prior art references, Kim, and further in view of Wong.
Applicant in their submitted response, please refer to pp. 20-21 of Applicant’s remarks, presents the argument that the prior art reference(s) Freeman et al. (US2016/0126852A1), in view of Abdesselam (US2023/0014264A1), and further in view of Djenguerian et al. (US2014/0204624A1), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination the amended limitation(s), “a second control interface that is coupled to the secondary winding of the transformer, the second control interface being configured to: (i) power an external device with power that is received via the secondary winding, (ii) detect whether an error is present in the external device, and (iii) in response to detecting the error, report the error to the first control interface by reducing a level of the electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer.” The examiner would like to point out that amended independent claim 9 on pg. 4 of Amended Claims, recites “a second control interface that is coupled to the secondary winding of the transformer, the second control interface being configured to: (i) power an external device with power that is received via the secondary winding, (ii) detect whether an error is present in the external device, and (iii) in response to detecting the error, causing an electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer; wherein the electrical current through the primary winding is caused to drop by changing a load on the transformer, the load being changed by changing a resistance of a transistor whose conduction terminals are coupled to respective ends of the secondary winding in parallel with a device that is powered with the transformer.” Further, amended independent claim 9 on pg. 4 of Amended Claims, has removed the following claim limitations, “report the error to the first control interface by changing a level of the electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer.” Independent Claim 9 was examined using the amendments provided on pg. 4 of Amended Claims.
In light of the amendments in independent claim 9, new ground(s) of rejection(s) is/are made over Freeman, in view of Abdesselam, in view of Djenguerian, in view of Kim et al. (US9825543B1), and further in view of Wong et al. (US2019/0348920A1). The Examiner respectfully disagrees with the Applicant’s contentions that Freeman, in view of Abdesselam, in view of Djenguerian, now in light of new prior art reference(s) Kim, and further in view of Wong, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s) for the above stated amendments in independent claim 9. The prior art references further disclose the additional limitations that have been amended and included in independent claim 9, and meet these requirements. Therefore, Applicant’s arguments are unconvincing and the rejection(s) of amended independent claim 9, and dependent claims 10-12, & 14-18, which depend from and incorporate the limitations of amended independent claim 9, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Applicant in their submitted response, please refer to pp. 18-20 of Applicant’s remarks, presents the argument that the motivation to combine rationale for obviousness ”does not satisfy the requirement to provide articulated reasoning with a rational underpinning to support the legal conclusion…”, further expanding into six different reasonings and explanations.
The Examiner appreciates the reasonings and explanations provided, but respectfully disagrees. The motivation to combine rationales provided in the previous Non-Final Office Action, pp. 29-44, were based on MPEP 2143(A), 2143(C), 2143(D), 2143(E), 2143(G), and MPEP 2143.02. In light of the amendments in independent claim 9, the motivation to combine rationales have been updated with the newly included prior art references, Kim, and further in view of Wong.
Applicant in their submitted response, please refer to pp. 21-22 of Applicant’s remarks, presents the argument that the prior art reference(s) Freeman et al. (US2016/0126852A1), in view of Abdesselam (US2023/0014264A1), and further in view of Djenguerian et al. (US2014/0204624A1), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination the amended limitation(s), “a transistor that is coupled between the transformer and the second control interface, the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding, and a gate that is coupled to the second control interface wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance of a path between the source and the drain of the transistor.”, recited in amended dependent claim 16.
In light of the amendments in dependent claim 16, new ground(s) of rejection(s) is/are made over Freeman, in view of Abdesselam, in view of Djenguerian, in view of Kim et al. (US9825543B1), and further in view of Wong et al. (US2019/0348920A1). The Examiner respectfully disagrees with the Applicant’s contentions that Freeman, in view of Abdesselam, in view of Djenguerian, now in light of new prior art reference(s) Kim, and further in view of Wong, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s) for the above stated amendments in dependent claim 16. The prior art references further disclose the additional limitations that have been amended and included in dependent claim 16, and meet these requirements. Therefore, Applicant’s arguments are unconvincing and the rejection(s) of amended dependent claim 16, which depends from and incorporate the limitations of amended independent claim 9, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Applicant in their submitted response, please refer to pg. 22 of Applicant’s remarks, presents the argument that the prior art reference(s) Vemuri et al. (US2017/0033698A1), in view of Abdesselam (US2023/0014264A1), and further in view of Yang et al. (US2022/0155383A1), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination the amended limitation(s), “causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold, wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding, and wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer.”, recited in amended independent claim 29.
In light of the amendments in independent claim 29, new ground(s) of rejection(s) is/are made over Vemuri, in view of Abdesselam, in view of Yang, in view of Kim et al. (US9825543B1), and further in view of Wong et al. (US2019/0348920A1). The Examiner respectfully disagrees with the Applicant’s contentions that Vemuri, in view of Abdesselam, in view of Yang, now in light of new prior art reference(s) Kim, and further in view of Wong, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s) for the above stated amendments in independent claim 29. The prior art references further disclose the additional limitations that have been amended and included in independent claim 29, and meet these requirements. Therefore, Applicant’s arguments are unconvincing and the rejection(s) of amended independent claim 29, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Applicant in their submitted response, please refer to pp. 18-20 of Applicant’s remarks, presents the argument that the motivation to combine rationale for obviousness ”does not satisfy the requirement to provide articulated reasoning with a rational underpinning to support the legal conclusion…”, further expanding into six different reasonings and explanations.
The Examiner appreciates the reasonings and explanations provided, but respectfully disagrees. The motivation to combine rationales provided in the previous Non-Final Office Action, pp. 63-74, were based on MPEP 2143(A), 2143(C), 2143(D), 2143(E), 2143(G), and MPEP 2143.02. In light of the amendments in independent claim 29, the motivation to combine rationales have been updated with the newly included prior art references, Kim, and further in view of Wong.
Applicant in their submitted response, please refer to pp. 22-26 of Applicant’s remarks, presents the argument that the prior art reference(s) Ahmed et al. (US2024/0283352A1), in view of Freeman et al. (US2016/0126852A1), and further in view of Abdesselam (US2023/0014264A1), as cited by the Applicant, do not teach, suggest, and/or disclose individually or in combination the amended limitation(s), “wherein the electrical current through the primary winding is caused to fall into the threshold range by changing a load on the transformer, the load being changed by changing a resistance of an element that is coupled to the secondary winding,” and further the previously recited claim limitation(s), “wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range.”, recited in amended independent claim 30.
In light of the amendments in independent claim 30, new ground(s) of rejection(s) is/are made over Ahmed, in view of Freeman, in view of Abdesselam, in view of Kim et al. (US9825543B1), in view of Wong et al. (US2019/0348920A1), and further in view of Knoedgen (US2013/0235632A1). The Examiner respectfully disagrees with the Applicant’s contentions that Ahmed, in view of Freeman, in view of Abdesselam, now in light of new prior art reference(s) Kim, in view of Wong, and further in view of Knoedgen, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s) for the above stated amendments in independent claim 30. The prior art references further disclose the additional limitations that have been amended and included in independent claim 30, to include previously cited claim limitation(s), and meet these requirements. Therefore, Applicant’s arguments are unconvincing and the rejection(s) of amended independent claim 30, and dependent claims 31-32, & 36, which depend from and incorporate the limitations of amended independent claim 30, are respectively maintained. are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Applicant in their submitted response, please refer to pp. 22-26 of Applicant’s remarks, presents the argument that the motivation to combine rationale for obviousness ”…further noted that the rejection of claim 30 is prima facie deficient.”
The Examiner appreciates the reasonings and explanations provided, but respectfully disagrees. The motivation to combine rationales provided in the previous Non-Final Office Action for independent claim 30, pp. 74-84, were based on MPEP 2143(A), 2143(C), 2143(D), 2143(E), 2143(G), and MPEP 2143.02. In light of the amendments in independent claim 30, the motivation to combine rationales have been updated with the newly included prior art references, Kim, in view of Wong, and further in view of Knoedgen.
Claim Objections
Applicant is advised that should claim 34 be found allowable, claim 35 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30-32 & 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 30 recites the limitation "and wherein causing the level of the electrical current…" in line 18, without previous disclosure of “the level…”, resulting in a lack of antecedent basis for this claim. For examination purposes, examiner interprets “the level…” to refer to “a level…”. Claims 31-32 & 36, which do not rectify the defect, are rejected by virtue of dependence to claim 30.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, & 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Khamesra et al. (US 2024/0280645 A1, Fil. Date Jun. 12, 2023, hereinafter, Khamesra), in view of Abdesselam (US 2023/0014264 A1 Fil. Date Jul. 13, 2022, hereinafter, Abdesselam), in view of Djenguerian et al. (US 2014/0204624 A1, Pub. Date Jul. 24, 2014, hereinafter, Djenguerian), in view of Kim et al. (US 9825543 B1, Pat. Date Nov. 21, 2017, hereinafter, Kim), and further in view of Wong et al. (US 2019/0348920 A1, Pub. Date Nov. 14, 2019, hereinafter, Wong).
Regarding independent claim 1, Khamesra, teaches:
A system (Figs. 1-2; [Abstract] & [0020]), comprising:
a transformer having a primary winding and a secondary winding (Figs.1-2; [0020]-[0027]: “a flyback transformer 106 having a first winding (NP1) on a primary side 108” and “a secondary winding (NS) on a secondary side 110”), the primary winding and the secondary winding being arranged to power an external load (Figs. 1-2; [0020]-[0027]: discloses the flyback transformer 106 with a primary side 108 and the secondary side 110 that provides a DC output voltage to an output port/connector 128, which is the external load);
a first control interface that is coupled to the primary winding, the first control interface being arranged to: (i) detect an electrical current through the primary winding ([0020] & [0024]: primary-side controller 102 connects to “resistive element 120 (RCS)…to sense a primary side current (IPR)) and (ii) output a fault signal in response to detecting that the electrical current through the primary winding has crossed a threshold ([0004]-[0008], [0017]-[0018], [0020], [0024]-[0025], [0027]-[0029], [0042], [0049], [0052], [0055]-[0057], [Claim 1], [Claim 9], [Claim 14], [Claim 15], [Claim 17], & [Claim 18]: primary-side controller 102 is arranged to “disable the power switch 118 if an over voltage condition is detected” or if preset thresholds are crossed); and
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Khamesra, and Abdesselam, are silent in regard to:
a second control interface that is coupled to the secondary winding, the second control interface being configured to: (i) provide an electrical current received from the transformer to the external load, (ii) detect whether an error is present in the system, and (iii) in response to detecting the error, report the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold,
However, Kim, further teaches:
a second control interface that is coupled to the secondary winding ([Abstract], [Col. 1, ll. 25-28], & [Col. 3, ll. 26-35]), the second control interface being configured to: (i) provide an electrical current received from the transformer to the external load (Figs. 1,2, & 3; [Abstract], [Col. 1, ll. 32-38], [Col. 2, ll. 2-11 & 16-28], [Col. 3, ll. 18-21, 26-39, & 53-64], [Col. 4, ll. 57-63], [Claim 1], & [Claim 6]), (ii) detect whether an error is present in the system ([Abstract], [Col. 1, ll. 25-28 & 32-38], [Col. 2, ll. 2-11 & 16-28], [Col. 3, ll. 18-21, 26-39, & 53-64], [Col. 4, ll. 57-63], [Claim 1], & [Claim 6]: The secondary-side control circuit 140 detects whether the output voltage Vout is normal, “The latch circuit 170 receives a fault signal SFAULT and detects whether a fault event occurs”), and (iii) in response to detecting the error, report the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold ([Col. 3, ll. 18-21, 26-45, & 49-67], [Col. 4, ll. 1-5, 23-25, & 46-56], [Col. 6, ll. 60-67], & [Col. 7, ll. 1-2 & 17-32]): when the fault is detected, the secondary side communicates the error to the primary side. The primary side stops normal switching, which “is referred that the switching of the current switch 120 is completely stopped, or the switching of the current switch 120 is controlled by pulse-width modulation (PWM) signal with smaller pulse width in a burst mode”, dropping the primary current into the intermediate window),
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the isolated power converter system of Khamesra to include the secondary-side fault detection and primary-side burst-mode response taught by Kim. This combination teaches a system comprising a transformer having a primary and secondary winding powering an external load, a first control interface coupled to the primary winding that detects an electrical current and outputs a fault signal upon crossing a threshold, and a second control interface coupled to the secondary winding that provides current to the load and detects whether an error is present. Further, Kim teaches, in response to detecting the error, the second control interface reports the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold via a burst mode ([Col. 3, ll. 26-45]). A POSITA would be motivated to incorporate Kim’s secondary-side error detection and primary burst-mode reporting into Khamesra’s control architecture ([0020]-[0028]) to provide a reliable, low-power standby state that safely handles a fault without completely shutting down the system. Applying this known technique to improve similar devices yields the predictable variation results of a system that securely drops primary current to an intermediate maintenance window upon detecting secondary-side anomalies, thus yielding expected predictable results (KSR).
Khamesra, Abdesselam, Djenguerian, and Kim, are silent in regard to:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding, and
wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer.
However, Wong, further teaches:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer ([0008]-[0009], [0017], [0020], [0029], [0035]-[0045], [0047]-[0048], & [0058]: teaches controlling the switching state on the secondary side directly regulates the transformer’s current draw as seen on the primary side), the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding (Fig. 1; [0003], [0012], [0021]-[0022], [0025]-[0026], [0029], [0039]-[0050]: the element coupled to the secondary winding is a solid-state switch, “The rectifier is realized by a transistor, as shown in Fig. 1, a metal-oxide-semiconductor field effect transistor (MOSFET) serves as the rectifier MSR…”. Modulating the MOSFET between its ON and OFF states operates changing its internal channel resistance, restricting or allowing current flow to alter the transformer’s draw), and
wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer ([0015] & [0051]-[0053]: identifies the parasitic effects and oscillating current that maintain a baseline minimum current draw even when secondary load current crosses zero, the oscillating current represents the minimum baseline draw required by the transformer’s internal parasitics).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivating experimentation and optimization. Building upon the combined system of Khamesra and Kim, it would have been obvious to further incorporate the secondary-side resistance modulation and transformer characteristics by Wong. Wong addresses the limitation wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, which is changed by increasing a resistance of an element that is coupled to the secondary winding by modulating a MOSFET switch MSR ([0039]). Wong, further identifies the parasitic and internal non-idealities that maintain a baseline current even when the load is disconnected ([0052]), teaching the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer. A POSITA would be motivated to incorporate Wong’s solid-state resistance modulation to achieve precise, primary-side current manipulation across the isolation barrier without relying on the physical optical coupler utilized in Kim. Further, a POSITA would recognize this substitution of an optocoupler with direct secondary-side load modulation as a predictable variation that utilizes the inherent physical non-idealities of the transformer to establish a minimum baseline current during the fault signaling phase, thus yielding expected predictable results (KSR).
Regarding dependent claim 4, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0029]-[0030] & [0041]), wherein the threshold is less than a lower bound (Fig. 3; [0005] & [0029]-[0033]): “the controller 208 issues an RSENSE short detect interrupt responsive to the output of the low-side CSA 206 being reduced (e.g., lower than a first threshold) and the turn-on pulse of the PWM control signal being wider (e.g., greater than a second threshold)”, teaches a fault detection method based on the measured output current falling below a specific threshold, this is the definition of an undercurrent threshold set below the normal operating range, where the fault detection is triggered when the measured output is abnormally low, Fig. 3, illustrates in the flowchart the first step of the fault detection method (block 304) is the comparison: “IOUT < CURRENT THRESHOLD?”) of a normal operating range (Fig. 3; [0005] & [0029]-[0033]: “at 304, the output current, IOUT, is compared to a threshold”, checks if current < threshold, “at 306, the PWM width is compared to a PWM threshold”, checks if PWM width > threshold, and “if the conditions of 204 and 206 are both met at 308, an RSENSE fault interrupt is raised”, step 308 fault triggered only if both conditions persist, teaches a fault detection method based on the measured output current falling below a specific threshold, this is the definition of an undercurrent threshold set below the normal operating range, where “the output of the low-side CSA 206 being reduced (e.g., lower than a first threshold)…”) of the electrical current draw of the transformer (Figs. 2-3; [0022] & [0027]-[0033]: 134, RSENSE 134, “a first node of the RSENSE resistor 134 is connected to a current sensing negative pin (CSN) 144 of the secondary-side controller 104, and a second node connected to the negative terminal of the DC output and to a current sensing positive pin (CSP) 146, to enable the secondary-side controller 104 to sense the output current, IOUT, from the power converter 100”) and greater than the minimum current draw of the transformer (Fig. 3; [0029]-[0033]: “if the fault count meets a threshold, such as N, as 314, the RSENSE fault condition is raised at 316, such as by the firmware 214 and the method 300 stops at 318” and “if the fault count does not meet a threshold at 316, a wait interval, such as M ms, is implemented at 320 and the method 300 returns to 304 and 306 to determine if the RSENSE fault persists” and “current through the RSENSE resistor 134 is lower than the first threshold and the pulse-width counter is higher than the second threshold, the controller 208 raises an interrupt to indicate an RSENSE short fault”, where “firmware 214 checks for the persistence of this interrupt multiple times (e.g., present for N-times sampled after intervals of M ms) before asserting an RSENSE short condition signal”, the core teaching is to detect a fault by identifying when the measured current is less than a predetermined threshold, which by definition, is less than the lower bound of the normal operating range, purpose is to detect an abnormally low reading, but would have to be greater than a minimum current to be a functional electronic measurement).
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Regarding dependent claim 5, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0029]-[0030], [0041] & [0046]),
Khamesra, in combination with Abdesselam, are silent in regard to:
wherein the first control interface is formed on a first semiconductor die and the second control interface is formed on a second semiconductor die.
However, Djenguerian, further teaches:
wherein the first control interface is formed on a first semiconductor die ([0031]-[0032]: discloses the primary controller (first control interface) formed on a first integrated circuit die) and the second control interface is formed on a second semiconductor die ([0031]-[0032]: discloses the secondary controller (second control interface) formed on a distinct second die to ensure they are “galvanically isolated from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date, where Khamesra discloses that the system’s modules (primary/secondary controller) may be implemented on different semiconductor dies, Djenguerian teaches separating the primary and secondary controllers onto different dies to maintain galvanic isolation, therefore applying the dual-die configuration of Djenguerian to the USB-PD system of Khamesra to achieve the necessary galvanic isolation and voltage handling capabilities required by a transformer-based design, combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 6, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0029]-[0030], [0041] & [0046]),
Khamesra, is silent in regard to:
wherein the element includes a transistor that is coupled between the transformer and the second control interface, the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding and a gate that is coupled to the second control interface,
However, Abdesselam, in combination with Djenguerian, further teach:
wherein the element includes a transistor that is coupled between the transformer and the second control interface (Abdesselam: [0061]: discloses a stop element 26 which is a switch/transistor driven by the power and fault detection controller 21, acting as the second control interface; Djenguerian: Fig. 1; [0020]-[0021], [0025], [0029], [0035], [0038], [0048]-[0049], [0051], [0101], [Claim 4], [Claim 13], & [Claim 17]: further corroborates the solid-state implementation with secondary-side switch 704),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the current control hardware logic taught by Djenguerian/Abdesselam. Djenguerian reinforces the transistor structural arrangement, to a solid-state implementation of the transistor coupled between the transformer and the second control interface, detailing the use of a switch 704 with the first power circuit 152 to manage the secondary load. A POSITA would be motivated to utilize Djenguerian’s parallel switch topology to ensure that the secondary controller maintains sufficient operation power and stability while the load is being modulated. This integration represents a substitution of one known secondary-side switching topology for another, producing the predictable results of maintaining system stability and component power during active signaling states (KSR).
However, Abdesselam, further teaches:
the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding and a gate that is coupled to the second control interface (Fig. 1; [0061]: teaches the physical parallel connection, “the stop element 26 may be a switch connected in parallel with the secondary winding 34 and driven by the power and fault detection controller 21”, connecting a transistor directly in parallel with the winding inherently dictates that its source and drain are coupled across the first and second ends of the winding, with the gate coupled to the controller, further illustrated in Fig. 1),
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter system of Khamesra to include the secondary-side stop element switch taught by Abdesselam. This combination discloses the stop element mechanism includes a transistor that is coupled between the transformer and the second control interface, having a source and drain coupled across the secondary winding and a gate coupled to the control interface. Abdesselam discloses a stop element 26 switch connected directly in parallel with the secondary winding 34 and driven by controller 21. The motivation to incorporate Abdesselam’s parallel switch into Khamesra’s architecture is to establish a direct signaling pathway across the secondary winding that can manipulate the transformer’s magnetic flux. A POSITA would recognize this substitution of adding a parallel control switch as a known technique to improve similar devices, predictably allowing the secondary controller to immediately modulate the transformer’s behavior across the isolation barrier (KSR).
Khamesra, Abdesselam, Djenguerian, and Kim, are silent in regard to:
wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance of a path between the source and the drain of the transistor.
However, Wong, further teaches:
wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance of a path between the source and the drain of the transistor ([0039]-[0040], [0064], & [0066]: teaches applying a control voltage to the gate terminal of a metal-oxide-semiconductor field effect transistor (MOSFET) switch MSR coupled to the secondary winding. Modulating this element towards an off-state physically operates by changing the voltage applied at its gate to increase its channel resistance between the source and drain, safely restricting the current to report the error across the isolation barrier).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the parallel transistor using the physical resistance-modulation mechanics detailed by Wong. Wong teaches the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance path between the source and the drain of the transistor, by teaching the active modulation of a MOSFET’s gate to restrict channel current flow. The secondary controller detects a fault, and instead of just shutting down, gently increasing the resistance the gate of the parallel transistor. By turning this transistor into a variable resistor directly across the winding, it safely alters the magnetic flux of the transformer, which forces the primary-side current to drop, sending an error signal across the isolation barrier without needing a physical wire or optical coupler. A POSITA would be motivated to utilize Wong’s solid-state resistance modulation on the parallel transistor to drop the primary current into a stable signaling window, rather than creating a hard short circuit that could cause a destructive overcurrent spike. This combination represents a predictable variation combining known electrical control methods, predictably allowing the secondary controller to safely regulate the current during the active fault signaling phase (KSR).
Regarding dependent claim 7, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0027]-[0030], [0041] & [0046]), further comprising a power switch (Figs. 1-2; [0022] & [0027]: 118 & 132, where “a synchronous rectifier (SR) field effect transistor 132 (SRFET) connected between the flyback transformer 106 and through a current sense resistor 134 (RSENSE) to a negative terminal of the DC output”, “the SRFET 132 includes a drain node 132A connected to the fourth terminal of the flyback transformer 106, and through a resistor 136, to an SR sense pin (SR_SEN 138) of the secondary-side controller 104 to sense a voltage on the drain node 132A of the SRFET 132”, describes a “power converter 100” configured for “DCM operation” which is a type of switch-mode power system, includes a transformer 106, “The SRFET 132 includes…a gate node 132B connected to an SR gate drive pin (SR_DRV140) of the secondary-side controller 104 to drive or control the SRFET…”, and a primary-side controller 102, and a secondary-side controller 104 that controls the switching cycle, the SRFET 132 is a power switch), wherein the power switch, is coupled between the second control interface and a switching cell (Figs. 1 & 2; [0020] & [0022]-[0027]: 106,118, 124, 126, & 132, flyback transformer 106, primary switch 118, SRFET 132, and capacitors 124/126, the SRFET 132 is the power switch, the SR_DRV 140 gate pin drive of the secondary-side controller 104 to drive or control the SRFET 132, and the “switching cell” is the path through the transformer 106 and the SRFET itself), of a switch-mode power system ([0020] & [0022]-[0027]: the SRFET (power switch) gate is coupled to the secondary controller 104, the drain/source are coupled to the transformer secondary winding (NS) and output filter, forming the secondary switching cell of the flyback converter (switch-mode system)), and the power switch is turned on and off based on a direction of the electrical current through the secondary winding ([0020] & [0022]-[0027]: secondary-side controller 104 senses the drain voltage (SR_SEN138) to determine when to switch the SRFET 132, the voltage polarity corresponds to the direction of current (forward vs. reverse), where the system monitors when the secondary current “decreases to zero” (end of forward conduction/direction change) to manage the switching state (e.g., turn off SRFET/signal primary)).
Regarding dependent claims 34 & 35, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0027]-[0030], [0041] & [0046]),
Khamesra, is silent in regard to:
wherein the element and the external load are coupled in parallel to the secondary winding.
However, Abdesselam, further teaches:
wherein the element and the external load are coupled in parallel to the secondary winding (Fig. 1; [0037] & [0060]-[0061]: discloses the parallel topology for the control element: “the stop element 26 may be a switch connected in parallel with the secondary winding 34…”. The external load is powered from the same secondary winding, arranging the element (stop element 26) across the winding inherently places it in parallel with both the secondary winding and the downstream external load).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter system of Khamesra to arrange the signaling element in parallel to the secondary winding, as taught by Abdesselam. This combination addresses the structural topology requiring the element and the external load to be coupled in parallel to the secondary winding, because Abdesselam discloses a stop element 26 switch connected directly in parallel with the secondary winding 34 to manage fault signaling. A POSITA would have been motivated to integrate Abdesselam’s parallel switch placement into Khamesra’s secondary-side structure to provide a direct pathway to instantly manipulate the transformer’s magnetic flux independent of the main external load path. Utilizing this known technique to improve similar devices represents a substitution of secondary-side control topologies, producing the predictable result of a fault reporting mechanism that safely bypasses the main load components (KSR).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Khamesra, in view of Abdesselam, in view of Djenguerian, in view of Freeman et al. (US 2016/0126852 A1, Pub. Date May 5, 2016, hereinafter Freeman), in view of Kim, and further in view of Wong.
Regarding dependent claim 8, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0027]-[0030], [0041] & [0046]),
Khamesra, is silent in regard to:
wherein the first control interface includes: one or more magnetic field sensing elements that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer; and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements.
However, Freeman, further teaches:
wherein the first control interface includes: one or more magnetic field sensing elements (Fig. 1 & 66; [0038], [0103], [0106]-[0115], [0125] & [0140]-[0144]: discloses the use of Hall Effect sensors (magnetic field sensing elements) in the sensing circuit) that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer (Fig. 3; [0125]: teaches using a magnetic field sensor for this purpose, voltage sensing circuit 62, “the sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field being generated within the transformer.”, “the Hall Effect sensors facilitate determining a zero-crossing of the transformer by directly sensing the magnetic field being generated by the transformer during operation.”); and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements (Fig. 3; [0038], [0103], [0125], [0133]-[0134], [0143], & [0248]: teaches that the signal from the Hall Effect sensor is sent to the controller (“processing circuitry”) for use in regulating the converter, where the Hall Effect sensor, when used to sense the magnetic field of a transformer winding, produces a signal proportional to the current in that winding, and the controller (“processing circuitry”) can use this signal for detection purposes (e.g., zero-crossing, which is a current detection event) and to “detect the electrical current”).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first controller interface in the presence of a transformer and primary winding with one or more magnetic field sensing elements and processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, of Freeman to Khamesra, in order to improve the circuitry and magnetic field sensing (via Hall Effect sensors) on the primary side transformer within a control interface to detect current-related phenomena (zero-crossing) for regulation purposes, the substitution would be to gain the known advantages of magnetic current sensing, such as improved electrical isolation, can detect magnetic flux saturation or zero-crossings more directly than measuring voltage drops across a sense resistor, and lower power loss (no power dissipated in a series senses resistor), substituting one known current sensing technique for another, since it has been held to be within the general skill in the art to incorporate a known technique to improve similar devices in the same way is obvious, achieving a predictable improvement in performance (KSR).
Claims 9-12 & 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman, in view of Abdesselam, in view of Djenguerian, in view of Kim, and further in view of Wong.
Regarding independent claim 9, Freeman teaches:
A system (Figs. 2 & 4; [Abstract], [0032] & [0133-[0134]), comprising:
a transformer having a primary winding and a secondary winding (Figs. 2, 13, & 72; [Abstract], [0032], [0125] & [0133]-[0134]: 102, the primary voltage reduction circuit 98 includes a transformer 102.”, “The primary side of the transformer 102 is connected to the primary power circuit 26 and the secondary side of the transformer 102 is connected to the secondary voltage reduction circuit 100.”);
a first control interface that is coupled to the primary winding of the transformer (Fig. 71; [0032], [0038], [0100], [0106], [0125] & [0133]-[0134]: 102, 103, 106, & primary side regulation circuit, the primary side regulation circuit 240 and transformer control circuit 103 are coupled to the primary winding, Fig. 71 illustrates the primary side regulation circuit 240 coupled to the primary winding), the first control interface being arranged to: (i) detect an electrical current through the primary winding (Fig. 72; [Abstract], [0038], [0100], [0125], [0133]-[0134], [0163], & [0248]: 102, 103, 107 & 109, teaches the first control interface detecting current: “The transformer control circuit 103 may include a primary side current sense circuit 107 that is connected to the primary side of the transformer 102…The control circuit 103 uses a current sense resistor 109 and measures across the primary winding.”) and (ii) take a remedial action in response to the electrical current through the primary winding crossing a threshold ([Abstract], [0107]-[0108], [0163], [0186], [0202], [0251], [0253], & [0304] : control interface takes remedial action when the current crosses a threshold limit: “The output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage”), and
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Freeman, in combination with, Abdesselam, and Djenguerian, are silent in regard to:
a second control interface that is coupled to the secondary winding of the transformer, the second control interface being configured to: (i) power an external device with power that is received via the secondary winding, (ii) detect whether an error is present in the external device, and (iii) in response to detecting the error, causing an electrical current through the primary winding to drop a value to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer,
However, Kim, further teaches:
a second control interface that is coupled to the secondary winding of the transformer ([Abstract], [Col. 1, ll. 25-28], [Col. 2, ll. 2-11], [Col. 3, ll. 26-35 & 51-67], & [Col. 4, ll. 1-5]), the second control interface being configured to: (i) power an external device with power that is received via the secondary winding (Figs. 1,2, & 3; [Abstract], [Col. 1, ll. 32-38], [Col. 2, ll. 2-11 & 16-28], [Col. 3, ll. 18-21, 26-39, & 51-67], [Col. 4, ll. 1-5 & 57-63], [Claim 1], & [Claim 6]), (ii) detect whether an error is present in the external device ([Abstract], [Col. 1, ll. 25-28 & 32-38], [Col. 2, ll. 2-11 & 16-28], [Col. 3, ll. 18-21, 26-39, & 51-67], [Col. 4, ll. 1-5 & 57-63], [Claim 1], & [Claim 6]: The secondary-side control circuit 140 provides power/voltage to the external device, detects whether the output voltage Vout is normal, “The latch circuit 170 receives a fault signal SFAULT and detects whether a fault event occurs,” detecting an error in the system/device), and (iii) in response to detecting the error, causing an electrical current through the primary winding to drop a value to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer ([Col. 3, ll. 18-21, 26-45, & 49-67], [Col. 4, ll. 1-5, 23-25, & 46-56], [Col. 6, ll. 60-67], & [Col. 7, ll. 1-2 & 17-32]: when the fault is detected, the secondary side communicates the error to the primary side, forcing it into a state where switching “is controlled by the pulse-width modulation (PWM) signal with smaller pulse width in a burst mode”. This actively steps the primary current down into an intermediate diagnostic window below the overcurrent threshold but above the absolute minimum/zero),
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the system with the secondary-side fault detection and primary-side burst-mode response taught by Kim. This combination teaches a system where the second control interface detects an error and reports it by causing the electrical current through the primary winding to drop to an intermediate diagnostic value via a burst-mode that is less than a threshold and greater than a minimum draw ([Col. 3, ll. 26-45]). A POSITA would be motivated to incorporate Kim’s error detection and burst-mode logic into the established switch architecture to provide a reliable, low-power standby state that safely handles an external fault without completely shutting down the system. Utilizing this known technique to improve similar devices yields the predictable results of a system that securely drops primary current to an intermediate maintenance window upon detecting secondary-side anomalies, thus yielding expected predictable results (KSR).
Freeman, Abdesselam, Djenguerian, and Kim, are silent in regard to:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, the load being changed by changing a resistance of a transistor
However, Wong, further teaches:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer ([0008]-[0009], [0017], [0020], [0029], [0035]-[0045], [0047]-[0048], & [0058]: teaches modulating the switching behavior on the secondary side directly alters the load and overall current draw of the transformer as reflected back to the primary winding), the load being changed by changing a resistance of a transistor (Fig. 1; [0003], [0012], [0021]-[0022], [0025]-[0026], [0029], [0039]-[0050]: incorporates a solid-state metal-oxide-semiconductor field effect transistor (MOSFET). To change the load, the secondary interface drives this switch toward an off-state, which physically functions by changing its channel resistance, “The rectifier is realized by a transistor, as shown in Fig. 1, a metal-oxide-semiconductor field effect transistor (MOSFET) serves as the rectifier MSR…”. Modulating the MOSFET between its ON and OFF states operates changing its internal channel resistance, restricting or allowing current flow to alter the transformer’s draw)
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivating experimentation and optimization. Building upon the combined system of Freeman and Kim, it would have been obvious to operate the parallel transistor using the physical resistance-modulation mechanics detailed by Wong. Wong addresses the limitation wherein the electrical current through the primary winding is caused to drop by changing a load on the transformer, which is changed by changing a resistance of a transistor, by teaching the active modulation of a MOSFET’s gate to restrict channel current flow ([0039]-[0040]). A POSITA would be motivated to utilize Wong’s solid-state resistance modulation on the parallel transistor to drop the primary current into a stable signaling window, rather than crating a hard short circuit that could cause a destructive overcurrent spike. This combination represents a predictable results variation combining known electrical control methods, predictably allowing the secondary controller to safely regulate the current and load draw during the active fault signaling phase, thus yielding expected predictable results (KSR).
Freeman, is silent in regard to:
whose conduction terminals are coupled to respective ends of the secondary winding in parallel with a device that is powered with the transformer.
However, Abdesselam, in combination with Djenguerian, further teach:
whose conduction terminals are coupled to respective ends of the secondary winding in parallel with a device that is powered with the transformer (Abdesselam: Fig. 1; [0061]: teaches the physical arrangement of the transistor’s conduction terminals bridging the winding: “the stop element 26 may be a switch connected in parallel with the secondary winding 34…”. Since it is connected in parallel with the winding and the main output stage, it physically bypasses the device powered; Djenguerian: [0025], [0038], [0101], [Claim 13]: reinforces this with the solid-state switch implementation with secondary-side switch 704 topology).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the power converter system of Freeman to include the parallel switch topology taught by Abdesselam. This combination addresses a transistor whose conduction terminals are coupled to respective ends of the secondary winding in parallel with a device that is powered with the transformer. Abdesselam discloses a stop element switch 26 connected directly in parallel with the secondary winding 34. A POSITA would be motivated to integrate Abdesselam’s parallel switch placement across the secondary winding to provide a pathway to manipulate the transformer’s magnetic flux. Applying this known technique to improve similar devices represents a substitution of adding a parallel control switch to immediately modulate the transformer’s behavior across the isolation barrier. Building upon the combined system, it would have been obvious to further incorporate the current control hardware logic taught by Djenguerian. Djenguerian reinforces the transistor coupled to the respective ends of the secondary winding, detailing a solid-state implementation using a switch 704 to manage the secondary load. A POSITA would be motivated to utilize Djenguerian’s solid-state parallel switch topology to ensure that the secondary controller maintains sufficient operational stability and power while the load is being modulated. This integration represents a substitution of one known secondary-side switching topology for another, producing the predictable results of maintaining system stability and component power during active signaling states (KSR).
Regarding dependent claim 10, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]), wherein taking the remedial action includes ([0163], [0189], [0202], [0248], [0251], [0253] & [0299]: teaches a digital control block with state machines for monitoring current and taking action on fault conditions, Tronium PSSoC 106 (contains the Current Sense Amplifier and digital control block responsible for error reporting and setting status bits), “output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage.”, describes an internal action (disabling SCVBC) where monitoring for “fault or alarm conditions” implies detection and internal signaling of such conditions, “Over-current condition: The system sets the over-current status bit.”, where setting a status bit is a form of internal fault indication that can be read or reported, “”current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop as well as error reporting.” where “error reporting” implies outputting or conveying fault information, “The output can be disabled as a result of error detection or as a result of a low output current or output power situation.”, highlights that “error detection” leads to remedial actions, and system’s ability to report errors [0248] would include signaling these detections, “I2C port is including for manufacturing settings, test, evaluation, updates, health-checks and debug.”, this port provides a communication “serial interface to support configurability of the PSSoC via an external microprocessor; or a multi-wire interface which will support two way communication between the Tronium PSSoC and the microprocessor or state machine” through which internal status bits or error reports (refer to paragraphs [0202] & [0248]) can be accessed and “outputted” to an external system for monitoring or debugging).
Freeman, is silent in regard to:
outputting a fault signal.
However, Abdesselam, further teaches:
outputting a fault signal ([0018]-[0019] & [0028]: teaches remedial process involves communicating/outputting a malfunction or fault signal between isolated primary and secondary circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the remedial shutdown/de-rating actions of Freeman with the specific fault-signaling communication method taught by Abdesselam, to ensure the primary side is notified of secondary-side errors, where Freeman establishes the framework for a system that senses primary-side current and takes remedial action (de-rating or shutdown) when thresholds are crossed, and Abdesselam provides the mechanism of “outputting a fault signal” across an isolation barrier to trigger the actions. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 11, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]), wherein taking the remedial action includes ([0041], [0163], [0182], [0202]-[0203], [0228]-[0229], [0251], [0253] & [0299]: describes a control state machine that transitions to a shutdown state in response to conditions like “over-current” or “under-load”, Tronium PSSoC 106 (controls actions described below), SCVBC 32, SWR (Switch-Mode Buck Regulator), PWM (Pulse-Width Modulation), “a vampire load elimination system that is configured to determine when a consumer device has finished charging and/or is disconnected from the power circuit, and operates the power circuit to disconnect the supply of power to the power circuit and/or the electronic device, and also capable of creating a flea powered “stand-by” mode. It is accomplished by placing the system in to “sleep mode” where the only circuits powered are the timing circuits, which periodically “wake up” to check if there is a connection or current draw”, in response to “fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVC 32 to prevent possible damage”, disabling a circuit turns off its operation, “Over-current condition” or “Under-load condition”, the system “transitions to sleep mode (SM).”, entering sleep mode turns off most active circuits, “Sleep Mode (SM). The system disables the HF_OSC, the CP, the SWR, the forward PID, the CUR_SNS and the ADC.”, disabling these components turns off significant parts of the device’s operation, the “Tronium PSSoC digital memory has intelligence” to ”always put itself into Sleep Mode during these times to conserve energy and not re-engage in the current sensing routing of the wake-up sequencing.”, for example a powered television has not been used for a fixed period, “there could be “real-time” instructions given to the Tronium PSSoC about when to go to Sleep Mode, when to wake up, and reset, upgrade or change other preconditions”, including commands “about resets, operation, or shutdowns/restarts” of the device”, “Actions taken to protect against thermal damage may include the de-rating of output power and complete shut-down of output.” where a “complete shut-down output” implies turning off the device’s power delivery, “output can be disabled as a result of error detection or as a result of a low output current or output power situation…This can take place by turning off the PWM, switch capacitor circuit, or through de-ration of either or both subsystems”, also mentions the Tronium PSSoC entering a “low current shut-down state.”, and a failsafe circuit where if a “system should malfunction…the system would shut itself down through a failsafe circuit which would prevent the chip from accepting any more signal from the source at VLine”).
Freeman, is silent in regard to:
turning off the external device.
However, Abdesselam, further teaches:
turning off the external device ([0031], [0066] & [Claim 14]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement the “complete shut-down” taught by Freeman as a remedial action to protect the system, resulting in the “turning off” of the external device, the mechanism for the deactivation is further corroborated by the command deactivator logic taught by Abdesselam. Freeman describes a power delivery system for electronic devices (external device) and lists a complete shut-down of output as a remedial action to protect the hardware. Abdesselam reinforces this by describing the circuit logic required to execute the remedial action, teaching a command deactivator, that cancels the operation of the power stage upon detecting a fault, stopping the transfer of energy, thereby turning off the load/device connected to the secondary side. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 12, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]),
Freeman, in combination with Abdesselam, are silent in regard to:
wherein the element includes a current control device that is coupled to the secondary winding in parallel with the second control interface.
However, Djenguerian, further teaches:
wherein the element includes a current control device that is coupled to the secondary winding in parallel with the second control interface (Fig. 1; [0020]-[0021], [0025], [0029], [0035], [0038], [0048]-[0049], [0051], [0101], [Claim 4], [Claim 13], & [Claim 17]: discloses a “First Power Circuit 152” which functions as the current control device. This device is physically coupled to the secondary winding 116 as a distinct parallel current path alongside the main secondary controller 120 (the second control interface) to selectively manage the secondary load bypass current).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the current control hardware logic taught by Djenguerian. Djenguerian addresses the element includes a current control device that is coupled to the secondary winding in parallel with the second control interface, by detailing a first power circuit 152 acting as a current control device coupled in parallel with the secondary controller 120. A POSITA would be motivated to utilize Djenguerian’s parallel current control device topology to ensure that the secondary interface maintains sufficient operation power, stability, and longevity while the load is being modulated. This integration represents a substitution of one known secondary-side switching topology for another, producing the predictable results of safely managing system stability and component power during active signaling states (KSR).
Regarding dependent claim 14, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202], [0207] & [0253]), wherein the threshold is less than a lower bound of a normal operating range of an electrical current draw of the transformer (Figs. 3, 66, & 72; [0041], [0098], [0102]-[0104], [0107], [0112], [0140], [0144], [0174], [0180], [0182]-[0183], [0186]-[0187], [0202]-[0203], [0217], [0229] & [0467]: teaches a controller that monitors for and reacts to a low current condition by comparing the current to a threshold set below the normal operating range, Tronium PSSoC 106 (contains the Control State Machine and current sensing capabilities), “the switch capacitor voltage divider circuit is configured to deliver up to 50 mA and maintain a ≥95% efficiency across the range of load currents from 50 mA to less than 1 mA under light load conditions.”, indicating that 50 mA is a lower bound for a normal operating range, and the system operates below this for “light load conditions.”, “the forward converter control loop may be configured to regulate the output voltage under heavy fluctuation (4.5 nA to 4.5 A) of load current without triggering any instability.”, indicating that 4.5 nA (nanoamperes) is a low end of the normal operating range for the forward converter, a threshold for ‘under-load” would be below this operating range, note that “Control State Machine or microprocessor continually monitors the output voltage current for an over-or-under-current alarm condition.”, where an “under-current” alarm condition indicates a threshold below the normal operating range, also note that ”Under-load condition: if the LCSD EN pin is high and sleep mode is not disabled, the system transitions to sleep mode (SM).”, where the “under-load condition” is triggered by a threshold that is below the normal operating range, which causes the system to enter a low-power state, where “the Control State Machine can disable the SWR Buck Regulator if the load current decreases to the programmed digital threshold”, where the “programmed digital threshold” that disables the buck regulator due to a decreasing load current would be below the normal operating range, and “The output can be disabled as a result of error detection or as a result of a low output current or output power situation such as arises when connected device that includes a battery is done charging the battery and the Tronium PSSoC is only providing power to the non-battery charging functionality.”, where the “low output current or output power situation” refers to a threshold below normal operation)
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Freeman, in combination with Abdesselam, are silent in regard to:
and greater than the minimum current draw of the transformer.
However, Djenguerian, further teaches:
and greater than the minimum current draw of the transformer (Figs. 1; &7; [0021], [0025], [0049]-[0051], [0056], [0067], [0069]-[0071], [0081] & [0100]: during faults or startup, when main load is off/low, the first power circuit is enabled to draw operating current, current is small (maintenance level) compared to a full load, primary side sees a current drop (from full load) but maintains a level sufficient to power the secondary chip (greater than zero/minimum) and less than a threshold, further discusses charging from multiple sources to maintain bypass voltage above a “minimum value” sufficient to operate circuits).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivate experimentation and optimization. Freeman teaches the use of current thresholds to detect operating states, distinguishing between a normal load and a ”no load” or low-current state, defining the “ceiling” of the window (below normal load). Djenguerian provides the “minimum current draw”, defining the “floor” (above minimum to keep current alive), regulating power to ensure the system stays above a minimum operational value (bypass voltage/current) to keep the controller working. Therefore, setting the detection threshold between the normal operating current and the system’s baseline minimum draw (quiescent/magnetizing current) to improve and reliably distinguish a fault-induced drop from background noise or total disconnection. Djenguerian provides further support for secondary-side control circuits that manage power and regulate bypass voltages from multiples sources, providing the bypass path hardware (a parallel current control device connected to the secondary winding), describing a bypass voltage above a minimum operational value to ensure the control interfaces remain powered during different transitions, such as the remedial actions disclosed by Freeman, “shut-down of output” or “de-rating of output power) when thresholds (like over-temperature or over-current) are crossed. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 15, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0202], [0207] & [0253]),
Freeman, in combination with Abdesselam, are silent in regard to:
wherein the first control interface is formed on a first semiconductor die and the second control interface is formed on a second semiconductor die.
However, Djenguerian, further teaches:
wherein the first control interface is formed on a first semiconductor die ([0031]-[0032]: discloses the primary controller (first control interface) formed on a first integrated circuit die) and the second control interface is formed on a second semiconductor die ([0031]-[0032]: discloses the secondary controller (second control interface) formed on a distinct second die to ensure they are “galvanically isolated from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date, where Freeman discloses the foundational structure of using multiple semiconductor chips in a power architecture, Djenguerian teaches separating the primary and secondary controllers onto different dies to maintain galvanic isolation, therefore modifying the multi-chip system of Freeman, which already utilizes a first and second chip, by incorporating the dual-die configuration of Djenguerian, to achieve high-voltage galvanic isolation between the input (primary) and the output (secondary) sides and voltage handling capabilities required by a transformer-based design, while maintaining a compact form factor, combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 16, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]),
Freeman, is silent in regard to:
wherein the element includes a transistor that is coupled between the transformer and the second control interface, the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding and a gate that is coupled to the second control interface
However, Abdesselam, in combination with Djenguerian, further teach:
wherein the element includes a transistor that is coupled between the transformer and the second control interface (Abdesselam: [0061]: discloses a stop element 26 which is a switch/transistor driven by the power and fault detection controller 21, acting as the second control interface; Djenguerian: Fig. 1; [0025], [0038], [0048]-[0049], [0051], [0101], [Claim 13]: further corroborates the solid-state implementation with secondary-side switch 704),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the current control hardware logic taught by Djenguerian/Abdesselam. Djenguerian reinforces the transistor structural arrangement, to a solid-state implementation of the transistor coupled between the transformer and the second control interface, detailing the use of a switch 704 with the first power circuit 152 to manage the secondary load. A POSITA would be motivated to utilize Djenguerian’s parallel switch topology to ensure that the secondary controller maintains sufficient operational stability and precise current handling while the load is being modulated. This integration represents a substitution of one known secondary-side switching topology for another, producing the predictable results of safely managing system stability and component power during active signaling states (KSR).
However, Abdesselam, further teaches:
the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding and a gate that is coupled to the second control interface (Fig. 1; [0061]: teaches the physical parallel connection, “the stop element 26 may be a switch connected in parallel with the secondary winding 34 and driven by the power and fault detection controller 21”, connecting a transistor directly in parallel with the winding inherently dictates that its source and drain are coupled across the first and second ends of the winding, with the gate coupled to the controller, further illustrated in Fig. 1),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the primary power converter system of Freeman to include the parallel switch topology taught by Abdesselam. This combination discloses the transistor has a source and drain coupled to the first and second ends of the secondary winding and a gate coupled to the second control interface. Abdesselam discloses a stop element 26 switch connected directly in parallel with the secondary winding 34 and driven by controller 21. A POSITA would be motivated to incorporate Abdesselam’s parallel switch into Freeman’s architecture is to establish a direct signaling pathway across the secondary winding that can manipulate the transformer’s magnetic flux. Applying this known technique to improve similar devices, represents a substitution of adding a parallel control switch to immediately modulate the transformer’s behavior across the isolation barrier (KSR).
Freeman, Abdesselam, Djenguerian, and Kim, are silent in regard to:
wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance of a path between the source and the drain of the transistor.
However, Wong, further teaches:
wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance of a path between the source and the drain of the transistor ([0039]-[0040], [0064], & [0066]: teaches applying a control voltage to the gate terminal of a metal-oxide-semiconductor field effect transistor (MOSFET) switch MSR coupled to the secondary winding. Modulating this solid-state element towards an off-state physically operates by changing the voltage applied at its gate to increase its channel resistance between the source and drain, safely restricting the current to report the error across the isolation barrier).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the parallel transistor using the physical resistance-modulation mechanics detailed by Wong. Wong teaches the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to increase a resistance path between the source and the drain of the transistor, by teaching the active modulation of a MOSFET’s gate to restrict channel current flow. The secondary controller detects a fault, and instead of just shutting down, gently increasing the resistance the gate of the parallel transistor. By turning this transistor into a variable resistor directly across the winding, it safely alters the magnetic flux of the transformer, which forces the primary-side current to drop, sending an error signal across the isolation barrier without needing a physical wire or optical coupler. A POSITA would be motivated to utilize Wong’s solid-state resistance modulation on the parallel transistor to drop the primary current into a stable signaling window, rather than creating a hard short circuit that could cause a destructive overcurrent spike. This combination represents a predictable variation combining known electrical control methods, predictably allowing the secondary controller to safely regulate the current and load draw during the active fault signaling phase by pinching the transistor’s channel (KSR).
Regarding dependent claim 17, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]), further comprising a power switch for controlling a switching cell of a switch-mode power supply (Figs. 50 & 72; [0108], [0124], [0133], [0261]: discloses a switch-mode power supply (e.g., Forward Converter or Flyback) comprising a power switch (synchronous rectifier) for controlling the switching cell (secondary side), M2 MOSFET, PFET SR 238 & NFET SR 238, M2 MOSFET within the secondary voltage reduction circuit 100 is a power switch, PFET and NFET are synchronous rectifier MOSFETs, acting as power switches in the forward converter (a switch-mode power supply), “the secondary voltage reduction circuit 100 may include a diode and a MOSFET”, the “secondary voltage reduction circuit” is part of the “forward converter circuit 96”, which is a switch-mode power supply, “synchronous rectifier FETs.”, where FETs (Field-Effect Transistors) are power switches and synchronous rectification is a technique used in switching cells of switch-mode power supplies for rectification, circuitry includes power switches, specifically MOSFETs, that act as synchronous rectifiers to control the power delivery cell on the secondary side, replacing diodes with MOSFETs for rectification is a well-known “switching cell” in SMPS design for higher efficiency),
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Freeman, in combination with Abdesselam, are silent in regard to:
wherein the power switch is coupled between the second control interface and the device, wherein the power switch is turned on and off by the second control interface based on a direction of the electrical current through the secondary winding.
However, Djenguerian, further teaches:
wherein the power switch is coupled between the second control interface and the device (Fig. 1; [0046]: discloses a power switch (synchronous rectification circuit 132) coupled between the second control interface (secondary controller 120) and the device (output 104 or load), the controller drives the switch via a control terminal, figure further illustrates secondary controller 120 coupled to synchronous rectification circuit 132 (switch) which is the path to output terminals 104 (device)), wherein the power switch is turned on and off by the second control interface based on a direction of the electrical current through the secondary winding (Fig. 1; [0041] & [0046]: teaches that the secondary controller turns the power switch (SR) on and off based on the state of the secondary winding, which dictates the direction of electrical current flow, i.e., conducting energy to the output).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the secondary-side controller and synchronous rectification logic of Djenguerian into the power system of Freeman to improve efficiency. Djenguerian provides a standard, high-efficiency implementation where a secondary controller manages, drives the power switch/the synchronous rectifier, based on the conduction state (current direction) of the secondary winding to minimize voltage drops and conduction losses. Freeman discloses a power switch controlling a switch-mode power supply, using a primary-side regulation circuit with a controller and a current sensor to generate a pulse-width modulated (PWM) signal to operate the switch. Additionally, doing so, merely combines prior art elements according to known methods, without the need for additional complex components, and yielding predictable results (KSR).
Regarding dependent claim 18, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]), wherein the first control interface includes (Fig. 66; [0038], [0103], [0106]-[0115], [0125], [0140]-[0144], & [0167]: Tronium PSSoC 106, “power module includes the advanced power supply system on a chip (TroniumTM PSSoC)…including a controller application specific integrated circuit (ASIC)”, the “TroniumTM PSSoC” serves as the central “first control interface”, additional components of “the Tronium PSSoC 106 includes the single-stage switch capacitor circuit 32, a PID regulator control block 11 for PWM control of the forward converter secondary transformer 102…a current and temperature sense blocks 116, 12-bit Analog-to-Digital Converter (ADC) 118 for voltage and current monitoring,… and a digital control block 122 for current monitoring state machine.”, these components collectively form parts of the processing circuitry in the first control interface):
one or more magnetic field sensing elements (Fig. 1 & 66; [0038], [0103], [0106]-[0115], [0125] & [0140]-[0144]: discloses the use of Hall Effect sensors (magnetic field sensing elements) in the sensing circuit) that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer (Fig. 3; [0124]-[0125], [0167]: teaches using a magnetic field sensor voltage sensing circuit 62, “the sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field being generated within the transformer.”, the Hall Effect sensors are the “magnetic field sensing elements” and are arranged to measure a magnetic field associated with the primary side of the transformer, the sensors are part of the “regulator control circuit 58”, “the Hall Effect sensors facilitate determining a zero-crossing of the transformer by directly sensing the magnetic field being generated by the transformer during operation”); and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements (Fig. 3; [0038], [0103], [0125], [0133]-[0134], [0143], & [0248]: voltage sensing circuit 62, linking the magnetic field sensing to current detection: “The Hall Effect sensor is connected to the PWM controller 60 for transmitting a signal to the PWM controller 60 for transmitting a signal to the PWM controller 60 for use in determining when the transformer nears the “zero-crossing”.”, further stating, “The sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field generated within the transformer”, where the “PWM controller 60” acts as the “processing circuit”, “determining a time at which the transformer reaches the “zero-crossing” by sensing its magnetic field is a method of detecting current-related behavior (e.g., the point where current crosses zero through the primary winding, based on the signal generated by the Hall Effect sensors), “a current sense circuit configured to sense a current level on the primary side, and a controller configured to generate a pulse-width modulated control signal delivered to the switching device as a function of the sensed current level to regulate the transformer.”, supports the idea of a controller (processing circuit) deterring the primary side current, “The current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop as well as error reporting. The current can be measured by an ADC or through a series of comparators with varying thresholds.”, confirms the Tronium PSSoC (first control interface) includes processing circuitry capable of current measurement, also teaches the control circuit 103 includes processing circuitry (e.g., sample-and-hold circuits, comparators, ADCs, digital state machines) that is “arranged to detect the electrical current” based on a signal from a sensor (resistor 109), where the processing of a sensor signal is used to determine current for the purpose of regulation).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Vemuri et al. (US 2017/0033698 A1, Pub. Date Feb. 2, 2017, hereinafter Vemuri), in view of in view of Abdesselam, in view of Yang et al. (US 2022/0155383 A1, Pub. Date May 19, 2022, hereinafter Yang), in view of Kim, and further in view of Wong.
Regarding independent claim 29, Vemuri teaches:
A system (Figs.1 & 8; [Abstract] & [0014]-[0016]: 100, flyback converter system), comprising:
a power switch (Figs.1 & 8; [0016]-[0019]: “The flyback converter 100 includes a primary side or first switch S1, and a secondary side or second switch S2. The first switch S1 is operated by the first switching control signal SC1 from the first control circuit 114, and the second switch S2 is operated according to the second switching control signal SC2 from the second control circuit 130”, “N-channel field effect transistor (FET) switches S1 and S2”, and “The primary winding 108 includes a first end 106 to receive the input voltage signal VIN, and a second end 110 connected to the first terminal or drain (D) of the first switch S1. The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sensor resistor R1 that provides a current sense signal CS to the first control circuit 114.”, the second switch S2 is a power switch (e.g., a synchronous rectifier) connected to the secondary winding 122);
a transformer having a primary winding and a secondary winding (Fig. 1; [0014] & [0017]-[0019]: discloses a transformer 104 with a primary winding 108 and a secondary winding 122), the primary winding and the secondary winding being arranged to power an external load via the power switch (Fig. 1; [0014]-[0019]: 104, 108, 118, & 122, “a flyback power converter or conversion system 100 including a controller integrated circuit (IC) 101 having a first control circuit (e.g., a primary side controller or PSC) 114 and a second control circuit (e.g., a secondary side controller or SSC) 130, as well as a transformer 104 with a primary winding 108 receiving input VIN and a secondary winding 122 providing output VO to a load 125 (“external load’) via the secondary switch S2 (power switch). The transformer 104 also includes an additional or auxiliary winding 118 on the primary side.” and also contains a first switch S1);
a controller (Figs. 1-3 & 8; [0014]-[0019] & [0023]-[0024]: “The first (primary side) control circuit 114 includes a driver circuit 116 with an output 117 to provide a first switching control signal SC1 under control of a first control logic circuit 120. The logic circuit 120 is coupled with the driver circuit 116, and includes an input 121 coupled with the auxiliary winding 118 through a resistor R2 to receive a signal VAUX representing a voltage of the auxiliary winding 118…The first control circuit 114 receives a predetermined cycle start request signal from the second control circuit 130 via the auxiliary winding 118 to initiate power transfer cycles for operation in a second mode to implement secondary side regulation (SSR) of the output voltage VO”, “the first control circuit 114 can operate according to a predetermined time period between successive power transfer cycles. This operation, in conjunction with operation of the second control circuit 130 in the case of synchronous rectifier implementations (or through operations of a separate secondary side rectifier diode)”, “the primary side control circuit 114, including the first control logic circuit 120. The first logic circuit 120 can include any suitable analog and/or digital circuitry, programmable or preconfirmed”, where the primary control circuit 114, containing control logic 120, serves as the controller for the first control interface, system includes a first control circuit 114 and a second control circuit 130, these can be in a single IC 101 or separate 101a/101b, collectively forming the controller);
a first control interface that is coupled between the controller and the primary winding (Figs.1 & 2; [0014]-[0019]: “The first (primary side) control circuit 114 includes a driver circuit 116 with an output 117 to provide a first switching control signal SC1 under control of a first control logic circuit 120. The logic circuit 120 is coupled with the driver circuit, and includes an input 121 coupled with the auxiliary winding 118 through a resistor R2 to receive a signal VAUX representing a voltage of the auxiliary winding 118.”, “The primary winding 108 includes a first end 106 to receive the input voltage signal VIN, and a second end 110 connected to the first terminal or drain (D) of the first switch S1. The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sense resistor R1 that provides a current sense signal CS to the first control circuit 114.”, primary side of control circuit 114 is part of the controller and is coupled to the primary winding 108 via switch S1, it monitors the primary side, including the current sense (CS) signal from resistor R1, which measures the electrical current through the primary winding via switch S1),
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Vemuri, is silent in regard to:
the first control interface being arranged to: (i) obtain a first measurement of an electrical current through the primary winding, and (ii) obtain a second measurement of the electrical current through the primary winding,
a second control interface that is coupled between the secondary winding and the power switch, the second control interface being configured to: (i) provide an electrical current received from the transformer to the power switch,
However, Vemuri, in combination with Yang, further teach:
the first control interface being arranged to: (i) obtain a first measurement of an electrical current through the primary winding (Vemuri: Figs.1 & 2; [0014]-[0019]: “The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sense resistor R1 that provides a current sense signal CS to the first control circuit 114.”, “the first switch S1 is placed in an on state or condition to selectively allow a first switch current IS1 to flow between the first and second terminals (D,S) of the switch S1 when the first switching control signal SC1 is in a first state (e.g., HIGH for an N-channel FET S1). In this condition, current flows from the input source 102 into the first end 106, including the current IS1 flowing through the first switch S1, and current associated with a magnetizing inductance of the primary winding 108,” the first control circuit 114 obtains a current measurement via the current sense CS signal from resistor R1, which is proportional to the current IS1 through the primary switch S1 and the primary winding, this is considered the first measurement; Yang: Figs. 9, 10, & 11; [Abstract], [0005], [0007], [0010], [0045], [0049], [0126]-[0127], [Claim 1], & [Claim 18]: provides the logic applied to that interface: “receive a first signal indicating a first current…receive a second signal indicating a second current” ), and (ii) obtain a second measurement of the electrical current through the primary winding (Vemuri: Figs.1 & 2; [0014]-[0019]: teaches the interface obtaining a measurement of the electrical current through the primary winding via the current sense signal CS; Yang: [Abstract], [0004]-[0005], [0007], [0010], [0015], [0025], [0032], [0044]-[0050], [0126]-[0127], [Claim 1], & [Claim 18]: teaches using two sensors (140/142) to obtain multiple measurements of current flow to ensure accuracy and distinguish faults),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Vemuri to incorporate the redundant current sensing and fault validation logic taught by Yang. Vemuri addresses a first control interface coupled between the controller and the primary winding to measure primary current, specifically through a current sense resistor R1 providing a current sense signal CS to the first control circuit 114. Yang addresses obtaining a first and second measurement of the current, detecting if they are in agreement, and selectively outputs a first fault signal for sensor disagreement or a second fault signal for a true threshold-crossing overcurrent. A POSITA would be motivated to integrate Yang’s redundant measurement and agreement-checking logic into Vemuri’s primary-side sensing interface to distinguish between a true primary winding overcurrent fault and a false alarm caused by a single failing sensor. Applying this known technique to improve similar devices yields the predictable result of a reliable power system that prevents unnecessary shutdowns while maintaining protection against genuine threshold-crossing events (KSR).
However, Abdesselam, further teaches:
a second control interface that is coupled between the secondary winding and the power switch, the second control interface being configured to: (i) provide an electrical current received from the transformer to the power switch (Fig. 1; [0059] & [0061]-[0062]: discloses a power and fault detection controller 21 (second control interface) coupled between the secondary winding 34 and a stop element 26 (power switch) to actively manage and provide the electrical current reaching the switch),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the secondary-side power switch control architecture taught by Abdesselam into the combined system of Vemuri/Yang. Abdesselam addresses a second control interface coupled between the secondary winding and the power switch configured to provide current to the power switch, by disclosing a power and fault detection controller 21 driving a secondary switch 26. A POSITA would be motivated to utilize Abdesselam’s secondary interface topology to ensure localized control and power delivery management at the secondary boundary before reaching the external load. Further, the motivation to incorporate Abdesselam’s parallel switch into the combined system of Vemuri/Yang architecture is to establish a direct signaling pathway across the secondary winding that can manipulate the transformer’s magnetic flux. This integration represents a substitution of one known secondary-side switching arrangement for another, predictably allowing the secondary interface to actively manage the current provided to the downstream power switch (KSR).
Vemuri, in combination with Abdesselam, are silent in regard to:
(iii) detect whether the first and second measurements are in agreement with each other, (iv) output a first fault signal to the controller when the first and second measurements are not in agreement with each other, and (v) output a second fault signal to the controller when the first measurement and the second measurement are in agreement with each other, but at least one of the first and second measurements has crossed a threshold; and
However, Yang, further teaches:
(iii) detect whether the first and second measurements are in agreement with each other ([Abstract], [0010]-[0011], [0004]-[0005], [0007], [0013]-[0015], [0025]-[0029], [0032]-[0033], [0040], [0043]-[0052], & [0064]-[0065]: teaches comparing two signals, if they diverge (disagreement), it indicates a specific type of fault or sensor error, checks the redundant signals for agreement: “determine that if the first difference is not greater than a first threshold level”, which verifies the two redundant current sensors are reading the same value and are in agreement), (iv) output a first fault signal to the controller when the first and second measurements are not in agreement with each other ([0032]-[0033], [0043]-[0050], [0064]-[0069], [0072], [Claim 2], [Claim 3], [Claim 4], [Claim 7], [Claim 19]: if sensors disagree (e.g., one reads fault, one does not), the system identifies the sensor fault or location of the system fault, generating an internal fault determination (signal) and outputs a fault indicating a sensor mismatch rather than a true overcurrent: “detect the fault in response to determining that the first difference is greater than the threshold level”), and (v) output a second fault signal to the controller when the first measurement and the second measurement are in agreement with each other, but at least one of the first and second measurements has crossed a threshold ([0010], [0032]-[0033], [0040], [0043]-[0052], [0064], [0112]-[0115], [Claim 10], & [Claim 19]: teaches declaring a system fault (second fault signal) when both sensors agree (both show high derivative/current crossing a threshold), further when both sensors agree (first difference is not greater than the threshold) but the actual measured current crosses the overcurrent limit (second different is greater than the second threshold level), further confirming a true system fault and outputs the corresponding true overcurrent fault signal); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the power converter system of Vemuri to include the redundant current sensing and fault validation logic taught by Yang. This combination addresses the first control interface obtaining a first and second measurement of the primary winding current, detecting whether they are in agreement, outputting a first fault signal if they disagree, and outputting a second fault signal if they agree but cross a threshold. A POSITA would be motivated to integrate Yang’s redundant measurement and agreement logic into Vemuri’s primary-side controller to accurately distinguish between a true overcurrent fault and a false alarm caused by a failing current sensor. Applying this known technique to improve similar devices yields the predictable result of a reliable power system that prevents unnecessary shutdowns while maintaining protection against genuine threshold-crossing events (KSR).
Vemuri, in combination with, Abdesselam, and Yang, are silent in regard to:
(ii) detect whether an error is present in operational conditions of the power switch, and (iii) in response to detecting the error, report the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold,
However, Kim, further teaches:
(ii) detect whether an error is present in operational conditions of the power switch ([Abstract], [Col. 1, ll. 25-28 & 32-38], [Col. 2, ll. 2-11 & 16-28], [Col. 3, ll. 18-21, 26-45, & 51-67], [Col. 4, ll. 1-5 & 57-63], [Claim 1], & [Claim 6]: The secondary-side control circuit 140, detects abnormal operational conditions, whether the output voltage Vout is normal, “The latch circuit 170 receives a fault signal SFAULT and detects whether a fault event occurs,” detecting an error in the system/device), and (iii) in response to detecting the error, report the error to the first control interface by causing the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold ([Col. 3, ll. 8-16, 18-21, 26-45, & 49-67], [Col. 4, ll. 1-5, 23-25, & 46-56], [Col. 6, ll. 60-67], & [Col. 7, ll. 1-2 & 17-32]: when the fault is detected, the secondary interface forces a state where primary switching “is controlled by the pulse-width modulation (PWM) signal with smaller pulse width in a burst mode,” which steps the primary current down into an intermediate diagnostic window below the threshold but above the minimum draw),
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the system with the secondary-side fault detection and primary-side burst-mode response taught by Kim. This combination teaches a system where the second control interface detects an error in operational conditions and reports it by causing the primary electrical current through the primary winding to drop to an intermediate diagnostic value via a burst-mode that is greater than a minimum draw and less than the threshold via a burst-mode ([Col. 3, ll. 26-45]). A POSITA would be motivated to incorporate Kim’s error detection and burst-mode signaling logic into the established switch architecture to provide a reliable, low-power standby state that safely handles a fault at the power switch without completely shutting down the entire transformer system. Utilizing this known technique to improve similar devices yields the predictable results of a system that securely drops the primary current to an intermediate maintenance window upon detecting secondary-side anomalies, thus yielding expected predictable results (KSR).
Vemuri, in combination with, Abdesselam, Yang, and Kim, are silent in regard to:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer, the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding, and
wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer.
However, Wong, further teaches:
wherein the electrical current through the primary winding is caused to drop by changing a current draw of the transformer ([0008]-[0009], [0017], [0020], [0029], [0035]-[0045], [0047]-[0048], & [0058]: teaches modulating the switching behavior on the secondary side directly alters the overall current draw of the transformer as reflected back to the primary winding), the current draw of the transformer being changed by increasing a resistance of an element that is coupled to the secondary winding (Fig. 1; [0003], [0012], [0021]-[0022], [0025]-[0026], [0029], [0039]-[0050]: incorporates a solid-state metal-oxide semiconductor field effect transistor (MOSFET) MSR, which is the element coupled to the secondary winding is a solid-state switch, “The rectifier is realized by a transistor, as shown in Fig. 1, a metal-oxide-semiconductor field effect transistor (MOSFET) serves as the rectifier MSR…”. To change the draw, the secondary interface modulates this switch toward an off-state, which physically functions by increasing its channel resistance. Further, modulating the MOSFET between its ON and OFF states operates changing its internal channel resistance, restricting or allowing current flow to alter the transformer’s draw), and
wherein the minimum current draw of the transformer is a current draw that is caused by an internal resistance of the transformer ([0015] & [0051]-[0053]: identifies the parasitic effects and oscillating current (non-idealities) of the transformer, the core excitation energy and internal parasitic/winding resistances, prevent the primary current that maintain a baseline minimum current draw even when secondary load current crosses zero, from reaching absolute zero, thereby causing the baseline “minimum current draw”, further, the oscillating current represents the minimum baseline draw required by the transformer’s internal parasitics).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivating experimentation and optimization. Building upon the combined system mentioned above, it would have been obvious to operate the signaling mechanics using the physical resistance-modulation and transformer characteristics taught by Wong. Wong addresses the electrical current through the primary winding is caused to drop by changing a current draw of the transformer by increasing a resistance of an element, and wherein the minimum current draw is caused by an internal resistance of the transformer ([0039] & [0052]). A POSITA would be motivated to utilize Wong’s solid-state gate resistance modulation to drop the primary current into the signaling window without creating a destructive hard short circuit across the secondary boundary. This combination represents a predictable variation combining known electrical control methods, predictably utilizing the inherent physical non-idealities of the transformer to establish a safe, minimum baseline current during the active fault signaling phase, thus yielding expected predictable results (KSR).
Claims 30-32 & 36 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed et al. (US 2024/0283352 A1, Filed Date Jun. 16, 2023, hereinafter Ahmed) in view of Freeman, in view of Abdesselam, in view of Kim, in view of Wong, and further in view of Knoedgen (US 2013/0235632 A1, Pub. Date Sep. 12, 2013, hereinafter, Knoedgen).
Regarding independent claim 30, Ahmed teaches:
A system (Fig. 1; [0003], [0012], [0014] & [0039]-[0040]: discloses a flyback converter system comprising a primary side and a secondary side), comprising:
a transformer having a primary winding and a secondary winding (Fig. 1; [0012], [0014], & [0039]-[0040]: discloses the flyback transformer 130 that includes a primary-side winding and a secondary-side winding, “A flyback transformer 130” acts as a magnetically coupled structure, this transformer has a “primary-side winding” and a “secondary-side winding”, the windings correspond to the “first element” and “second element” respectively, flyback transformer 130 separates the primary side 110 and the secondary side 120);
a first control interface that is coupled to the primary winding (Fig. 1; [Abstract], [0012]-[0013], [0028], [0039]-[0040], [0042], & [0046]), the first control interface being arranged to: (i) measure an electrical current through the primary winding (Figs. 1, 2A, 2B; [0012]-[0013], [0018]-[0022], [0024], [0031]-[0032], [0039]-[0040], [0042], [0044], [0046], [0086], & [0094]: teaches the primary side 110 includes a primary-side controller 116, this controller interfaces with the primary winding via the switch 118, which is interpreted as the first control interface, “the primary-side controller 116” (a “controller”) is coupled to the “primary-side winding” (the “first element”) of the flyback transformer 130, the primary-side controller 116 controls operation of the switch, which in turn controls the primary element, the “first control interface” can be largely embodied by the primary-side controller 116 and associated circuitry, primary-side controller 116 is coupled to the primary winding and monitors for “peak current limits” and “over-current (OC)” which necessitates measuring the primary electrical current), (ii) detect whether the measured electrical current falls into any given one of a plurality of threshold ranges that are outside of a normal operating range of the transformer ([Abstract], [0003]-[0004], [0012], [0014], [0016], [0018]-[0024], [0026]-[0029], [0031]-[0032], [0036], [0039]-[0040], [0042]-[0043], [0045]-[0046], [0048]-[0049], [0051], [0053]-[0057], [0062]-[0063], [0065]-[0067], [0069], [0072]-[0074], [0077], [0080], [0094], & [0106]: discloses a primary-side controller programmed to detect multiple distinct categories of current-based faults), (iii) when the measured electrical current falls into any given one of the plurality of threshold ranges, identify an error type that corresponds to the given threshold range (0012]-[0013], [0018]-[0024], [0026]-[0027], [0030]-[0032], [0039]-[0040], [0041]-[0042], [0044]-[0046], [0048]-[0049], [0052]-[0054], [0056], [0058]-[0059], [0061]-[0064], [0066], [0069]-[0070], [0072], [0074]-[0078], [0086]-[0087], [0094], [0103]-[0106], & [0108]: teaches the system identifies the exact functional error that occurred based on the detected parameters), and (iv) output a fault signal that is indicative of the error type ([Abstract], [0003], [0015]-[0019], [0021]-[0022], [0024]-[0032], [0039]-[0045], [0047]-[0055], [0057]-[0060], [0062]-[0065], [0067]-[0074], [0076]-[0078], [0080], [0084], [0086]-[0089], [0092]-[0097], [0103]-[0104], [0106]-[0109], [Claim 7], [Claim 10], [Claim 12], [Claim 14], [Claim 18],: teaches outputting distinct fault information tailored to the specific error type identified); and
a second control interface that is coupled to the secondary winding, the second control interface being configured to (Figs. 1, 2A, & 2B; [0012], [0015]-[0017], [0024], [0039]-[0040] & [0043]: discloses the secondary side 120 includes a secondary-side controller 126, this controller is coupled to the secondary winding 122 and is the second control interface, a “secondary-side controller 126” (a “second control interface”) that is coupled to the “secondary-side winding” (the ”second element”) of the flyback transformer 130, the secondary-side controller 126 is configured to “communicate control signals to the primary-side controller” (which controls the “power switch”) via a “signal transformer 140”): (i) provide an electrical current received from the transformer to an external load (Fig. 1; [0012]-[0014], [0042], & [0084]-[0087]: discloses the secondary side provides the output voltage VO to drive a load 125 via connector 122, the current from the secondary winding 122 flows through diode 128 or a synchronous rectifier to the load, when the primary-side power switch is in the off-state, the “secondary current to flow from the flyback transformer” (i.e., received from the magnetically coupled structure’s secondary winding or transformer) and this “secondary current is used to charge the at least one secondary-side capacitor and deliver power to the load connected to the connector”, the secondary-side control interface enables current flow to the load by sending signals to the primary side, indirectly affecting the primary power switch operation in relation to energy transfer, further, secondary-side controller 126 negotiates a contract to “cause power to be provided to the consumer device”), (ii) detect whether an error is present (Figs. 2B & 5; [0022], [0032], [0046], [0054], [0064], [0078], [0084]-[0087], & [0094]: discloses the secondary-side controller 126 can store and monitor for faults such as “over-voltage (OV), under-voltage (UV), or over-current (OC), short-circuit detection, over-temperature (OT)”, a direct reaching of error detection on the secondary side, where 521 (including OCP module), states that the secondary-side controller 126 can “achieve circuit protection based on analysis of current and voltage conditions and the detection of faults”, further lists “OCP (over current protection), SCP (short circuit protection)” as fault conditions that the secondary side can detect and manage, demonstrating the capability to detect the presence of an error, “On detection of fault conditions, a control signal may be sent to disconnect connector 420 from the flyback transformer 130…This disconnection may be caused by an over-voltage conditions, an over-current condition, or other conditions…”, indicates the secondary side detects errors, “USB-PD modules 521 may include…an over-voltage protection (OVP) module and an over-current protection (OCP) module for providing over-current and over-voltage protection on the VBUS_IN line…”, these modules are part of the IC system 500, which includes the secondary-side controller functionality), and
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Ahmed, in combination with Freeman, Abdesselam, Kim, and Wong, are silent in regard to:
(iii) when the error is present, report error to the first control interface by causing the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error,
wherein the electrical current through the primary winding is caused to fall into the threshold range by changing a load on the transformer, the load being changed by changing a resistance of an element that is coupled to the secondary winding, and
wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range.
However, Knoedgen, further teaches:
(iii) when the error is present, report error to the first control interface by causing the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error ([Abstract], [0002], [0004]-[0011], [0013], [0015]-[0021], [0034]-[0040], [0042]-[0046], [0049]-[0050], [0052], [0054]-[0055], [0060], [0069], [0071], [0073]-[0075], [0077]-[0078], [0081], & [0083]-[0085]: teaches reporting encoded information (reported error) by changing the load on the transformer: teaches the communication mechanism to report information back to the primary side, stating that the secondary system uses an “encoding unit 170 configured to encode information (e.g., a state of charging…)” and that this “encoded information may be mapped to one or more modulation states…which are detected in a decoding unit 180 within the charging unit 140 [primary side].”, thus teaches actively reporting encoded states to the primary interface, using amplitude modulation to transmit different states to the primary side by altering the primary current, and the encoded information (error detection and/or error correction schemes (e.g., error-correcting codes), are composed of parity bits, checksums, redundancy checks, which constitute the threshold range(s), further communicated to current sensing means 203, and further passed to a demodulation and decoding unit 280, based on the type of encoded information),
wherein the electrical current through the primary winding is caused to fall into the threshold range by changing a load on the transformer ([Abstract], [0002], [0004]-[0013], [0015]-[0021], [0034]-[0040], [0042]-[0046], [0049]-[0050], [0052], [0054]-[0055], [0060], [0069], [0071], [0073]-[0075], [0077]-[0078], [0081], & [0083]-[0085]: teaches reporting encoded information (reported error) by changing the load on the transformer: “modulation unit 120 may be used to modulate a voltage drop across the rectifier…to induce a modulation on the load current.”, and the encoded information (error detection and/or error correction schemes (e.g., error-correcting codes), are composed of parity bits, checksums, redundancy checks, which constitute the threshold range(s), further communicated to current sensing means 203, and further passed to a demodulation and decoding unit 280, and teaches that the signals transmitted by precisely changing the load characteristics of the rectifier circuit connected to the secondary winding), the load being changed by changing a resistance of an element that is coupled to the secondary winding ([Abstract], [0001]-[0002], [0005]-[0006], [0008]-[0011], [0012]-[0018], [0020]-[0021], [0035]-[0039], [0042]-[0044], [0048]-[0049], [0052], [0055]-[0056], [0058], [0061], [0067], [0069]-[0070], [0073]-[0074], [0076], [0078]-[0081], [0083]-[0085], [Claim 1], [Claim 3], [Claim 4], [Claim 6], [Claim 8], [Claim 9], [Claim 11], [Claim 13], [Claim 14], [Claim 16], [Claim 18], [Claim 19], & [Claim 24]: teaches physically changing the resistance of a solid-state element: “The voltage source 521 may be adjustable…By adjusting the gate voltage, the resistance of the first low side switch 511 can be adjusted, thereby adjusting the voltage drop…”), and
wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range (Table 1; [Abstract], [0001]-[0002], [0004]-[0021], [0034]-[0040], [0042]-[0046], [0048]-[0050], [0052], [0054]-[0056], [0058], [0060]-[0061], [0067], [0069]-[0071], [0073]-[0081], [0083]-[0085], [Claim 1], [Claim 3], [Claim 4], [Claim 6], [Claim 8], [Claim 9], [Claim 11], [Claim 13], [Claim 14], [Claim 16], [Claim 18], [Claim 19], & [Claim 24]: teaches mapping different data states to different distinct analog threshold levels: “Amplitude modulation may be achieved by controlling the total voltage drop across the rectifier to be at a limited number of N voltage values.” Table 1 illustrates configuring the gate voltage of the switches to multiple different resistance levels (State 1, State 2, State 3, etc.) to encode different specific information states).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Ahmed to incorporate the multi-state amplitude modulation signaling taught by Knoedgen. This combination addresses reporting the error by causing the electrical current through the primary winding to fall into a first threshold range for a first error type and a second threshold range for a second error type by changing the resistance of an element coupled to the secondary winding, as Knoedgen teaches transmitting encoded information by adjusting the gate voltage and resistance of a secondary switch to produce multiple distinct amplitude modulation states. Furthermore, Knoedgen teaches that these distinct resistance states modulate the current drawn through the transformer, allowing the primary-side sensing means to decode the specific transmitted information based on the resulting distinct current ranges. A POSITA would be motivated to integrate Knoedgen’s analog amplitude modulation into Ahmed’s multi-error detection system to allow the secondary controller to communicate specific, categorized fault types across the isolation barrier without requiring a dedicated, costly pulse transformer. Applying this known technique to improve similar devices represents a substitution of digital pulse communication with multi-level analog resistance modulation, yielding the predictable results of a diagnostic, single-transformer isolated power system (KSR).
Regarding dependent claim 31, Ahmed, teaches:
The system of claim 30 (Fig. 1; [0003], [0012], [0014] & [0039]-[0040]), wherein changing a level of an electrical current through the secondary winding ([0027]-[0028]: discloses a secondary-side controller that modulates current through a signal transformer (secondary winding) using a programmable current DAC)
Ahmed, in combination with Freeman, Abdesselam, Kim, and Wong, are silent in regard to:
wherein the element and the external load are coupled in series to the secondary winding.
However, Knoedgen, further teaches:
wherein the element and the external load are coupled in series to the secondary winding (Fig. 3; [0005], [0009], [0015], [0037], [0039], [0047]-[0050], & [0084]-[0085]: teaches that the element whose resistance is changed (modulation switch 323 operating in conjunction with diodes 311, 312) and the external load 330 are arranged in a series circuit path with the secondary source. Further confirms this series loop mathematically by stating: “the sum of the voltage drop across the rectifier diodes 311, 312 and the output voltage corresponds to the voltage provided by the voltage source 301…” (where voltage source 301 represents the secondary-side alternating voltage). Further, “A modulation of the output voltage leads to a modulation of the current through the load…Consequently, the modulation switch 323 can be used to modulate the current…” because the current must pass through the elements to reach the load, they are coupled in series to the secondary winding).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Ahmed to arrange the modulation element and the external load in series to the secondary winding, as taught by Knoedgen. This combination addresses the structural topology where the element and the external load are to be coupled in series to the secondary winding, because Knoedgen discloses arranging the modulating resistance switches (e.g., modulation switch 323 or active rectifier switch 511) in the series power path between the secondary winding and the external load 330. A POSITA would be motivated to utilize Knoedgen’s series-coupled modulation element with Ahmed’s secondary-side architecture to ensure that the induced resistance changes efficiently restrict the main power flow to the load. Applying this known technique to improve similar devices yields the predictable result of an amplitude-modulated signaling system that provides sensitive and safe current-adjusting across the isolation barrier, avoiding the need for dangerous parallel short-circuit pathways that could damage the transformer (KSR).
Regarding dependent claim 32, Ahmed teaches:
The system of claim 31 (Fig. 1; [0003], [0012], [0014] & [0039]-[0040]),
Ahmed, in combination with Freeman, Abdesselam, Kim, and Wong, are silent in regard to:
wherein the current control device includes a transistor, and the configuration setting includes a gate voltage for the transistor.
However, Knoedgen, further teaches:
wherein the current control device includes a transistor ([0059]-[0061]: discloses that the devices used to modulate the voltage drop and control the current are implemented as solid-state transistors: “the high side switches 513, 514 are implemented as P channel MOS (metal-oxide semiconductor) FETs (field effect transistors), whereas the low side transistors are implemented as N channel MOS FETs.”), and the configuration setting includes a gate voltage for the transistor (Table 1; [0060]-[0061] & [0071]: teaches using the gate voltage as the specific configuration parameter to dictate the resistance state: “The voltage source 521 may be adjustable thereby adjusting the gate voltage to the first low side switch 511. By adjusting the gate voltage, the resistance of the first low side switch 511 can be adjusted…” Further, Table 1 lists different gate voltage configurations (e.g., “Full gate voltage”, ““half” gate voltage”, etc.) utilized to set the exact voltage drop and corresponding modulation state).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the isolated power converter of Ahmed to implement the current control device as a transistor utilizing a variable gate voltage for its configuration setting, as taught by Knoedgen. This combination addresses the current control device to include a transistor and the configuration setting to include a gate voltage for that transistor, because Knoedgen discloses using an adjustable voltage source 521 to provide specific, varying gate voltages to a low side switch 511 transistor to configure its resistance state. A POSITA would have been motivated to utilize Knoedgen’s method of configuring specific gate voltages on a solid-state transistor to control the current amplitude across the isolation barrier without needing to switch between a bulky physical bank of separate resistors. Utilizing this known technique to improve similar devices allows the secondary controller to step through different resistance states using a single component, resulting in a significant cost and printed circuit board (PCB) space reduction(s). This integration represents a predictable result of utilizing a solid-state transistors to achieve a precise, multi-level analog current modulation (KSR).
Regarding dependent claim 36, Ahmed teaches:
The system of claim 30 (Fig. 1; [0003], [0012], [0014] & [0039]-[0040]),
Ahmed, in combination with Freeman, are silent in regard to:
wherein the element and the external load are coupled in parallel to the secondary winding.
However, Abdesselam, further teaches:
wherein the element and the external load are coupled in parallel to the secondary winding (Fig. 1; [0037] & [0060]-[0061]: discloses the parallel topology for the control element: “the stop element 26 may be a switch connected in parallel with the secondary winding 34…”. The external load is powered from the same secondary winding, arranging the element (stop element 26) across the winding inherently places it in parallel with both the secondary winding and the downstream external load).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined analog-signaling power converted system of Ahmed and Knoedgen to arrange the signaling element in parallel to the secondary winding, as taught by Abdesselam. This combination address the structural topology requiring the element and the external load to be coupled in parallel to the secondary winding, because Abdesselam discloses a stop element 26 switch connected directly in parallel with the secondary winding 34 to manage fault signaling. A POSITA would be motivated to integrate Abdesselam’s parallel switch placement into the secondary-side architecture to provide a localized, direct pathway to manipulate the transformer’s magnetic flux independently of the main external load path. Utilizing this known technique to improve similar devices represents a substitution of a series-modulating configuration for a parallel-modulating topology, producing the predictable result of a fault reporting mechanism that safely bypasses the main load components (KSR).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/Examiner, Art Unit 2858 June 16, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 6/29/2026
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