Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on November 7, 2023, May 30, 2024, November 27, 2024, and June 18, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 7, 2026 has been entered.
Response to Amendment
The Amendment, filed on January 7, 2026, has been received and made of record. In response to the most recent Office Action, dated October 10, 2025, claims 1, 4-12, 14-18 & 29-32 are pending. Claims 1, 4, 9, 14, 16 & 29 have been amended. Claims 2-3, 13, 19-28 & 33 have been cancelled. Applicant’s amendments to the Claims have overcome each and every objection and 35 U.S.C. § 112(a) rejections previously set forth in the Final Office Action mailed October 10, 2025, hereafter referred to as the Final Office Action.
Response to Arguments
Applicant's arguments filed on January 7, 2026, have been entered and fully considered. In light of the amendments, the rejections have been withdrawn. However, upon further consideration, new grounds of rejections have been made, and applicant’s arguments are rendered moot.
In response to the applicant’s arguments, see pages 8-18 of applicant’s remarks, with respect to the rejection of independent claim 1 under U.S.C. § 103 Khamesra (US2024/0280645A1), in view of Abdesselam (US12341499B2), as cited by the applicant, fail to disclose, teach, or suggest individually or in combination, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”.
A new ground of rejection is made over Khamesra (US2024/0280645A1), in view of Abdesselam (US10008947B2//US2017/033698A1), and further in view of Djenguerian (US2014/0204624A1), for independent claim 1. The examiner respectfully disagrees with the applicant’s contentions that Khamesra, in view of Abdesselam, now in light of new prior art reference, Djenguerian, fail to disclose, teach, or suggest individually or in combination, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”. Khamesra, in view of Abdesselam, and further in view of Djenguerian, further disclose the additional limitations that have been amended and included in independent claim 1, and meet these requirements. Therefore, the Applicant’s arguments are unconvincing and the rejections of amended independent claim 1, and dependent claims, including claims 4-8, which depend from and incorporate the limitations of claim 1, are respectively maintained. Rejections based on the newly cited prior art reference follow.
In response to the applicant’s arguments, see pages 8-18 of applicant’s remarks, with respect to the rejection of independent claim 9 under U.S.C. § 103 Freeman (US2016/0126852A1), in view of Abdesselam (US12341499B2), as cited by the applicant, fail to disclose, teach, or suggest individually or in combination, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”.
A new ground of rejection is made over Freeman (US2016/0126852A1), in view of Abdesselam (US10008947B2//US2017/033698A1), and further in view of Djenguerian (US2014/0204624A1), for independent claim 9. The examiner respectfully disagrees with the applicant’s contentions that Freeman, in view of Abdesselam, now in light of new prior art reference, Djenguerian, fail to disclose, teach, or suggest individually or in combination, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”. Freeman, in view of Abdesselam, and further in view of Djenguerian, further disclose the additional limitations that have been amended and included in independent claim 9, and meet these requirements. Therefore, the Applicant’s arguments are unconvincing and the rejections of amended independent claim 9, and dependent claims, including claims 10-12 & 14-18, which depend from and incorporate the limitations of claim 9, are respectively maintained. Rejections based on the newly cited prior art reference follow.
In response to the applicant’s arguments, see pages 8-18 of applicant’s remarks, with respect to the rejection of independent claim 29 under U.S.C. § 103 Vemuri (US10008947B2), in view of Abdesselam (US12341499B2), as cited by the applicant, fail to disclose, teach, or suggest individually or in combination, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”.
However, upon review of the current claim listing filed on January 7, 2026, independent claim 29 does not contain the recited limitation, “wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold”. The argument appears to be based on an amendment that was not entered or was omitted from the claims as filed. Amended independent claim 29 contains the following recited limitation, “report the error to the first control interface by decreasing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer.”
A new ground of rejection is made over Vemuri (US10008947B2//US2017/033698A1), in view of Abdesselam (US12341499B2//US2023/0014264), and further in view of Yang (US2022/0155383A1), for independent claim 29. The examiner respectfully disagrees with the applicant’s contentions that Vemuri, in view of Abdesselam, now in light of new prior art reference, Yang, fail to disclose, teach, or suggest individually or in combination, “report the error to the first control interface by decreasing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer.” Vemuri, in view of Abdesselam, and further in view of Yang, further disclose the additional limitations that have been amended and included in independent claim 29, and meet these requirements. Therefore, the Applicant’s arguments are unconvincing and the rejections of amended independent claim 29, and no dependent claims, are respectively maintained. Rejections based on the newly cited prior art reference follow.
In response to the applicant’s arguments, see pages 8-18 of applicant’s remarks, with respect to the rejection of independent claim 30 under U.S.C. § 103 Ahmed (US2024/0283352A1), in view of Freeman (US2016/0126852A1), and further in view of Abdesselam (US12341499B2), as cited by the applicant, fail to disclose, teach, or suggest individually or in combination, “wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range” and “the use of different electrical current ranges to signify different error types”.
A new ground of rejection is made over Ahmed (US2024/0283352A1), in view of Freeman (US2016/0126852A1), and further in view of Abdesselam (US10008947B2//US2017/033698A1), for independent claim 30. The examiner respectfully disagrees with the applicant’s contentions that Ahmed, in view of Freeman, and further in view of Abdesselam, fail to disclose, teach, or suggest individually or in combination, “wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range” and “the use of different electrical current ranges to signify different error types”. However, upon re-examination, Ahmed, in view of Freeman, and further in view of Abdesselam, further disclose the limitations in independent claim 30, and meet these requirements. Please see MPEP 2143(I)(A). Freeman, further teaches the limitations in Figs. 78-80; [0325]-[0330], [0339], [0355], [0430], [0440] & [Claim 6]: discloses a “window comparator” logic that divides the primary current into multiple distinct ranges (windows 1, 2, 3, etc.), using this for gain control/feedback, and also links the sensing to alarms and error states), the combination of prior art references is further explained below. Therefore, the Applicant’s arguments are unconvincing and the rejections of previously presented independent claim 30, and dependent claims, including claims 31-32, which depend from and incorporate the limitations of claim 30, are respectively maintained. Updated rejections based on the cited prior art references follow.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 & 30-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "wherein the threshold is less than a lower bound of the normal operating range…" in ll. 1-2, without previous disclosure resulting in a lack of antecedent basis for this claim limitation. For examination purposes, examiner interprets the claim limitation as “wherein the threshold is less than a lower bound of a normal operating range…”.
Claim 30 recites the limitation, “and (iii) when an error is present, report error to the first control interface…” in ll. 11-12, where “an error” is disclosed within the same sentence. The repeated recitation of “error” introduces indefiniteness to the claim. For examination purposes, the examiner interprets “error” to refer to “an error” from claim 30. Claims 31-32 are rejected by virtue of dependency on claim 30, which do not rectify the defect.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Khamesra et al. (US 2024/0280645 A1, Fil. Date Jun. 12, 2023, hereinafter Khamesra), in view of Abdesselam (US 2023/0014264 A1 Fil. Date Jul. 13, 2022, hereinafter Abdesselam), and further in view of Djenguerian et al. (US 2014/0204624 A1, Pub. Date Jul. 24, 2014, hereinafter Djenguerian).
Regarding independent claim 1, Khamesra, teaches:
A system (Figs. 1-2; [Abstract] & [0020]), comprising:
a transformer having a primary winding and a secondary winding (Figs.1-2; [0020]-[0027]: “a flyback transformer 106 having a first winding (NP1) on a primary side 108” and “a secondary winding (NS) on a secondary side 110”), the primary winding and the secondary winding being arranged to power an external load (Figs. 1-2; [0020]-[0027]: discloses the flyback transformer 106 with a primary side 108 and the secondary side 110 that provides a DC output voltage to an output port/connector 128, which is the external load);
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Khamesra, is silent in regard to:
a first control interface that is coupled to the primary winding, the first control interface being arranged to: (i) detect an electrical current through the primary winding and (ii) output a fault signal in response to detecting that the electrical current through the primary winding has crossed a threshold; and
a second control interface that is coupled to the secondary winding, the second control interface being configured to: (i) provide an electrical current received from the transformer to the external load, (ii) detect whether an error is present in the system, and (iii) in response to detecting the error, report the error to the first control interface by changing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to cross the threshold,
However, Abdesselam, further teaches:
a first control interface that is coupled to the primary winding (Fig. 1; [0017]), the first control interface being arranged to: (i) detect an electrical current through the primary winding (Fig. 1; [0023]-[0024], [0031], [0038], [0040]-[0041], [0053]-[0055], [Claim 1] & [Claim 6]: primary circuit 10 includes a “primary circuit malfunction detector” 17 with a “short-circuit detector” 18 that is able to “detect an overcurrent in the primary circuit” and is able to “detect an opening fault…and/or a short-circuit fault”) and (ii) output a fault signal in response to detecting that the electrical current through the primary winding has crossed a threshold (Fig. 1; [0053]-[0059]: detection is based on the control current it crossing a threshold (e.g., >100 mA)); and
a second control interface that is coupled to the secondary winding (Fig. 1; [0017]-[0018]), the second control interface being configured to: (i) provide an electrical current received from the transformer to the external load (Fig. 1; [0017]-[0019], [0022], [0031], [0038], [0041]-[0044] & [0052]), (ii) detect whether an error is present in the system (Fig. 1; [0017]-[0019], [0022], [0031], [0041]-[0044], [0052] & [0059]-[0062]), and (iii) in response to detecting the error (Fig. 1; [0017]-[0019], [0022], [0028], [0031], [0038], [0041]-[0044], [0052] & [0059]-[0062]), report the error to the first control interface by changing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to cross the threshold (Fig. 1; [0017]-[0019], [0022], [0028], [0031], [0038], [0041]-[0044], [0052]-[0057], [0059]-[0066] & [Claim 8]: discloses the secondary circuit 20 includes a “power and fault detection controller” 21 that (i) is connected to the power transistor (load equivalent), (ii) detects malfunctions of the secondary circuit or power transistor, and (iii) “comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection”, where the action of short-circuiting the secondary winding changes the current in the secondary winding, which “when a short circuit occurs in the secondary circuit 20, an overcurrent then forms in the primary circuit 10, …this overcurrent is detected directly by the short-circuit detector 18”, which in turn “causes the primary winding current to cross a threshold”, communicating the fault to the primary side),
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first control interface that is coupled to the primary winding, the first control interface being arranged to: (i) detect an electrical current through the primary winding and (ii) output a fault signal in response to detecting that the electrical current through the primary winding has crossed a threshold, and a second control interface that is coupled to the secondary winding, the second control interface being configured to: (i) provide an electrical current received from the transformer to the external load, (ii) detect whether an error is present in the system, and (iii) in response to detecting the error, report the error to the first control interface by changing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to cross the threshold, of Abdesselam to Khamesra, in order to improve, by combining the references, where Khamesra discloses a modern power converter system with a transformer and sophisticated controllers on both the primary and secondary sides, where the secondary controller is responsible for providing power to a load and detecting various fault conditions, implementing the robust and safe power converter that provides a reliable communication channel from the secondary side back to the primary side to report faults of Abdesselam, where the secondary-side controller can create a change in the load on the secondary winding (e.g., a short circuit) which is reflected as a detectable overcurrent condition on the primary side, and integrating the fault reporting mechanism, also taught by Abdesselam, that would allow Khamesra’s secondary-side controller to alert Khamesra’s primary-side controller of critical faults by using Abdesselam’s technique, making the overall system safer and more reliable without any additional components, arriving at the claimed invention with predictable results (KSR).
Khamesra, in combination with Abdesselam, are silent in regard to:
wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold,
wherein the bypass path is coupled in parallel with the second control interface between the first end of the secondary winding and the second end of the secondary winding, and
wherein the bypass is part of a current control device that is coupled to the secondary winding in parallel with the second control interface.
However, Djenguerian, further teaches:
wherein changing the level of the electrical current through the secondary winding includes changing a resistance of a bypass path that extends from a first end of the secondary winding to a second end of the secondary winding (Figs. 1 & 7; [0025], [0049]-0051] & [0056]: teaches “first power circuit 152 is coupled to forward terminal FWD 128-4…transferring charge…to bypass terminal BP 128-6”, the FWD terminal connects to “node 162…of secondary winding 116”, includes switches (MOSFETs 700/704) which change resistance to enable current flow ) so as to cause the electrical current through the primary winding to drop to a value that is greater than a minimum current draw of the transformer and less than the threshold ([0025], [0067], [0069]-[0071], [0081] & [0100]: during faults or startup, when main load is off/low, the first power circuit is enabled to draw operating current, current is small (maintenance level) compared to a full load, primary side sees a current drop (from full load) but maintains a level sufficient to power the secondary chip (greater than zero/minimum) and less than a threshold),
wherein the bypass path is coupled in parallel with the second control interface between the first end of the secondary winding and the second end of the secondary winding (Fig. 1; [0048]-[0051]: first power circuit 152 is parallel to the main output path (synchronous rectifier 132) and the second control interface (controller 120) logic and bypass regulation circuit 156), and
wherein the bypass is part of a current control device that is coupled to the secondary winding in parallel with the second control interface (Figs. 1 & 7; [0048]-[0051] & [0100]-[0101]: first power circuit 152 is the current control device, physically integrated with the secondary controller, but acts as a distinct parallel current path from the winding).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivating experimentation and optimization. Khamesra establishes the base isolated power converter system with primary and secondary controllers and basic fault protections. Abdesselam teaches communicating information from the secondary side to the primary side, detecting various faults, which the primary side detects, providing the motivation to modify Khamesra’s systems to include a secondary-side active reporting mechanism, active signaling capability. Djenguerian provides the bypass path hardware (a parallel current control device connected to the secondary winding), for powering the controller during low-voltage/startup conditions, and draws a controlled current (changing resistance) that results in a primary current level distinct from the main load current (greater than minimum, less than a high-load threshold), when uses as the signal load as suggested by Abdesselam. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 4, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0029]-[0030] & [0041]), wherein the threshold is less than a lower bound (Fig. 3; [0005] & [0029]-[0033]): “the controller 208 issues an RSENSE short detect interrupt responsive to the output of the low-side CSA 206 being reduced (e.g., lower than a first threshold) and the turn-on pulse of the PWM control signal being wider (e.g., greater than a second threshold)”, teaches a fault detection method based on the measured output current falling below a specific threshold, this is the definition of an undercurrent threshold set below the normal operating range, where the fault detection is triggered when the measured output is abnormally low, Fig. 3, illustrates in the flowchart the first step of the fault detection method (block 304) is the comparison: “IOUT < CURRENT THRESHOLD?”) of the normal operating range (Fig. 3; [0005] & [0029]-[0033]: “at 304, the output current, IOUT, is compared to a threshold”, checks if current < threshold, “at 306, the PWM width is compared to a PWM threshold”, checks if PWM width > threshold, and “if the conditions of 204 and 206 are both met at 308, an RSENSE fault interrupt is raised”, step 308 fault triggered only if both conditions persist, teaches a fault detection method based on the measured output current falling below a specific threshold, this is the definition of an undercurrent threshold set below the normal operating range, where “the output of the low-side CSA 206 being reduced (e.g., lower than a first threshold)…”) of the electrical current draw of the transformer (Figs. 2-3; [0022] & [0027]-[0033]: 134, RSENSE 134, “a first node of the RSENSE resistor 134 is connected to a current sensing negative pin (CSN) 144 of the secondary-side controller 104, and a second node connected to the negative terminal of the DC output and to a current sensing positive pin (CSP) 146, to enable the secondary-side controller 104 to sense the output current, IOUT, from the power converter 100”) and greater than the minimum current draw of the transformer (Fig. 3; [0029]-[0033]: “if the fault count meets a threshold, such as N, as 314, the RSENSE fault condition is raised at 316, such as by the firmware 214 and the method 300 stops at 318” and “if the fault count does not meet a threshold at 316, a wait interval, such as M ms, is implemented at 320 and the method 300 returns to 304 and 306 to determine if the RSENSE fault persists” and “current through the RSENSE resistor 134 is lower than the first threshold and the pulse-width counter is higher than the second threshold, the controller 208 raises an interrupt to indicate an RSENSE short fault”, where “firmware 214 checks for the persistence of this interrupt multiple times (e.g., present for N-times sampled after intervals of M ms) before asserting an RSENSE short condition signal”, the core teaching is to detect a fault by identifying when the measured current is less than a predetermined threshold, which by definition, is less than the lower bound of the normal operating range, purpose is to detect an abnormally low reading, but would have to be greater than a minimum current to be a functional electronic measurement).
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Regarding dependent claim 5, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0029]-[0030], [0041] & [0046]),
Khamesra, in combination with Abdesselam, are silent in regard to:
wherein the first control interface is formed on a first semiconductor die and the second control interface is formed on a second semiconductor die.
However, Djenguerian, further teaches:
wherein the first control interface is formed on a first semiconductor die ([0031]-[0032]: discloses the primary controller (first control interface) formed on a first integrated circuit die) and the second control interface is formed on a second semiconductor die ([0031]-[0032]: discloses the secondary controller (second control interface) formed on a distinct second die to ensure they are “galvanically isolated from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date, where Khamesra discloses that the system’s modules (primary/secondary controller) may be implemented on different semiconductor dies, Djenguerian teaches separating the primary and secondary controllers onto different dies to maintain galvanic isolation, therefore applying the dual-die configuration of Djenguerian to the USB-PD system of Khamesra to achieve the necessary galvanic isolation and voltage handling capabilities required by a transformer-based design, combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 6, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0029]-[0030], [0041] & [0046]), further comprising a transistor that is coupled between the transformer and the second control interface (Fig. 2; [0022]: 132, “the power converter 100 includes, on the secondary side 110, a synchronous rectifier (SR) field effect transistor 132 (SRFET) connected between the flyback transformer 106 and through a current sense resistor 134 (RSENSE) to a negative terminal of the DC output”, the SRFET 132 is a transistor coupled between the secondary winding of the flyback transformer 106 and the secondary-side controller 104), the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding (Fig. 2; [0022]: “the SRFET 132 includes a drain node 132A connected to the fourth terminal of the flyback transformer 106, and through a resistor 136, to an SR sense pin (SR_SEN 138) of the secondary-side controller 104 to sense a voltage on the drain node 132A of the SRFET 132, a gate node 132B connected to an SR gate drive pin (SR_DRV 140) of the secondary-side controller 104 to drive or control the SRFET 132, and a source noted connected to the negative DC output and to the secondary-side controller 104 through a SR-VSS ground voltage pin (SR-VSS) 142)” and “a first node of the RSENSE resistor is connected to a current sensing pin (CSN) 144 of the secondary-side controller 104, and a second node connected to the negative terminal of the DC output and to a current sensing positive pin (CSP) 146, to enable the secondary-side controller 104 to sense the output current, IOUT, from the power converter 100”, the SRFET 132 has its drain connected to the transformer and its source connected towards the output, and the gate of SRFET 132 is controlled by the secondary-side controller), wherein the error is reported to the first control interface ([0025]-[0027 & [0029]-[0030]: teaches the secondary-side controller 104 identifies a fault condition (e.g., an RSENSE short), the primary-side controller 102 needs to be informed to disable the converter, a communication path exists across the isolation barrier 156)
Khamesra, is silent in regard to:
and a gate that is coupled to the second interface, wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to reduce a resistance of a path between the source and the drain of the transistor.
However, Abdesselam, further teaches:
and a gate that is coupled to the second interface ([0053]-[0066]: teaches that the stop element is controlled, “driven by,” the secondary-side power and fault detection controller 21), wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor ([0053]-[0066]: secondary controller detects the fault (error) and applies a voltage to the control terminal (gate) of the stop element to activate it (close the switch)) so as to reduce a resistance of a path between the source and the drain of the transistor ([0053]-[0066]: teaches the key concept, the “stop element” (which is a transistor), when activated is used to create a short-circuit (low resistance path) between its source and drain across the winding, the reduced resistance allows an overcurrent to flow, which signals the error to the primary side, by changing a voltage that is applied at the gate of the transistor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Abdesselam’s stop element mechanism, wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to reduce a resistance of a path between the source and the drain of the transistor, to Khamesra, in order to improve, by combining both prior art references, achieve the claimed error reporting function, where Khamesra seeks reliable fault protection, disclosing a USB-PD system with a secondary-side controller that detects faults (e.g., RSENSE short) and must communicate this to the primary side to disable the converter, and teaches a communication path (e.g., a pulse transformer) and a transistor (SRFET 132) on the secondary side, while Abdesselam addresses isolating fault reporting, ensuring the primary side shuts down immediately upon a secondary fault, further teaching that a fault in the secondary circuit can be reported to the primary circuit by using a “stop element” (a transistor) to short-circuit the secondary winding of the pulse transformer, creating an overcurrent condition on the primary side, which is detected as a fault signal, using the existing SRFET 132 (or a similar transistor) not just for rectification, but also as the “stop element”, by driving the gate of the SRFET to create a low-resistance path (a short) across the transformer winding upon detecting a fault like an RSENSE short of Khamesra, could induce an overcurrent detectable by the primary-side controller, achieving the error reporting function without the need for additional complex components (i.e., optocouplers), and providing a robust fault-reporting mechanism, combining prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 7, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0027]-[0030], [0041] & [0046]), further comprising a power switch (Figs. 1-2; [0022] & [0027]: 118 & 132, where “a synchronous rectifier (SR) field effect transistor 132 (SRFET) connected between the flyback transformer 106 and through a current sense resistor 134 (RSENSE) to a negative terminal of the DC output”, “the SRFET 132 includes a drain node 132A connected to the fourth terminal of the flyback transformer 106, and through a resistor 136, to an SR sense pin (SR_SEN 138) of the secondary-side controller 104 to sense a voltage on the drain node 132A of the SRFET 132”, describes a “power converter 100” configured for “DCM operation” which is a type of switch-mode power system, includes a transformer 106, “The SRFET 132 includes…a gate node 132B connected to an SR gate drive pin (SR_DRV140) of the secondary-side controller 104 to drive or control the SRFET…”, and a primary-side controller 102, and a secondary-side controller 104 that controls the switching cycle, the SRFET 132 is a power switch), wherein the power switch, is coupled between the second control interface and a switching cell (Figs. 1 & 2; [0020] & [0022]-[0027]: 106,118, 124, 126, & 132, flyback transformer 106, primary switch 118, SRFET 132, and capacitors 124/126, the SRFET 132 is the power switch, the SR_DRV 140 gate pin drive of the secondary-side controller 104 to drive or control the SRFET 132, and the “switching cell” is the path through the transformer 106 and the SRFET itself), of a switch-mode power system ([0020] & [0022]-[0027]: the SRFET (power switch) gate is coupled to the secondary controller 104, the drain/source are coupled to the transformer secondary winding (NS) and output filter, forming the secondary switching cell of the flyback converter (switch-mode system)), and the power switch is turned on and off based on a direction of the electrical current through the secondary winding ([0020] & [0022]-[0027]: secondary-side controller 104 senses the drain voltage (SR_SEN138) to determine when to switch the SRFET 132, the voltage polarity corresponds to the direction of current (forward vs. reverse), where the system monitors when the secondary current “decreases to zero” (end of forward conduction/direction change) to manage the switching state (e.g., turn off SRFET/signal primary)).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Khamesra, in view of Abdesselam, in view of Djenguerian, and further in view of Freeman et al. (US 2016/0126852 A1, Pub. Date May 5, 2016, hereinafter Freeman).
Regarding dependent claim 8, Khamesra teaches:
The system of claim 1 (Figs. 1-2; [Abstract], [0005], [0020], [0022], [0027]-[0030], [0041] & [0046]),
Khamesra, is silent in regard to:
wherein the first control interface includes: one or more magnetic field sensing elements that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer; and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements.
However, Freeman, further teaches:
wherein the first control interface includes: one or more magnetic field sensing elements (Fig. 1 & 66; [0038], [0103], [0106]-[0115], [0125] & [0140]-[0144]: discloses the use of Hall Effect sensors (magnetic field sensing elements) in the sensing circuit) that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer (Fig. 3; [0125]: teaches using a magnetic field sensor for this purpose, voltage sensing circuit 62, “the sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field being generated within the transformer.”, “the Hall Effect sensors facilitate determining a zero-crossing of the transformer by directly sensing the magnetic field being generated by the transformer during operation.”); and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements (Fig. 3; [0038], [0103], [0125], [0133]-[0134], [0143], & [0248]: teaches that the signal from the Hall Effect sensor is sent to the controller (“processing circuitry”) for use in regulating the converter, where the Hall Effect sensor, when used to sense the magnetic field of a transformer winding, produces a signal proportional to the current in that winding, and the controller (“processing circuitry”) can use this signal for detection purposes (e.g., zero-crossing, which is a current detection event) and to “detect the electrical current”).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first controller interface in the presence of a transformer and primary winding with one or more magnetic field sensing elements and processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, of Freeman to Khamesra, in order to improve the circuitry and magnetic field sensing (via Hall Effect sensors) on the primary side transformer within a control interface to detect current-related phenomena (zero-crossing) for regulation purposes, the substitution would be to gain the known advantages of magnetic current sensing, such as improved electrical isolation, can detect magnetic flux saturation or zero-crossings more directly than measuring voltage drops across a sense resistor, and lower power loss (no power dissipated in a series senses resistor), substituting one known current sensing technique for another, since it has been held to be within the general skill in the art to incorporate a known technique to improve similar devices in the same way is obvious, achieving a predictable improvement in performance (KSR).
Claims 9-12 & 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Freeman, in view of Abdesselam, and further in view of Djenguerian.
Regarding independent claim 9, Freeman teaches:
A system (Figs. 2 & 4; [Abstract], [0032] & [0133-[0134]), comprising:
a transformer having a primary winding and a secondary winding (Figs. 2, 13, & 72; [Abstract], [0032], [0125] & [0133]-[0134]: 102, the primary voltage reduction circuit 98 includes a transformer 102.”, “The primary side of the transformer 102 is connected to the primary power circuit 26 and the secondary side of the transformer 102 is connected to the secondary voltage reduction circuit 100.”);
a first control interface that is coupled to the primary winding of the transformer (Fig. 71; [0032], [0038], [0100], [0106], [0125] & [0133]-[0134]: 102, 103, 106, & primary side regulation circuit, the primary side regulation circuit 240 and transformer control circuit 103 are coupled to the primary winding, Fig. 71 illustrates the primary side regulation circuit 240 coupled to the primary winding, “a primary side regulation circuit coupled to a primary side of the transformer” which includes a “controller configured to generate a pulse-width modulated control signal…to regulate the transformer”, “the primary side regulation circuit includes a switching device that is coupled to the primary side of the transformer, a current sense circuit that is configured to sense a current level on the primary side”, “transformer control circuit 103 may include a primary side current sense circuit 107 that is connected to the primary side of the transformer 102 to sense the load current and the load voltage”, The control circuit 103 uses a current sense resistor 109 and measures across the primary winding”, “The control circuit 103 is configured to sense the load current on a pulse by pulse basis and sense the peak current.”, “power module includes the advanced power supply system on a chip (TroniumTM PSSoC), which is the subject of this present invention, including a controller application specific integrated circuit (ASIC)” that manages power conversion, and the Tronium PSSoC serving as the central control interface coupled to the transformer’s primary side), the first control interface being arranged to: (i) detect an electrical current through the primary winding (Fig. 72; [Abstract], [0038], [0100], [0125], [0133]-[0134], [0163], & [0248]: 102, 103, 107 & 109, “the transformer control circuit 103 may include a primary side current sense circuit 107 that is connected to the primary side of the transformer 102 to sense the load current and the load voltage”, “current sense circuit configured to sense a current level on the primary side”, ”control circuit 103 uses a current sense resistor 109 and measures across the primary winding.”, “The control circuit 103 is configured to sense the load current on a pulse by pulse basis and sense the peak current”, “Current Sense Amplifier of the Tronium PSSoC senses the voltage across the external current sense resistor at pins RCSP and RCSN. This voltage is sampled and held by a switched-capacitor difference amplifier and digitized by the on-chip general purpose ADC.”, “current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop as well as error reporting. The current can be measured by an ADC or through a series of comparators with varying thresholds.”) and (ii) take a remedial action in response to the electrical current through the primary winding crossing a threshold ([Abstract], [0107]-[0108], [0163], [0186], [0202], [0251], [0253], & [0304] : “controller configured to generate a pulse-width modulated control signal delivered to the switching device as a function of the sensed current level to regulate the transformer”, “output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage”, “the state machine or microprocessor continually monitors the output voltage current for an over-or-under-current alarm condition”, “Over-current condition: The system sets the over-current status bit. If sleep mode is not disabled, the system transitions to sleep mode (SM);”, “Actions take to protect against thermal damage may include de-rating of output power and complete shut-down of output.”, “output can be disabled as a result of error detection or as a result of low output current or output power situation”, “the Tronium PSSoC has entered into a low current shut-down state, it will intermittently re-apply output power to the end device in order to check whether or not it now requires power above certain threshold”, and “the controller 106 may sense a current level of the output power signal and adjust the duty cycle as a function of the sensed current level”, where the control interface is arranged to take remedial actions (e.g., regulation, disabling circuits, shut-down, de-rating, entering sleep mode) based on sensed/detected current thresholds); and
a second control interface that is coupled to the secondary winding of the transformer (Figs. 30 & 72; [0098], [0103], [0111], [0122], [0125], [0133]-[0134], [0140], [0174], [0250], [0256], [0258]-[0259] & [0263]: the secondary voltage reduction circuit 100 and any external microprocessor or feedback control on the secondary side constitute the second control interface, a specific “second control interface” part number isn’t explicitly provided, the “external microprocessor and voltage sense circuits” [0174] and “microcontroller, standalone ADC, or secondary ASIC” [0258] on the secondary side, collectively function as the second control interface, “a control circuit to operate the MOSFET to regulate the voltage at the output of the forward converter as a load current is drawn from the secondary-side of the transformer” indicates a control mechanism on the secondary side, “the Tronium PSSoC also provides a PID switching controller with which to drive the primary side of a transformer if isolation is required, or other topologies of conversation and regulation. It also features either a secondary or primary side control/feedback”, “the sensing circuit 62 includes a secondary side Hall Effect sensor that is coupled to the secondary side of the transformer, and is connected to the forward controller (shown in Fig. 13) for transmitting a signal indicative of the transformer magnetic field for use in determining the time at which the transformer reaches the “zero-crossing”.” identifies a sensor on the secondary side connected to the controller, “Feedback for the Universal loop is provided by the external microprocessor and voltage sense support circuits, and is input to the Tronium pin as a serial data stream” where the feedback originates from the secondary side where the output voltage is sensed, “Feedback to the PID loop can be from either a digital source for example, but not limited to, a serialized ADC stream or analog signal, both of which are dependent on the output of the circuit. This feedback can provide information relating regulated output current or voltage” where the output of the circuit is on the secondary side, “module can take many forms, which can include either analog or digital feedback of the output to the ASIC, or the ASIC can operate in open loop mode with no feedback”, “sensing capabilities within the module are meant to supplement or replace the measurements taken by ASIC” the output is on the secondary side, “Digital Feedback Description. The digital feedback module includes a microcontroller, standalone ADC, or secondary ASIC in order to monitor the output voltage and to allow very precise measurements to be taken at the output connection”, functions as a second control interface on the secondary side, “Analog Feedback Description” where “the current through an opto-isolation LED is proportional to the output voltage”, another form of secondary side feedback.), the second control interface being configured to: (i) power an external device with power that is received via the secondary winding (Figs. 1 & 14; [0098], [0121]-[0122], [0133]-[0134], [0149] & [0263]: the output of the secondary side circuitry (e.g., VOUT) to power consumer electronic devices, figure illustrates connection to electronic device 20), (ii) detect whether an error is present in the external device (Figs. 33 & 80; [0068], [0107], [0134], [0163], [0186], [0202], [0233]-[0234], [0246]-[0249], [0251] & [0253]: teaches the controller monitors output conditions such as current and temperatures, which would indicate an error in the connected external device (e.g., a short circuit causing an overcurrent), flowchart for “low-current detection and an error detection Fig. 33, a state diagram including “ERROR” states for “Error Condition” and “Over Current/Over Temperature Error Condition” in Fig. 80, “output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage”, establishes the concept of error detection and remedial action(s) within the system, “Control State Machine or microprocessor continually monitors the output voltage current for an over-or-under-current alarm condition”, the monitoring of output voltage/current is for error detection related to the device powered by the transformer, “Over-current condition” and ”Under-load condition” and “Under-load condition” described as detectable errors that are monitored by the system, “an on-board temperature sensor” provides “ample protection from over temperature situations”, “Actions taken to protect against thermal damage may include de-rating of output power and complete shut-down of output.”, where this is an example of detecting an error (over temperature) within the system, “output can be disabled as a result of error detection or as a result of low output current or output power situations such as arises when a connected device that includes a battery is done charging the battery and the Tronium PSSoC is only providing power to the non-battery charging functionality”, directly pointing error detection (low output current/power, device done charged) to the device powered by the transformer), and
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Freeman, is silent in regard to:
(iii) in response to detecting the error, report the error to the first control interface by changing a level of the electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum draw of the transformer.
However, Abdesselam, further teaches:
(iii) in response to detecting the error (Fig. 1; [0017]-[0019], [0022], [0028], [0031], [0038], [0041]-[0044], [0052] & [0059]-[0062]), report the error to the first control interface by changing a level of the electrical current through the secondary winding (Fig. 1; [0017]-[0019], [0022], [0028], [0031], [0038], [0041]-[0044], [0052]-[0057], [0059]-[0066] & [Claim 8]: discloses the secondary circuit 20 includes a “power and fault detection controller” 21 that (i) is connected to the power transistor (load equivalent), (ii) detects malfunctions of the secondary circuit or power transistor, and (iii) “comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection”, where the action of short-circuiting the secondary winding changes the current in the secondary winding, which “when a short circuit occurs in the secondary circuit 20, an overcurrent then forms in the primary circuit 10, …this overcurrent is detected directly by the short-circuit detector 18”, which in turn “causes the primary winding current to cross a threshold”, communicating the fault to the primary side)
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ combinations and sub-combinations of these complementary embodiments and otherwise motivate experimentation and optimization. Incorporating, in response to detecting the error, report the error to the first control interface by changing a level of an electrical current through the secondary winding, of Abdesselam to Freeman, in order to improve, by combining the references, where Freeman discloses a power converter system with a transformer, a first control interface (primary side regulation circuit), a second control interface (secondary power circuit) for powering an external electronic device, the first control interface includes a current sense circuit to detect the primary winding current and a controller that takes remedial action (e.g., regulating the duty cycle) when the current crosses a threshold, the second control interface monitors output voltage and current, detecting errors (such as short circuit) in the external device, Abdesselam, teaches and discloses a controller where the secondary side, upon detecting an error, short-circuits the secondary winding of the transformer, causing an overcurrent in the primary winding, which is detected by the primary-side controller’s existing overcurrent threshold detection circuit, incorporating the fault-reporting method of Abdesselam would be a simple means of communicating a fault to the primary side, making the overall system safer and more reliable without any additional components, therefore by substituting known fault-handling mechanisms for another, combining prior art elements according to known methods yield predictable results (KSR).
Freeman, in combination with Abdesselam, are silent in regard to:
so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum draw of the transformer.
However, Djenguerian, further teaches:
so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum draw of the transformer (Figs. 1; &7; [0025], [0049]-[0051], [0056], [0067], [0069]-[0071], [0081] & [0100]: during faults or startup, when main load is off/low, the first power circuit is enabled to draw operating current, current is small (maintenance level) compared to a full load, primary side sees a current drop (from full load) but maintains a level sufficient to power the secondary chip (greater than zero/minimum) and less than a threshold, further discusses charging from multiple sources to maintain bypass voltage above a “minimum value” sufficient to operate circuits).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivating experimentation and optimization. Freeman establishes the base power converter architecture using primary side regulation and current sensing. Abdesselam teaches bidirectional error reporting mechanism through a pulse transformer, where a secondary circuit changes current levels to communicate faults back to a primary circuit detector, either by short-circuiting the transformer or modifying signals to indicate a fault, providing the motivation to modify Freeman’s system to include a secondary-side active reporting mechanism, active signaling capability. Djenguerian provides further support for secondary-side control circuits that manage power and regulate bypass voltages from multiples sources, providing the bypass path hardware (a parallel current control device connected to the secondary winding), describing a bypass voltage above a minimum operational value to ensure the control interfaces remain powering during different transitions, such as the remedial actions disclosed by Freeman, “shut-down of output” or “de-rating of output power) when thresholds (like over-temperature or over-current) are crossed. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 10, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]), wherein taking the remedial action includes ([0163], [0189], [0202], [0248], [0251], [0253] & [0299]: teaches a digital control block with state machines for monitoring current and taking action on fault conditions, Tronium PSSoC 106 (contains the Current Sense Amplifier and digital control block responsible for error reporting and setting status bits), “output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage.”, describes an internal action (disabling SCVBC) where monitoring for “fault or alarm conditions” implies detection and internal signaling of such conditions, “Over-current condition: The system sets the over-current status bit.”, where setting a status bit is a form of internal fault indication that can be read or reported, “”current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop as well as error reporting.” where “error reporting” implies outputting or conveying fault information, “The output can be disabled as a result of error detection or as a result of a low output current or output power situation.”, highlights that “error detection” leads to remedial actions, and system’s ability to report errors [0248] would include signaling these detections, “I2C port is including for manufacturing settings, test, evaluation, updates, health-checks and debug.”, this port provides a communication “serial interface to support configurability of the PSSoC via an external microprocessor; or a multi-wire interface which will support two way communication between the Tronium PSSoC and the microprocessor or state machine” through which internal status bits or error reports (refer to paragraphs [0202] & [0248]) can be accessed and “outputted” to an external system for monitoring or debugging).
Freeman, is silent in regard to:
outputting a fault signal.
However, Abdesselam, further teaches:
outputting a fault signal ([0018]-[0019] & [0028]: teaches remedial process involves communicating/outputting a malfunction or fault signal between isolated primary and secondary circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date to combine the remedial shutdown/de-rating actions of Freeman with the specific fault-signaling communication method taught by Abdesselam, to ensure the primary side is notified of secondary-side errors, where Freeman establishes the framework for a system that senses primary-side current and takes remedial action (de-rating or shutdown) when thresholds are crossed, and Abdesselam provides the mechanism of “outputting a fault signal” across an isolation barrier to trigger the actions. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 11, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]), wherein taking the remedial action includes ([0041], [0163], [0182], [0202]-[0203], [0228]-[0229], [0251], [0253] & [0299]: describes a control state machine that transitions to a shutdown state in response to conditions like “over-current” or “under-load”, Tronium PSSoC 106 (controls actions described below), SCVBC 32, SWR (Switch-Mode Buck Regulator), PWM (Pulse-Width Modulation), “a vampire load elimination system that is configured to determine when a consumer device has finished charging and/or is disconnected from the power circuit, and operates the power circuit to disconnect the supply of power to the power circuit and/or the electronic device, and also capable of creating a flea powered “stand-by” mode. It is accomplished by placing the system in to “sleep mode” where the only circuits powered are the timing circuits, which periodically “wake up” to check if there is a connection or current draw”, in response to “fault or alarm conditions such as over current, allowing a digital state machine that controls the current sense feedback to disable the SCVC 32 to prevent possible damage”, disabling a circuit turns off its operation, “Over-current condition” or “Under-load condition”, the system “transitions to sleep mode (SM).”, entering sleep mode turns off most active circuits, “Sleep Mode (SM). The system disables the HF_OSC, the CP, the SWR, the forward PID, the CUR_SNS and the ADC.”, disabling these components turns off significant parts of the device’s operation, the “Tronium PSSoC digital memory has intelligence” to ”always put itself into Sleep Mode during these times to conserve energy and not re-engage in the current sensing routing of the wake-up sequencing.”, for example a powered television has not been used for a fixed period, “there could be “real-time” instructions given to the Tronium PSSoC about when to go to Sleep Mode, when to wake up, and reset, upgrade or change other preconditions”, including commands “about resets, operation, or shutdowns/restarts” of the device”, “Actions taken to protect against thermal damage may include the de-rating of output power and complete shut-down of output.” where a “complete shut-down output” implies turning off the device’s power delivery, “output can be disabled as a result of error detection or as a result of a low output current or output power situation…This can take place by turning off the PWM, switch capacitor circuit, or through de-ration of either or both subsystems”, also mentions the Tronium PSSoC entering a “low current shut-down state.”, and a failsafe circuit where if a “system should malfunction…the system would shut itself down through a failsafe circuit which would prevent the chip from accepting any more signal from the source at VLine”).
Freeman, is silent in regard to:
turning off the external device.
However, Abdesselam, further teaches:
turning off the external device ([0031], [0066] & [Claim 14]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement the “complete shut-down” taught by Freeman as a remedial action to protect the system, resulting in the “turning off” of the external device, the mechanism for the deactivation is further corroborated by the command deactivator logic taught by Abdesselam. Freeman describes a power delivery system for electronic devices (external device) and lists a complete shut-down of output as a remedial action to protect the hardware. Abdesselam reinforces this by describing the circuit logic required to execute the remedial action, teaching a command deactivator, that cancels the operation of the power stage upon detecting a fault, stopping the transfer of energy, thereby turning off the load/device connected to the secondary side. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 12, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202] & [0253]), wherein changing the level of the electrical current through the secondary winding (Fig. 72; [0132]-[0134], [0253] & [0258]: output enable transistors, no specific part numbers provided, they are components within the digital feedback module (that includes a microcontroller, a standalone ADC, or secondary ASIC), “Digital Feedback Description. The digital feedback module includes a microcontroller, standalone ADC, or secondary ASIC in order to monitor the output voltage and to allow very precise measurements to be taken at the output connection.”, further stating, “Current sensing and output enable transistors are also shown so that should a multitude of outputs be connected to the module with individual sensing at each. In this manner the low power shut-off functionality described in the ASIC description could be applied to individual loads even though the power is shared.”, where the “output enable transistors” function as “current control devices” on the secondary side, where they are coupled to the secondary winding (via individual loads) and activated (enabled/disabled) to change the current by allowing or preventing power delivery to specific loads. While the transistors are described as being part of the digital feedback description module (which serves as the “second control interface”), rather than a separate device in parallel to the entire interface, the transistors perform the function of controlling current on the secondary side and their activation (turning on/off) changes the current level through the secondary winding by enabling or disabling the load, “The output can be disabled as a result of error detection or as a result of low output current or output power situation…This can take place by turning off the PWM, switch capacitor circuit, or through de-ration of either or both subsystems.”, discusses the actions controlled from the primary side (Tronium PSSoC), and the effect would be a change in the secondary current, the “output enable transistors” from [0258] are the mechanism on the secondary side to achieve the disabling for individual loads, function as switching elements on the secondary side, when the “output enable transistors” are activated (turned on), they allow current to flow to the connected load, establishing or increasing the electrical current through the secondary winding (secondary winding suppliers power to these loads), and when the transistors are deactivated (turned off), they cut off or significantly reduce the current to the load, changing the level of electrical current through the secondary winding, and linked to “low-power shut-off functionality” for individual loads, the “output enable transistors” described as being connected to “a multitude of outputs…with individual sensing at each.”, where the outputs are on the secondary side of the transformer, where the device being powered (the load) is connected, therefore the transistors effectively coupled to the secondary winding via the loads they control).
Freeman, is silent in regard to:
includes activating a current control device that is coupled to the secondary winding in parallel with the second control interface
However, Abdesselam, further teaches:
includes activating a current control device that is coupled to the secondary winding in parallel with the second control interface (Fig. 1; [0019], [0026]-[0031], [0059]-[0064], [Claim 9] & [Claim 11]: teaches a stop element 26 (“the current control device”) that is activated in response to a fault, device is a switch connected in parallel with the secondary winding).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate activating a current control device that is coupled to the secondary winding in parallel with the second control interface, of Abdesselam to Freeman, in order to improve, by combining the references, where Freeman discloses a power converter system with primary and secondary side control interfaces, where the secondary controller powers an external device and can detect fault conditions. Abdesselam, teaches and discloses a stop element, as a switch connected in parallel across the secondary winding, which is the current control device and is driven by the secondary-side controller, upon detecting a fault, signals a fault to the primary side, allowing the system to drawn a high current or collapse the voltage, the device is activated to short-circuit the secondary winding, changing the current level. Incorporating the fault-reporting circuit of Abdesselam into the power converter of Freeman, would provide a simple mechanism for communicating a secondary-side fault to the primary side, would involve adding the parallel current control device taught by Abdesselam to the secondary side of Freeman’s transformer, where the secondary-side controller already performs a fault detection, making the overall system safer and more reliable without any additional components. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 14, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0133]-[0134], [0163], 0177], [0181], [0202], [0207] & [0253]), wherein the threshold is less than a lower bound of a normal operating range of an electrical current draw of the transformer (Figs. 3, 66, & 72; [0041], [0098], [0102]-[0104], [0107], [0112], [0140], [0144], [0174], [0180], [0182]-[0183], [0186]-[0187], [0202]-[0203], [0217], [0229] & [0467]: teaches a controller that monitors for and reacts to a low current condition by comparing the current to a threshold set below the normal operating range, Tronium PSSoC 106 (contains the Control State Machine and current sensing capabilities), “the switch capacitor voltage divider circuit is configured to deliver up to 50 mA and maintain a ≥95% efficiency across the range of load currents from 50 mA to less than 1 mA under light load conditions.”, indicating that 50 mA is a lower bound for a normal operating range, and the system operates below this for “light load conditions.”, “the forward converter control loop may be configured to regulate the output voltage under heavy fluctuation (4.5 nA to 4.5 A) of load current without triggering any instability.”, indicating that 4.5 nA (nanoamperes) is a low end of the normal operating range for the forward converter, a threshold for ‘under-load” would be below this operating range, note that “Control State Machine or microprocessor continually monitors the output voltage current for an over-or-under-current alarm condition.”, where an “under-current” alarm condition indicates a threshold below the normal operating range, also note that ”Under-load condition: if the LCSD EN pin is high and sleep mode is not disabled, the system transitions to sleep mode (SM).”, where the “under-load condition” is triggered by a threshold that is below the normal operating range, which causes the system to enter a low-power state, where “the Control State Machine can disable the SWR Buck Regulator if the load current decreases to the programmed digital threshold”, where the “programmed digital threshold” that disables the buck regulator due to a decreasing load current would be below the normal operating range, and “The output can be disabled as a result of error detection or as a result of a low output current or output power situation such as arises when connected device that includes a battery is done charging the battery and the Tronium PSSoC is only providing power to the non-battery charging functionality.”, where the “low output current or output power situation” refers to a threshold below normal operation)
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Freeman, in combination with Abdesselam, are silent in regard to:
and greater than the minimum current draw of the transformer.
However, Djenguerian, further teaches:
and greater than the minimum current draw of the transformer (Figs. 1; &7; [0021], [0025], [0049]-[0051], [0056], [0067], [0069]-[0071], [0081] & [0100]: during faults or startup, when main load is off/low, the first power circuit is enabled to draw operating current, current is small (maintenance level) compared to a full load, primary side sees a current drop (from full load) but maintains a level sufficient to power the secondary chip (greater than zero/minimum) and less than a threshold, further discusses charging from multiple sources to maintain bypass voltage above a “minimum value” sufficient to operate circuits).
It is recognized that the citations and evidence provided above are derived from potentially different embodiments of a single reference. Nevertheless, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ combinations and sub-combinations of these complementary embodiments and otherwise motivate experimentation and optimization. Freeman teaches the use of current thresholds to detect operating states, distinguishing between a normal load and a ”no load” or low-current state, defining the “ceiling” of the window (below normal load). Djenguerian provides the “minimum current draw”, defining the “floor” (above minimum to keep current alive), regulating power to ensure the system stays above a minimum operational value (bypass voltage/current) to keep the controller working. Therefore, setting the detection threshold between the normal operating current and the system’s baseline minimum draw (quiescent/magnetizing current) to improve and reliably distinguish a fault-induced drop from background noise or total disconnection. Djenguerian provides further support for secondary-side control circuits that manage power and regulate bypass voltages from multiples sources, providing the bypass path hardware (a parallel current control device connected to the secondary winding), describing a bypass voltage above a minimum operational value to ensure the control interfaces remain powered during different transitions, such as the remedial actions disclosed by Freeman, “shut-down of output” or “de-rating of output power) when thresholds (like over-temperature or over-current) are crossed. Doing so merely combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 15, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0202], [0207] & [0253]),
Freeman, in combination with Abdesselam, are silent in regard to:
wherein the first control interface is formed on a first semiconductor die and the second control interface is formed on a second semiconductor die.
However, Djenguerian, further teaches:
wherein the first control interface is formed on a first semiconductor die ([0031]-[0032]: discloses the primary controller (first control interface) formed on a first integrated circuit die) and the second control interface is formed on a second semiconductor die ([0031]-[0032]: discloses the secondary controller (second control interface) formed on a distinct second die to ensure they are “galvanically isolated from one another”).
It would have been obvious to one of ordinary skill in the art before the effective filing date, where Freeman discloses the foundational structure of using multiple semiconductor chips in a power architecture, Djenguerian teaches separating the primary and secondary controllers onto different dies to maintain galvanic isolation, therefore modifying the multi-chip system of Freeman, which already utilizes a first and second chip, by incorporating the dual-die configuration of Djenguerian, to achieve high-voltage galvanic isolation between the input (primary) and the output (secondary) sides and voltage handling capabilities required by a transformer-based design, while maintaining a compact form factor, combines prior art elements according to known methods to yield predictable results (KSR).
Regarding dependent claim 16, Freeman teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]), further comprising a transistor (Fig. 72; [0133], [0261] & [0289]: M2, “the secondary voltage reduction circuit 100 may include a diode and a MOSFET.”, transistor M2 is the MOSFET) that is coupled between the transformer (Fig. 72; [0133], [0261] & [0289]; T1 (is part of the forward converter 96 and transformer 102) and the second control interface (Figs. 2 & 72; [0098]-[0114], [0133], [0261] & [0289]: control circuitry responsible for driving the gate of transistor M2, not labeled as a single block, gate M2 is visibly connected to the control logic, which is part of the overall controller 106 (detailed in Fig. 2), further described in [0098]-[0114], specifically for the forward converter, ([0103], [0133]-[0134] & [0167]-[0173]), where transistor M2 is controlled by this interface), the transistor having a source that is coupled to a first end of the secondary winding, a drain that is coupled to a second end of the secondary winding (Fig. 72; [0133], [0261] & [0289]: describes transistors connected to terminals and transformer windings, “primary voltage reduction circuit 98 includes a transformer 102. The primary side of the transformer 102 is connected to the primary power circuit 26 and the secondary side of the transformer 102 is connected to the secondary voltage reduction circuit 100. …the secondary voltage reduction circuit 100 may include a diode and a MOSFET”, where a MOSFET is identified (M2 in Fig. 72) as being part of the secondary voltage reduction circuit 100, that is connected to the secondary side of the transformer 102, where Fig. 72 depicts one end of the secondary winding of transformer T1 (is part of transformer 102) is connected to a diode D21 and inductor L1, which connect to the drain of M2, the other end of the secondary winding of T1 is connected to ground, which is also connected to the source of M2, where in a rectifier configuration, the MOSFET’s source and drain terminals are coupled to the current path originating from the secondary winding to rectify and control current flow, with the end nodes labeled as Vp and Vcp, transistor M2, the source (S) of transistor M2 connected to node Vcp (one end of the secondary winding), and the drain (D) of transistor M2 connected to node Vp (the other end of the secondary winding), “synchronous rectifier FETs”, indicating a configuration where the transistors are integrated into the secondary rectification circuit, with the source and drain terminals connected to the secondary winding’s output to control current flow),
Freeman, is silent in regard to:
and a gate that is coupled to the second control interface, wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to reduce a resistance of a path between the source and the drain of the transistor.
However, Abdesselam, further teaches:
and a gate that is coupled to the second control interface ([0018]-[0019], [0021]-[0031] & [0053]-[0066]: teaches that the stop element is controlled, “driven by,” the secondary-side power and fault detection controller 21), wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor ([0018]-[0019], [0021]-[0031] & [0053]-[0066]: secondary controller detects the fault (error) and applies a voltage to the control terminal (gate) of the stop element to activate it (close the switch)) so as to reduce a resistance of a path between the source and the drain of the transistor (Fig. 1; [0018]-[0019], [0021]-[0031], [0037]-[0044] & [0053]-[0066]: teaches the key concept, the “stop element” (which is a transistor), when activated is used to create a short-circuit (low resistance path) between its source and drain across the winding, the reduced resistance allows an overcurrent to flow, which signals the error to the primary side, by changing a voltage that is applied at the gate of the transistor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the “stop element” transistor of Abdesselam into the system of Freeman, further incorporating a gate that is coupled to the second control interface, wherein the error is reported to the first control interface by changing a voltage that is applied at the gate of the transistor so as to reduce a resistance of a path between the source and the drain of the transistor, of Abdesselam to Freeman, in order to improve, by combining both prior art references, where Freeman supplies the means of achieving a short-circuit by applying a voltage to the gate of a transistor, and Abdesselam provides an overall system architecture and functional purpose of short-circuiting the secondary winding for fault reporting, teaching that a fault in the secondary circuit can be reported to the primary circuit by using a “stop element” (a transistor) to short-circuit the secondary winding of the pulse transformer, reducing the resistance between the source and drain is used to communicate an error/malfunction from the secondary side to the primary side, achieving the error reporting function without the need for additional complex components (i.e. optocouplers), and providing a robust fault-reporting mechanism, yielding predictable results (KSR).
Regarding dependent claim 17, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]), further comprising a power switch for controlling a switching cell of a switch-mode power supply (Figs. 50 & 72; [0108], [0124], [0133], [0261]: discloses a switch-mode power supply (e.g., Forward Converter or Flyback) comprising a power switch (synchronous rectifier) for controlling the switching cell (secondary side), M2 MOSFET, PFET SR 238 & NFET SR 238, M2 MOSFET within the secondary voltage reduction circuit 100 is a power switch, PFET and NFET are synchronous rectifier MOSFETs, acting as power switches in the forward converter (a switch-mode power supply), “the secondary voltage reduction circuit 100 may include a diode and a MOSFET”, the “secondary voltage reduction circuit” is part of the “forward converter circuit 96”, which is a switch-mode power supply, “synchronous rectifier FETs.”, where FETs (Field-Effect Transistors) are power switches and synchronous rectification is a technique used in switching cells of switch-mode power supplies for rectification, circuitry includes power switches, specifically MOSFETs, that act as synchronous rectifiers to control the power delivery cell on the secondary side, replacing diodes with MOSFETs for rectification is a well-known “switching cell” in SMPS design for higher efficiency),
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Freeman, in combination with Abdesselam, are silent in regard to:
wherein the power switch is coupled between the second control interface and the device, wherein the power switch is turned on and off by the second control interface based on a direction of the electrical current through the secondary winding.
However, Djenguerian, further teaches:
wherein the power switch is coupled between the second control interface and the device (Fig. 1; [0046]: discloses a power switch (synchronous rectification circuit 132) coupled between the second control interface (secondary controller 120) and the device (output 104 or load), the controller drives the switch via a control terminal, figure further illustrates secondary controller 120 coupled to synchronous rectification circuit 132 (switch) which is the path to output terminals 104 (device)), wherein the power switch is turned on and off by the second control interface based on a direction of the electrical current through the secondary winding (Fig. 1; [0041] & [0046]: teaches that the secondary controller turns the power switch (SR) on and off based on the state of the secondary winding, which dictates the direction of electrical current flow, i.e., conducting energy to the output).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the secondary-side controller and synchronous rectification logic of Djenguerian into the power system of Freeman to improve efficiency. Djenguerian provides a standard, high-efficiency implementation where a secondary controller manages, drives the power switch/the synchronous rectifier, based on the conduction state (current direction) of the secondary winding to minimize voltage drops and conduction losses. Freeman discloses a power switch controlling a switch-mode power supply, using a primary-side regulation circuit with a controller and a current sensor to generate a pulse-width modulated (PWM) signal to operate the switch. Additionally, doing so, merely combines prior art elements according to known methods, without the need for additional complex components, and yielding predictable results (KSR).
Regarding dependent claim 18, Freeman, teaches:
The system of claim 9 (Figs. 2 & 4; [Abstract], [0032], [0035], [0038], [0133]-[0134], [0163], 0177], [0181], [0191], [0202], [0207], [0253], [0261] & [0289]), wherein the first control interface includes (Fig. 66; [0038], [0103], [0106]-[0115], [0125], [0140]-[0144], & [0167]: Tronium PSSoC 106, “power module includes the advanced power supply system on a chip (TroniumTM PSSoC)…including a controller application specific integrated circuit (ASIC)”, the “TroniumTM PSSoC” serves as the central “first control interface”, additional components of “the Tronium PSSoC 106 includes the single-stage switch capacitor circuit 32, a PID regulator control block 11 for PWM control of the forward converter secondary transformer 102…a current and temperature sense blocks 116, 12-bit Analog-to-Digital Converter (ADC) 118 for voltage and current monitoring,… and a digital control block 122 for current monitoring state machine.”, these components collectively form parts of the processing circuitry in the first control interface):
one or more magnetic field sensing elements (Fig. 1 & 66; [0038], [0103], [0106]-[0115], [0125] & [0140]-[0144]: discloses the use of Hall Effect sensors (magnetic field sensing elements) in the sensing circuit) that are arranged to measure a magnetic field associated with a line that couples the first control interface to the primary winding of the transformer (Fig. 3; [0124]-[0125], [0167]: teaches using a magnetic field sensor voltage sensing circuit 62, “the sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field being generated within the transformer.”, the Hall Effect sensors are the “magnetic field sensing elements” and are arranged to measure a magnetic field associated with the primary side of the transformer, the sensors are part of the “regulator control circuit 58”, “the Hall Effect sensors facilitate determining a zero-crossing of the transformer by directly sensing the magnetic field being generated by the transformer during operation”); and
a processing circuitry that is arranged to detect the electrical current through the primary winding based on a signal generated, at least in part, by the one or more magnetic field sensing elements (Fig. 3; [0038], [0103], [0125], [0133]-[0134], [0143], & [0248]: voltage sensing circuit 62, linking the magnetic field sensing to current detection: “The Hall Effect sensor is connected to the PWM controller 60 for transmitting a signal to the PWM controller 60 for transmitting a signal to the PWM controller 60 for use in determining when the transformer nears the “zero-crossing”.”, further stating, “The sensing circuit 62 includes one or more Hall Effect sensors that are coupled to the primary side of the forward converter transformer for sensing a magnetic field generated within the transformer”, where the “PWM controller 60” acts as the “processing circuit”, “determining a time at which the transformer reaches the “zero-crossing” by sensing its magnetic field is a method of detecting current-related behavior (e.g., the point where current crosses zero through the primary winding, based on the signal generated by the Hall Effect sensors), “a current sense circuit configured to sense a current level on the primary side, and a controller configured to generate a pulse-width modulated control signal delivered to the switching device as a function of the sensed current level to regulate the transformer.”, supports the idea of a controller (processing circuit) deterring the primary side current, “The current sense amplifier in the Tronium PSSoC allows the device to measure current as part of the feedback loop as well as error reporting. The current can be measured by an ADC or through a series of comparators with varying thresholds.”, confirms the Tronium PSSoC (first control interface) includes processing circuitry capable of current measurement, also teaches the control circuit 103 includes processing circuitry (e.g., sample-and-hold circuits, comparators, ADCs, digital state machines) that is “arranged to detect the electrical current” based on a signal from a sensor (resistor 109), where the processing of a sensor signal is used to determine current for the purpose of regulation).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Vemuri et al. (US 2017/0033698 A1, Pub. Date Feb. 2, 2017, hereinafter Vemuri), in view of in view of Abdesselam, and further in view of Yang et al. (US 2022/0155383 A1, Pub. Date May 19, 2022, hereinafter Yang).
Regarding independent claim 29, Vemuri teaches:
A system (Figs.1 & 8; [Abstract] & [0014]-[0016]: 100, flyback converter system), comprising:
a power switch (Figs.1 & 8; [0016]-[0019]: “The flyback converter 100 includes a primary side or first switch S1, and a secondary side or second switch S2. The first switch S1 is operated by the first switching control signal SC1 from the first control circuit 114, and the second switch S2 is operated according to the second switching control signal SC2 from the second control circuit 130”, “N-channel field effect transistor (FET) switches S1 and S2”, and “The primary winding 108 includes a first end 106 to receive the input voltage signal VIN, and a second end 110 connected to the first terminal or drain (D) of the first switch S1. The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sensor resistor R1 that provides a current sense signal CS to the first control circuit 114.”, the second switch S2 is a power switch (e.g., a synchronous rectifier) connected to the secondary winding 122);
a transformer having a primary winding and a secondary winding (Fig. 1; [0014], [0017] & [0019]: discloses a transformer 104 with a primary winding 108 and a secondary winding 122), the primary winding and the secondary winding being arranged to power an external load via the power switch (Fig. 1; [0014]-[0019]: 104, 108, 118, & 122, “a flyback power converter or conversion system 100 including a controller integrated circuit (IC) 101 having a first control circuit (e.g., a primary side controller or PSC) 114 and a second control circuit (e.g., a secondary side controller or SSC) 130, as well as a transformer 104 with a primary winding 108 receiving input VIN and a secondary winding 122 providing output VO to a load 125 (“external load’) via the secondary switch S2 (power switch). The transformer 104 also includes an additional or auxiliary winding 118 on the primary side.” and also contains a first switch S1);
a controller (Figs. 1-3 & 8; [0014]-[0019] & [0023]-[0024]: “The first (primary side) control circuit 114 includes a driver circuit 116 with an output 117 to provide a first switching control signal SC1 under control of a first control logic circuit 120. The logic circuit 120 is coupled with the driver circuit 116, and includes an input 121 coupled with the auxiliary winding 118 through a resistor R2 to receive a signal VAUX representing a voltage of the auxiliary winding 118…The first control circuit 114 receives a predetermined cycle start request signal from the second control circuit 130 via the auxiliary winding 118 to initiate power transfer cycles for operation in a second mode to implement secondary side regulation (SSR) of the output voltage VO”, “the first control circuit 114 can operate according to a predetermined time period between successive power transfer cycles. This operation, in conjunction with operation of the second control circuit 130 in the case of synchronous rectifier implementations (or through operations of a separate secondary side rectifier diode)”, “the primary side control circuit 114, including the first control logic circuit 120. The first logic circuit 120 can include any suitable analog and/or digital circuitry, programmable or preconfirmed”, where the primary control circuit 114, containing control logic 120, serves as the controller for the first control interface, system includes a first control circuit 114 and a second control circuit 130, these can be in a single IC 101 or separate 101a/101b, collectively forming the controller);
a first control interface that is coupled between the controller and the primary winding (Figs.1 & 2; [0014]-[0019]: “The first (primary side) control circuit 114 includes a driver circuit 116 with an output 117 to provide a first switching control signal SC1 under control of a first control logic circuit 120. The logic circuit 120 is coupled with the driver circuit, and includes an input 121 coupled with the auxiliary winding 118 through a resistor R2 to receive a signal VAUX representing a voltage of the auxiliary winding 118.”, “The primary winding 108 includes a first end 106 to receive the input voltage signal VIN, and a second end 110 connected to the first terminal or drain (D) of the first switch S1. The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sense resistor R1 that provides a current sense signal CS to the first control circuit 114.”, primary side of control circuit 114 is part of the controller and is coupled to the primary winding 108 via switch S1, it monitors the primary side, including the current sense (CS) signal from resistor R1, which measures the electrical current through the primary winding via switch S1),
the first control interface being arranged to: (i) obtain a first measurement of an electrical current through the primary winding (Figs.1 & 2; [0014]-[0019]: “The first switch S1 includes a second or source terminal (S) coupled to GND1 through a current sense resistor R1 that provides a current sense signal CS to the first control circuit 114.”, “the first switch S1 is placed in an on state or condition to selectively allow a first switch current IS1 to flow between the first and second terminals (D,S) of the switch S1 when the first switching control signal SC1 is in a first state (e.g., HIGH for an N-channel FET S1). In this condition, current flows from the input source 102 into the first end 106, including the current IS1 flowing through the first switch S1, and current associated with a magnetizing inductance of the primary winding 108,” the first control circuit 114 obtains a current measurement via the current sense CS signal from resistor R1, which is proportional to the current IS1 through the primary switch S1 and the primary winding, this is considered the first measurement),
a second control interface that is coupled between the secondary winding and the power switch (Figs. 1 & 3; [0014] & [0017]-[0020]: discloses the secondary side control circuit 130 is part of the controller and is coupled between the secondary winding 122 and the secondary switch S2 (the power switch), “The transformer secondary winding 122 includes a first end 124 coupled to provide the output voltage signal VO to drive the load 125, and a second end 126 coupled with the second switch S2. The second switch includes a first terminal (e.g., drain D) coupled with the second end 126 of the secondary winding 122, and the second terminal (e.g., source S) coupled to GND2. The switch S2 also includes a second control terminal (e.g., gate G) coupled to receive the second switching control signal SC2 from the second control circuit 130”, where the second control circuit 130 is the second control interface), the second control interface being configured to: (i) provide an electrical current received from the transformer to the power switch (Fig.1; [0014] & [0017]-[0020], [0022] & [0028]-[0030]: the secondary controller 130 turns on switch S2 to allow the secondary current IS2 from the transformer to flow through the power switch S2 to the load, “the transformer secondary winding 122 includes a first end 124 coupled to provide the output voltage signal VO to drive the load 125, and a second end coupled with the second switch S2. The second switch S2 includes a first terminal (e.g., drain D) coupled with the second end 126 of the secondary winding 122, and a second terminal (e.g., source S) coupled GND2. The switch S2 also includes a second control terminal (e.g., gate G) coupled to receive the second switching control signal SC2 from the second control circuit 130”, “The second switch S2 operates in an on state or condition to allow a second switch current IS2 to flow between its source and drain terminals D and S (e.g., between the second end 126 of the secondary winding 122 and GND2) when the second switching control signal SC2 is in a first state (e.g., HIGH for an N-channel FET S2)…the output current IO flows between the first end 124 of the secondary winding 122 and the output load 125.”),
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Vemuri, is silent in regard to:
(ii) detect whether an error is present in operational conditions of the power switch, and (iii) in response to detecting the error, report the error to the first control interface by decreasing a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer.
However, Abdesselam, further teaches:
(ii) detect whether an error is present in operational conditions of the power switch (Fig. 1; [0017]-[0019], [0022], [0031], [0041]-[0044] & [0052]-[0065]: teaches the “power and fault detection controller” 21 includes a “power transistor operation detector 24” able to “detect an operating fault of the power transistor” to detect at least one parameter of the “power transistor causing non-nominal operation of the power transistor”, which is a direct teaching of detecting an error in the power switch’s operational conditions), and (iii) in response to detecting the error (Fig. 1; [0017]-[0019], [0022], [0031], [0038], [0041]-[0044], [0052] & [0059]-[0062]), report the error to the first control interface by decreasing a level of an electrical current through the secondary winding (Fig. 1; [0017]-[0019], [0022], [0031], [0038], [0041]-[0044], [0052]-[0057], [0059]-[0066] & [Claim 8]: discloses the secondary circuit 20 includes a “power and fault detection controller” 21 that (i) is connected to the power transistor (load equivalent), (ii) detects malfunctions of the secondary circuit or power transistor, and (iii) “comprises a stop element able to short-circuit the pulse transformer on the basis of a fault detection”, where the action of short-circuiting the secondary winding changes the current in the secondary winding, which “when a short circuit occurs in the secondary circuit 20, an overcurrent then forms in the primary circuit 10, …this overcurrent is detected directly by the short-circuit detector 18”, which in turn “causes the primary winding current to cross a threshold”, communicating the fault to the primary side) so as to cause the electrical current through the primary winding to drop to a value that is less than the threshold and greater than a minimum current draw of the transformer (Fig. 1; [0017]-[0019], [0022], [0031], [0038], [0041]-[0044], [0052]-[0057], [0059]-[0066] & [Claim 8]: teaches detecting “opening faults” (current drop) on the primary winding, therefore modifying the second controller to “open” or “increase impedance” (decreasing current) instead of “shoring” (increasing current) to signal a fault is a variation, as the primary detector 18 is equipped to detect both states (open/short)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate in a second control interface (ii) detect whether an error is present in operational conditions of the power switch, and (iii) in response to detecting the error, change a level of an electrical current through the secondary winding so as to cause the electrical current through the primary winding to cross the threshold, of Abdesselam to Vemuri, in order to improve, by combining prior art references, where Vemuri discloses a system comprising a power switch, a transformer with primary and secondary windings for power a load, a controller, a first control interface, and a second control interface, the second control interface provides a current to the power switch and can communicate with the first interface by manipulating current in the secondary winding, Abdesselam teaches a bidirectional isolated controller designed for high-reliability applications, where a secondary circuit detects a fault (e.g., via a power transistor operation detector) and reports it to the primary circuit by short-circuiting the secondary winding, causing an over-current condition on the primary side that is detected by a short-circuit detector, would be the motivation to implement the fault reporting from a secondary side to a primary side in an isolated power system, modifying the system of Vemuri with the teachings of Abdesselam, would improve the reliability and fault tolerance, meeting the safety standards and providing cross-validation of sensor data, of Vemuri’s flyback converter, by adding a fault detection circuit to Vemuri’s secondary controller to monitor the power switch, programming Vemuri’s secondary controller, upon detecting a fault, to activate switch S2 to create a current pulse or short-circuit condition to signal the fault, then using the second current measurement in the primary circuit and the logic to compare them for agreement, yielding predictable results (KSR).
Vemuri, in combination with Abdesselam, are silent in regard to:
(ii) obtain a second measurement of the electrical current through the primary winding, (iii) detect whether the first and second measurements are in agreement with each other, (iv) output a first fault signal to the controller when the first and second measurements are not in agreement with each other, and (v) output a second fault signal to the controller when the first measurement and the second measurement are in agreement with each other, but at least one of the first and second measurements has crossed a threshold; and
However, Yang, further teaches:
(ii) obtain a second measurement of the electrical current through the primary winding ([0004], [0015], [0025], [0032], [0044]-[0047] & [0126]: teaches using two sensors (140/142) to obtain multiple measurements of current flow to ensure accuracy and distinguish faults), (iii) detect whether the first and second measurements are in agreement with each other ([0032]-[0033], [0040], [0043]-[0044] & [0049]-[0052]: teaches comparing two signals, if they diverge (disagreement), it indicates a specific type of fault or sensor error), (iv) output a first fault signal to the controller when the first and second measurements are not in agreement with each other ([0032]-[0033], [0043]-[0044], [0065]-[0069] & [0072]: if sensors disagree (e.g., one reads fault, one does not), the system identifies the sensor fault or location of the system fault, generating an internal fault determination (signal)), and (v) output a second fault signal to the controller when the first measurement and the second measurement are in agreement with each other, but at least one of the first and second measurements has crossed a threshold ([0032]-[0033], [0040], [0043]-[0044] & [0049]-[0052]: teaches declaring a system fault (second fault signal) when both sensors agree (both show high derivative/current crossing a threshold)); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the flyback converter system of Vemuri by incorporating the dual-sensor fault detection of Yang and the transformer-coupled fault reporting of Abdesselam. Abdesselam further teaches a secondary power and fault detection controller 21 that detects specific errors in the power switch and reports them to the primary side via the pulse transformer by manipulating the secondary winding load (e.g., shorting/impedance change), therefore, modifying/substitute the secondary control interface to decrease the current (via an open circuit or high impedance state) to report the error would be the motivation for the following reasons. Design choice, where selecting between an active high fault signal (increasing current/short circuit) and an active low fault signal (decreasing current/open circuit) is a recognized logical equivalent in circuit design, the choice based on the desired fail-safe characteristics. A POSITA would be motivated to use a “decreasing level” (current drop) because it allows for a fail-safe operation, where if the secondary controller loses power or the connection breaks, the current will naturally drop. By defining the fault signal as a drop in current (below a threshold but a minimum “keep-alive” or magnetizing current), the primary controller can detect both active errors and passive system failures (e.g., broken wires) using the same logic. Abdesselam discloses that primary detector 18 is capable of detecting an “opening fault” which corresponds to a current drop/zero current, in addition to short circuits, therefore the primary sensing hardware is capable of detecting the current drop as well. Vemuri teaches that the primary controller detects “interruption of the ringing waveform”, which constitutes a decrease or cessation of the expected oscillatory current/voltage, and further supports detecting a drop in signal activity and a design choice. Therefore, substituting Abdesselam’s “shorting” (current increase) method with a “damping” or “opening” (current decrease) method is a simple substitution of one known element for another to obtain predictable results (KSR), communicating a fault via a different signal state.
Claims 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over Ahmed et al. (US 2024/0283352 A1, Filed Date Jun. 16, 2023, hereinafter Ahmed) in view of Freeman, and further in view of Abdesselam.
Regarding independent claim 30, Ahmed teaches:
A system (Fig. 1; [0003], [0012] & [0014]: discloses a flyback converter system comprising a primary side and a secondary side), comprising:
a transformer having a primary winding and a secondary winding (Fig. 1; [0012], [0014] & [0039]-[0040]: discloses the flyback transformer 130 that includes a primary-side winding and a secondary-side winding, “A flyback transformer 130” acts as a magnetically coupled structure, this transformer has a “primary-side winding” and a “secondary-side winding”, the windings correspond to the “first element” and “second element” respectively, flyback transformer 130 separates the primary side 110 and the secondary side 120);
a first control interface that is coupled to the primary winding (Fig. 1; [0012], [0039]-[0040], & [0042]), the first control interface being arranged to (Figs. 1, 2A, 2B; [0012]-[0013], [0039]-[0040], [0042], [0044] & [0046]: teaches the primary side 110 includes a primary-side controller 116, this controller interfaces with the primary winding via the switch 118, which is interpreted as the first control interface, “the primary-side controller 116” (a “controller”) is coupled to the “primary-side winding” (the “first element”) of the flyback transformer 130, the primary-side controller 116 controls operation of the switch, which in turn controls the primary element, the “first control interface” can be largely embodied by the primary-side controller 116 and associated circuitry):
a second control interface that is coupled to the secondary winding, the second control interface being configured to (Figs. 1, 2A, & 2B; [0012], [0015]-[0017], [0024], [0039]-[0040] & [0043]: discloses the secondary side 120 includes a secondary-side controller 126, this controller is coupled to the secondary winding 122 and is the second control interface, a “secondary-side controller 126” (a “second control interface”) that is coupled to the “secondary-side winding” (the ”second element”) of the flyback transformer 130, the secondary-side controller 126 is configured to “communicate control signals to the primary-side controller” (which controls the “power switch”) via a “signal transformer 140”): (i) provide an electrical current received from the transformer to an external load (Fig. 1; [0012]-[0014] & [0042]: discloses the secondary side provides the output voltage VO to drive a load 125 via connector 122, the current from the secondary winding 122 flows through diode 128 or a synchronous rectifier to the load, when the primary-side power switch is in the off-state, the “secondary current to flow from the flyback transformer” (i.e., received from the magnetically coupled structure’s secondary winding or transformer) and this “secondary current is used to charge the at least one secondary-side capacitor and deliver power to the load connected to the connector”, the secondary-side control interface enables current flow to the load by sending signals to the primary side, indirectly affecting the primary power switch operation in relation to energy transfer), (ii) detect whether an error is present (Figs. 2B & 5; [0022], [0032], [0046], [0054], [0064], [0078], [0084], [0086]-[0087] & [0094]: discloses the secondary-side controller 126 can store and monitor for faults such as “over-voltage (OV), under-voltage (UV), or over-current (OC), short-circuit detection, over-temperature (OT)”, a direct reaching of error detection on the secondary side, where 521 (including OCP module), states that the secondary-side controller 126 can “achieve circuit protection based on analysis of current and voltage conditions and the detection of faults”, further lists “OCP (over current protection), SCP (short circuit protection)” as fault conditions that the secondary side can detect and manage, demonstrating the capability to detect the presence of an error, “On detection of fault conditions, a control signal may be sent to disconnect connector 420 from the flyback transformer 130…This disconnection may be caused by an over-voltage conditions, an over-current condition, or other conditions…”, indicates the secondary side detects errors, “USB-PD modules 521 may include…an over-voltage protection (OVP) module and an over-current protection (OCP) module for providing over-current and over-voltage protection on the VBUS_IN line…”, these modules are part of the IC system 500, which includes the secondary-side controller functionality), and
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Ahmed, is silent in regard to:
(i) measure an electrical current through the primary winding, (ii) detect whether the measured electrical current falls into any given one of a plurality of threshold ranges that are outside of a normal operating range of the transformer, (iii) when the measured electrical current falls into any given one of the plurality of threshold ranges, identify an error type that corresponds to the given threshold range, and (iv) output a fault signal that is indicative of the error type; and
wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range.
However, Freeman, further teaches:
(i) measure an electrical current through the primary winding (Figs. 71-72; [Abstract], [0133]-[0134], [0163], [0191] & [0248]: “The control circuit 103 uses a current sense resistor 109 and measures across the primary winding…The control circuit 103 is configured to sense the load current on a pulse by pulse basis and sense the peak current. For example in one embodiment, the control circuit 103 senses the voltage across the resistor 109…”, teaches measuring primary current),
(ii) detect whether the measured electrical current falls into any given one of a plurality of threshold ranges that are outside of a normal operating range of the transformer (Fig. 24; [0160], [0163], [0167], [0187], [0191] & [0202]: discloses “The following mutually exclusive conditions, the thresholds for which are programmable, can occur: 1. Over-current condition…2. Under-load condition…”, “The digital word is then compared against programmed thresholds to enable or disable the Buck Regulator 34 as needed to optimize efficiency. The output of the Current Sense Amplifier is also monitored for possible fault or alarm conditions such as over current…”, the thresholds define ranges (e.g., normal vs. fault vs. sleep)),
(iii) when the measured electrical current falls into any given one of the plurality of threshold ranges, identify an error type that corresponds to the given threshold range (Fig. 24; [0160], [0163], [0167] & [0202]-[0204]: discloses “1. Over-current condition: The system sets the over-current status bit…2. Under-load condition…” identifies specific conditions (error/state types) are identified based on the sensed current crossing different thresholds/ranges), and
(iv) output a fault signal that is indicative of the error type (Fig. 80; [0163], [0202], [0228] & [0253]: shows transitions to an “ERROR” state based on various conditions, which is an outputted status, “1. Over-current condition: The system sets the over-current status bit.”, setting a status bit is a form of outputting a fault signal indictive of the error type, the I2C interface can also be used to output this status, the controller takes action (outputs a signal/command) based on the identified type, “allowing a digital state machine that controls the current sense feedback to disable the SCVBC 32 to prevent possible damage”); and
wherein causing the level of the electrical current through the primary winding to fall into a threshold range that corresponds to the respective type of the error includes causing the level of the electrical current through the primary winding to fall into a first one of the plurality of threshold ranges when the error is from a first type and causing the level of the electrical current through the primary winding to fall into a second one of the plurality of threshold ranges when the error is from a second type, the second range being different from the first range (Figs. 78-80; [0325]-[0330], [0339], [0355], [0430], [0440] & [Claim 6]: discloses a “window comparator” logic that divides the primary current into multiple distinct ranges (windows 1, 2, 3, etc.), using this for gain control/feedback, and also links the sensing to alarms and error states).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate in a first control interface (i) measure an electrical current through the primary winding, (ii) detect whether the measured electrical current falls into any given one of a plurality of threshold ranges that are outside of a normal operating range of the transformer, (iii) when the measured electrical current falls into any given one of the plurality of threshold ranges, identify an error type that corresponds to the given threshold range, and (iv) output a fault signal that is indicative of the error type, of Freeman to Ahmed, in order to improve, by combining prior art references, where Ahmed discloses a system comprising a transformer with primary and secondary windings, a first and second control interface, where the second control interface provides current to an external load, managing power delivery and detects parameters and errors, communicates with the first control interface via a signal transformer by changing currents in the winding of the transformer. Freeman teaches a system with a power supply system with a transformer, primary-side error detection (measurement) based on current, threshold-based error detection, fault signaling and a communication interface from the secondary controller, and refines the threshold range by teaching a primary-side controller that uses a “window comparator” to detect if the primary current falls into specific “value windows” (ranges), which is used for state/fault monitoring. Modifying and combining the system of Ahmed with the teachings of Freeman, would improve the reliability and fault tolerance, taking Freeman’s multi-window detection with Abdesselam’s signaling method to report specific error types via specific current ranges. Doing so merely combines prior art elements according to known methods without any additional complex components, yielding predictable results (KSR).
Ahmed, and Freeman, are silent in regard to:
and (iii) when an error is present, report the error to the first control interface by changing a level of an electrical current through the secondary winding causing the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error,
However, Abdesselam, further teaches:
and (iii) when an error is present, report the error to the first control interface by changing a level of an electrical current through the secondary winding causing the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error (Fig. 1; [Abstract], [0018]-[0019], [0022]-[0031], [0042]-[0044], [0053]-[0064], [Claim 1], [Claim 2], [Claim 6] & [Claim 11]: teaches a method of fault communication, where “the stop element 26 may short-circuit the secondary winding 34 of the pulse transformer. … when a short circuit occurs in the secondary circuit 20, discloses the secondary circuit 20 includes a “power and fault detection controller” 21 that is connected to the power transistor (load equivalent), where the action of short-circuiting the secondary winding changes the current in the secondary winding, which “when a short circuit occurs in the secondary circuit 20, an overcurrent then forms in the primary circuit 10. And…this overcurrent is detected directly by the short-circuit detector 18”, which in turn “causes the primary winding current to fall into a threshold range that corresponds to a respective type of error”, communicating the fault to the primary side, this is a direct teaching of reporting an error by manipulating the current in the secondary winding to cause a specific, detectable over-current condition (i.e., causing the primary current to fall into a specific threshold range) on the primary side),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate in a second control interface (iii) when an error is present, report the error to the first control interface by changing a level of an electrical current through the secondary winding causing the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error, of Abdesselam to Ahmed and Freeman, in order to improve, by combining prior art references, where Ahmed discloses a system comprising a transformer with primary and secondary windings, a first and second control interface, where the second control interface provides current to an external load and detects errors, communicates with the first control interface via a signal transformer by changing currents in the winding of the transformer, Freeman teaches a system with a power supply system with a transformer, primary-side error detection (measurement) based on current, threshold-based error detection (provides the detection logic), Abdesselam, teaches and discloses a controller where the secondary side, upon detecting an error, short-circuits the secondary winding of the transformer (provides the mechanism of interaction), causing an overcurrent in the primary winding, which is detected by the primary-side controller’s existing overcurrent threshold detection circuit, linking it to different underlying faults (e.g., power transistor fault vs. control device fault), creating different types of loads to pull the primary current to different, specific threshold ranges and communicating the error type. Utilizing Freeman’s “window” (range) detection logic to interpret the fault signals generated by Abdesselam’s secondary controller, instead of a single “short” (one type of error), the secondary controller would be configured to modulate the current to different distinct levels (corresponding to Freeman’s windows) to indicate error types (error 1 type vs error type 2), and incorporating the fault-reporting method of Abdesselam would be a simple means of communicating a fault to the primary side, making the overall system safer and more reliable without any additional components, arriving at the claimed invention by substituting fault-handling mechanisms for another, with a more robust and efficient system, yielding predictable results (KSR).
Regarding dependent claim 31, Ahmed, teaches:
The system of claim 30 (Fig. 1; [0003], [0012] & [0014]), wherein changing a level of an electrical current through the secondary winding ([0027]-[0028]: discloses a secondary-side controller that modulates current through a signal transformer (secondary winding) using a programmable current DAC)
includes identifying a configuration setting for a current control device that corresponds to the respective type of the error ([0027]-[0028]: discloses a DAC controller (identifying) that determines a setting (digital parameter/configuration) for the “programmable current DAC” (current control device))
and applying the configuration setting to a current control device that is associated with the secondary winding (Figs. 1, 2A, & 2B; [Abstract], [0012], [0016], [0027]-[0028], [0039]-[0040], [0043], [0050] & [0103]: the secondary-side controller 126 applies configuration settings to its components, “A DAC controller of the secondary-side controller can control operation of the programmable DAC (e.g., current DAC) based on a set of parameters.”, “In some embodiments, the programmable DAC is controlled based on a set of parameters…secondary-side controller 126 can further include a DAC controller that can control operation of the programmable DAC based on the set of parameters…In some embodiments, the DAC controller configures the programmable DAC in accordance with the set of parameters”, shows the secondary controller is identifying and applying settings and further discloses the secondary side 120 includes a secondary-side controller 126, this controller is coupled to the secondary winding 122 and is the second control interface, a “secondary-side controller 126” (a “second control interface”) that is coupled to the “secondary-side winding” (the ”second element”) of the flyback transformer 130, the secondary-side controller 126 is configured to “communicate control signals to the primary-side controller” (which controls the “power switch”) via a “signal transformer 140”, thus generating the control signal).
Ahmed, in combination with Freeman, are silent in regard to:
so as to cause the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error
However, Abdesselam, further teaches:
so as to cause the electrical current through the primary winding to fall into a threshold range that corresponds to a respective type of the error (Fig. 1; [0037]-[0066]: teaches a system where the secondary-side fault can be communicated to the primary side via the transformer coupling, and this communication is detected as an overcurrent in the primary circuit, also mentions that the primary side can identify the “origin of the malfunction” by detecting different types of faults, describes a control module that generates a control current based on a pulsed wave, and this control current can have “positive pulses” or “negative pulses”, which corresponds to an activation or stop command, the secondary-side controller then uses an induced current to drive a power transistor, shows a mechanism for the secondary side to change the primary-side current for communication)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate and utilize the high-resolution current DAC of Ahmed to generate distinct current levels (as taught by Abdesselam’s fault communication) that correspond to specific error types, which are then categorized by the primary side using Freeman’s multi-threshold detection logic. Ahmed provides the core structure of a secondary-side controller with a current control device (programmable current DAC) capable of generating specific current levels based on configuration settings (digital bits). Abdesselam provides the motivation to use the transformer coupling to communicate specific fault/malfunction types from the secondary side to the primary side. Freeman teaches the use of varying thresholds and comparators on the primary side to detect specific states or faults on the sensed current levels. Ahmed used the DAC primarily for control signals, Abdesselam teaches the modification of the secondary system to detect faults, where the motivation would be to communicate specific error types (e.g., Over-voltage vs. Over-Temperature) rather than a generic fault, and Freeman, provides the mechanism for the threshold range detection on the primary side. Making it further obvious to modify Ahmed’s system to utilize its existing current DAC to generate specific current values upon the detection of specific errors, as taught by Abdesselam, the primary side would then employ Freeman’s varying thresholds to categorize the sensed current into ranges, identifying the respective error corresponding to the DAC’s configuration setting. Doing so, merely combines the prior art references according to known methods to improve the signaling mechanism of Abdesselam with the advanced control capabilities of Ahmed and Freeman, creating a more sophisticated system , combining the secondary-side’s programmable DAC from Ahmed with the principle of overcurrent signaling from Abdesselam, creating a design that uses different DAC settings (or a DAC with higher resolution) to create different levels of current in the secondary winding, where the different levels would cause different, pre-defined overcurrents in the primary winding, which could then be interpreted by a primary-side controller to identify different error types, the primary-side controller of Ahmed already has the capability to monitor against a plurality of thresholds, or “windows,” for this type of multi-level reporting scheme, yielding predictable results (KSR), with a more robust and efficient system.
Regarding dependent claim 32, Ahmed teaches:
The system of claim 31 (Fig. 1; [0003] & [0012]-[0014]), wherein the current control device includes a transistor (Fig. 1; [0003] & [0012]-[0014]: describes a flyback converter system where the primary side includes a power switch that controls the current (current control device), the switch is identified as a transistor (FET)),
Ahmed, is silent in regard to:
and the configuration setting includes a gate voltage for the transistor.
However, Freeman, further teaches:
and the configuration setting includes a gate voltage for the transistor ([0027]-[0028], [0131] & [0156]: teaches configuring the driver to provide a specific gate voltage (configuration setting) to the transistor to ensure it functions correctly (e.g., setting it 5-20V higher than the source)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the specific gate voltage configurations and driver teachings of Freeman to the FET disclosed in Ahmed to ensure the power switch operates efficiently and fully turns on/off, particularly in high-voltage applications. Ahmed discloses the current control device (primary-side controller and power switch arrangement) that includes a transistor (FET) used to control current in the flyback converter and a gate driver for the transistor. Freeman teaches the configuration setting regarding the gate voltage, detailing specific requirements for driving the transistors (e.g., 5-20V above rail) and the configuration of drives (charge pumps/level shifters) to generate and set the specific gate voltage for operation, and otherwise motivating experimentation and optimization. Doing so, merely combines prior art elements according to known methods to yield predictable results (KSR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Gritti (US9954445B2 & US10284096B2) disclose a current converter with current control on the primary winding side and compensation of the propagation delay. Bieber et al. (US2023/0318469A1) discloses a driver circuit for regulating an output voltage across a load. Rai (US10862399B1) discloses a primary controller calibration and trimming using secondary controller in secondary-controlled flyback converters. Li et al (US2006/0221528A1) discloses systems and methods for providing over-current protection in a switching power supply. Chobot (US2011/0234255A1) discloses fault detection circuits for switched mode power supplies and related methods of operation. Clauberg (US2023/0369957A1) discloses a system and method for determining mains voltage of a power supply.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 02/12/2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 2/19/2026