Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination
The present application is being examined as a continuation application of 17146564 (now US Pat. # 11737273). Now pending in this application are claims 1-20.
Specification
The specification submitted 6/23/2023 has been accepted by the examiner.
Drawings
The drawings submitted on 6/23/2023 have been accepted by the examiner.
Information Disclosure Statements
The information disclosure statements (IDS) submitted recently have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-15 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jung (US # 20190333931).
Regarding Claim 11, Jung (US # 20190333931) teaches a three-dimensional (3D) semiconductor memory device comprising:
a horizontal structure (SC) on an upper surface (top, as shown in Fig. 3) of a horizontal semiconductor layer (100);
a stack structure (ST) comprising a plurality of electrodes (EGE, CGE, SGE) stacked on the horizontal structure in a vertical direction (D3); and
a separation structure (SS and CPLG structure more generally) intersecting the stack structure and the horizontal structure (it extends through features ST and SC),
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wherein a lower portion of the separation structure is in a recess region (RS, see lowest portion of GIR, in Fig. 21C, portion of GIR below the level of the lowest ILD) of the horizontal semiconductor layer,
wherein an upper portion (portion of GIR above the level of SC) of the separation structure penetrates the stack structure in the vertical direction (shown), and
wherein, a bottom surface of the recess region is inclined with respect to a top surface of the horizontal semiconductor layer (see RS inclination in Fig. 21C).
Regarding Claim 12, Jung teaches the 3D semiconductor memory device of claim 11, wherein the lower portion of the separation structure protrudes more in a horizontal direction than the upper portion (shown wider in in Fig. 21C).
Regarding Claim 13, Jung teaches the 3D semiconductor memory device of claim 11, further comprising:
a vertical pattern (VS) extending through the plurality of electrodes and connected to the horizontal structure,
wherein, in a horizontal direction, a minimum distance between the lower portion of the separation structure and the vertical pattern is less than a distance between the upper portion of the separation structure and the vertical pattern at a level where a bottom surface of a lowermost electrode of the plurality of electrodes is positioned (lower portion is wider, thus it has a lesser horizontal distance).
Regarding Claim 14, Jung teaches the 3D semiconductor memory device of claim 11, wherein a lowermost electrode (EGE) of the plurality of electrodes comprises inner sidewalls that face each other and are spaced apart from each other in a horizontal direction with the separation structure interposed therebetween, and
wherein a maximum width of the recess region in the horizontal direction is greater than a distance between the inner sidewalls of the lowermost electrode at a level where a bottom surface of the lowermost electrode is positioned (that is shown in Fig. 21C).
Regarding Claim 15, Jung teaches the 3D semiconductor memory device of claim 11, wherein the lower portion of the separation structure is overlapped in the vertical direction by a lowermost electrode of the plurality of electrodes (shown in Fig. 21C, or see also Fig. 4E).
Claims 16-20 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jung # 2 (US # 20190244970).
Regarding Claim 16, Jung # 2 (US # 20190244970) teaches a three-dimensional (3D) semiconductor memory device (see Fig. 6 and corresponding text) comprising:
a horizontal structure (SCP1/SCP2) on an upper surface (top) of a horizontal semiconductor layer (10);
a stack structure (ST) comprising a plurality of electrodes (EGE, GGE, SGE) stacked on the horizontal structure in a vertical direction (normal to substrate surface); and
a separation structure (SS) intersecting the stack structure and the horizontal structure (it extends through features ST and SC),
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wherein a lower portion (portion lower than layer ILDa) of the separation structure is in a recess region (opening GIR is shown in Fig. 25C with bottom surface RS) of the horizontal semiconductor layer (shown in layer 10),
wherein an upper portion (portion higher than layer ILDa) of the separation structure penetrates the stack structure in the vertical direction (shown), and
wherein the horizontal semiconductor layer has a protrusion (see annotated drawing with protrusion point 1) that protrudes toward the horizontal structure in the recess region (this protrusion has a central line in it that points into the SCP1 layer).
Regarding Claim 17, Jung # 2 teaches the 3D semiconductor memory device of claim 16, wherein the lower portion of the separation structure protrudes more in a horizontal direction than the upper portion (shown wider in in Fig. 25C).
Regarding Claim 18, Jung # 2 teaches the 3D semiconductor memory device of claim 16, further comprising:
a vertical pattern (VS) extending through the plurality of electrodes and connected to the horizontal structure (shown),
wherein, in a horizontal direction, a minimum distance between the lower portion of the separation structure and the vertical pattern is less than a distance between the upper portion of the separation structure and the vertical pattern at a level where a bottom surface of a lowermost electrode of the plurality of electrodes is positioned (lower portion is wider, thus it has a lesser horizontal distance).
Regarding Claim 19, Jung # 2 teaches the 3D semiconductor memory device of claim 16, wherein a lowermost electrode (LSL2) of the plurality of electrodes comprises inner sidewalls that face each other and are spaced apart from each other in a horizontal direction with the separation structure interposed therebetween, and
wherein a maximum width of the recess region in the horizontal direction is greater than a distance between the inner sidewalls of the lowermost electrode at a level where a bottom surface of the lowermost electrode is positioned (that is shown in Fig. 25C).
Regarding Claim 20, Jung # 2 teaches the 3D semiconductor memory device of claim 16, wherein the lower portion of the separation structure is overlapped in the vertical direction by a lowermost electrode of the plurality of electrodes (that is shown in Fig. 25C).
Allowable Subject Matter
Claims 1-10 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, although the prior art shows substantial features of the claimed invention, the prior art reviewed by the examiner neither teaches nor reasonably suggests all the claimed limitations, including wherein, when viewed in cross section, the recess region has a polygonal shape and an asymmetrical shape with respect to a vertical line extending in the vertical direction.
Pending claims 2-10 are dependent on the claim above and are allowable at least based on that dependency.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899