DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on June 23, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claim 15 is objected to because of the following informality:
In claim 15, lines 6-7 “the metallization stack comprising the first portion of the device layer” should read --the metallization stack comprising a first portion of the first portion of the device layer-- (emphasis added). Support can be found at least in the context of the feature in lines 4-8 of the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 7, 8, 12, 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uchida US 2024/0079347.
Regarding claim 1, Uchida teaches an integrated circuit (IC) device (e.g., Fig. 3B, the description thereof; also see Fig. 1, Fig. 2 and the description thereof for additional details), comprising:
a substrate (e.g., 306 and/or 308, Fig. 3B) comprising a plurality of areas (e.g., 210, Fig. 3B) and one or more scribe lines (e.g., 208, Fig. 3B; Fig. 1) defining boundaries of individual areas of the plurality of areas, wherein the plurality of areas includes a first area (e.g., 210 at the left side with respect to 208, Fig. 3B) and a second area (e.g., 210 at the right side with respect to 208, Fig. 3B) adjacent to the first area, and wherein the one or more scribe lines include a scribe line (e.g., 208, Fig. 3B) between the first area and the second area;
a first device layer (e.g., first device layer including bottommost 322 at the left side with respect to 208, Fig. 3B) over the first area of the substrate;
a first metallization stack (e.g., first metallization stack including 336 at the left side with respect to 208, Fig. 3B) over the first device layer;
a second device layer over (e.g., second device layer including bottommost 322 at the right side with respect to 208, Fig. 3B) the second area of the substrate;
a second metallization stack (e.g., second metallization stack including 336 at the right side with respect to 208, Fig. 3B) over the second device layer; and
a conductive line (e.g., 318, Fig. 3B, [22]) extending between the first metallization stack and the second metallization stack, wherein a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line (e.g., Fig. 3, Fig. 2; [26]; [17]).
Regarding claim 2, Uchida teaches the IC device according to claim 1, wherein: a portion of the conductive line (e.g., portion of 318 in the first metallization stack (discussed above), Fig. 3B) in the first metallization stack is in a first metal layer (e.g., corresponding first metal layer of the first metallization stack (discussed above), Fig. 3B) of the first metallization stack, the conductive line is a first conductive line, and the first metallization stack further includes a second conductive line (e.g., portion of 320, Fig. 3B, [22]) in a second metal layer (e.g., corresponding second metal layer of the first metallization stack (discussed above), Fig. 3B) of the first metallization stack, wherein the second metal layer is either closer to the substrate than the first metal layer or further away from the substrate than the first metal layer (e.g., Fig. 3B).
Regarding claim 4, Uchida teaches the IC device according to claim 2, wherein: the first metallization stack further includes a third conductive line (e.g., 330 (in 312) of the first metallization stack (discussed above), Fig. 3B) in a third metal layer of the first metallization stack, wherein the first metal layer is between the second metal layer and the third metal layer (e.g., Fig. 3B).
Regarding claim 5, Uchida teaches the IC device according to claim 4, wherein: a portion of the conductive line (e.g., portion of 318 in the second metallization stack (discussed above), Fig. 3B) in the second metallization stack is in a first metal layer (e.g., corresponding first metal layer of the second metallization stack (discussed above), Fig. 3B) of the second metallization stack, and the second metallization stack further includes a fourth conductive line (e.g., portion of 320, Fig. 3B, [22]) in a second metal layer (e.g., corresponding second metal layer of the second metallization stack (discussed above), Fig. 3B) of the second metallization stack, wherein the second metal layer of the second metallization stack is either closer to the substrate than the first metal layer of the second metallization stack or further away from the substrate than the first metal layer of the second metallization stack (e.g., Fig. 3B).
Regarding claim 7, Uchida teaches the IC device according to claim 5, wherein: the second metallization stack further includes a fifth conductive line (e.g., 330 (in 312) of the second metallization stack (discussed above), Fig. 3B) in a third metal layer of the second metallization stack, wherein the first metal layer of the second metallization stack is between the second metal layer of the second metallization stack and the third metal layer of the second metallization stack (e.g., Fig. 3B).
Regarding claim 12, Uchida teaches the IC device according to claim 1, wherein the conductive line is substantially parallel to the substrate (e.g., Fig. 3B).
Regarding claim 19, Uchida teaches an integrated circuit (IC) package (e.g., Fig. 1, the description thereof), comprising:
an IC device (e.g., Fig. 3B, the description thereof; also see Fig. 1, Fig. 2 and the description thereof for additional details); and
a further component (e.g., 102, Fig. 1, Fig. 2), coupled to the IC device,
wherein the IC device includes:
a substrate (e.g., 306 and/or 308, Fig. 3B) comprising a first area (e.g., 210 at the left side with respect to 208, Fig. 3B), a second area (e.g., 210 at the right side with respect to 208, Fig. 3B), and a scribe line (e.g., 208, Fig. 3B) between the first area and the second area,
a first device layer (e.g., first device layer including bottommost 322 at the left side with respect to 208, Fig. 3B) over the first area of the substrate, and
a first metallization stack (e.g., first metallization stack including 336 at the left side with respect to 208, Fig. 3B) over the first device layer,
a second device layer (e.g., second device layer including bottommost 322 at the right side with respect to 208, Fig. 3B) over the second area of the substrate, and
a second metallization stack (e.g., second metallization stack including 336 at the right side with respect to 208, Fig. 3B) over the second device layer, and
a conductive line (e.g., 318, Fig. 3B, [22]) extending between the first metallization stack and the second metallization stack, wherein a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line (e.g., Fig. 3, Fig. 2; [26]; [17]).
Regarding claim 20, Uchida teaches. the IC package according to claim 19, wherein the further component is one of a package substrate, an interposer, or an IC die (e.g., 102, Fig. 1, Fig. 2, [13]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11 and 13-15 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Uchida US 2024/0079347.
Regarding claim 9, Uchida teaches the IC device according to claim 1 as discussed above.
Uchida does not explicitly teach wherein a critical dimension of the conductive line is less than about 100 nanometers.
Uchida, however, recognizes that the conductive layer 318 functions as a barrier film to prevent diffusion of conductive material such as copper (Cu) (e.g., [22]). In other words, a dimension of the conductive layer may be a result effective variable for varying the degree of barrier ability. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to control and optimize the device of Uchida to have the claimed range through routine experimentation and optimization. MPEP 2144.05. Also, Applicant has not disclosed that the claimed range is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical.
Regarding claim 10, Uchida teaches the IC device according to claim 9, wherein the critical dimension is a width of the conductive line (e.g., the discussion with respect to claim 9 above similarly applies).
Regarding claim 11, Uchida teaches the IC device according to claim 1, wherein a length of the conductive line is at least about 600 micron (e.g., the discussion with respect to claim 9 above similarly applies).
Regarding claim 13, Uchida teaches the IC device according to claim 1 as discussed above.
Uchida does not explicitly teach wherein a width of the scribe line is between about 50 micron and 200 micron.
Uchida, however, recognizes that the scribe line 208 may have a width in a micrometer scale (e.g., [17]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the device of Uchida to have the claimed range, since it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 14, Uchida teaches the IC device according to claim 1 as discussed above.
Uchida does not explicitly teach wherein a length of the scribe line is at least about 1 millimeter.
Uchida, however, recognizes that the substrate 306 may have various dimensions, such as 200 mm, 300 mm, 450 mm or other diameter wafers, as well as, rectangular or square panels (e.g., [21]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the device of Uchida to have the claimed range, since it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Regarding claim 15, Uchida teaches an integrated circuit (IC) device (e.g., Fig. 3B and the description thereof; also see Fig. 1, Fig. 2 and the description thereof for additional details), comprising:
a support (e.g., 306 and/or 308, Fig. 3B) comprising a first area (e.g., 210 at the left side with respect to 208, Fig. 3B), a second area (e.g., 210 at the right side with respect to 208, Fig. 3B), and a division line (e.g., 208, Fig. 3B) between the first area and the second area;
a device layer over the support, the device layer comprising a first portion (e.g., first portion of the device layer including bottommost 322 at the left side with respect to 208, Fig. 3B) over the first area, a second portion (e.g., second portion of the device layer including bottommost 322 at the right side with respect to 208, Fig. 3B) over the second area, and a third portion (e.g., third portion of the device layer between the first and second portions of the device layer (discussed above), Fig. 3B) over the division line;
a metallization stack over the device layer, the metallization stack comprising a first portion (e.g., first portion of the metallization stack including 336 at the left side with respect to 208, Fig. 3B; see the claim objection above) over the first portion of the device layer, a second portion (e.g., second portion of the metallization stack including 336 at the right side with respect to 208, Fig. 3B) over the second portion of the device layer, and a third portion (e.g., third portion of the metallization stack between the first and second portions of the metallization stack (discussed above), Fig. 3B) over the third portion of the device layer;
a conductive line (e.g., 318, Fig. 3B, [22]) having a first portion (e.g., portion of 318 in the first portion of the metallization stack (discussed above), Fig. 3B) in the first portion of the metallization stack, a second portion (e.g., portion of 318 in the second portion of the metallization stack (discussed above), Fig. 3B) in the second portion of the metallization stack, and a third portion (e.g., portion of 318 in the third portion of the metallization stack (discussed above), Fig. 3B) in the third portion of the metallization stack, wherein the first, second, and third portions of the conductive line are materially and electrically continuous portions of the conductive line (e.g., Fig. 3B, [22]).
Uchida does not explicitly teach wherein a width of the division line is between about 50 micron and 200 micron.
Uchida, however, recognizes that the scribe line 208 may have a width in a micrometer scale (e.g., [17]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to control and optimize the device of Uchida to have the claimed range, since it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Allowable Subject Matter
Claims 3, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if amended to overcome the claim objection to the base claim above.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Sharma et al. US 2023/0207565 relates to an integrated circuit (IC) device including a conductive line extending between the first metallization stack and the second metallization stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 September 5, 2026
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