DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/23/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restriction
It has been acknowledged that the applicant has elected without traverse Invention (Group I) by cancelling claims 18-20 (Group II) per the response dated on 11/21/2025. Currently claims 1-17 are present for examination.
Claim Objections
Claim 13 is objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
In claim 13, the limitation that “two adjacent source/drains have a space less than one contacted gate pitch between the two adjacent source/drains” is not clear. Specifically, “a space” can be interpreted in multiple ways, such as “a width”, “a distance” or “a void between”. For examining purpose, “a space” is considered to be “a space between the two adjacent source/drains”, by interpreting the disclosure (paragraph [0038]). For proper interpretation of claim 12, “a space” should be changed to “a space between the two adjacent source/drains”.
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation “the source/drain resides on the bottom dielectric isolation layer”. There is insufficient antecedent basis for this limitation in the claim, because “the bottom isolation layer” has not been introduced before in claim 14 or in claim 1 on which claim 14 depends. For examining purpose, “ the dielectric isolation layer” is considered to be “a dielectric isolation layer”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1-2 and 7-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shin (US 2024/0274679 A1).
Regarding claim 1, Shin teaches a semiconductor structure (integrated circuit device 100, Figs. 1 and 2A-B, [0021]) comprising:
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two adjacent semiconductor devices (see semiconductor device 1 and semiconductor device 2 in Illustrative Fig. 1, which is an annotated version of Fig. 2A: each nanosheet stack NSS with the associated gate structure 160, drain region 130D and source regions 130S corresponds to a semiconductor device, [0026] and [0032]) of a plurality of semiconductor devices (comprising nanosheet stacks NSS with the associated gate structure 160, drain region 130D and source regions 130S, Figs. 1 and 2A-B);
two adjacent source/drains (source region 1 and source region 2, Illustrative Fig. 1: adjacent source regions of semiconductor devices) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1); and
a backside contact (see backside contact as shown in Illustrative Fig. 1: backside contact comprises lower insulating liner 194, lower via contact 196, and the upper portion of lower power rail BPW, Illustrative Fig. 1, [0060]) connects the two adjacent source/drains (source region 1 and source region 2, Illustrative Fig. 1) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to a backside power rail (backside power rail, Illustrative Fig. 1).
Regarding claim 2, Shin teaches the semiconductor structure of claim 1, wherein the backside contact (backside contact, Illustrative Fig. 1) has a larger bottom contact area (the interface between backside contact and backside power rail shown as bottom surface in Illustrative Fig. 1) with the backside power rail (backside power rail, Illustrative Fig. 1) than a combined area (the interfaces of lower via contacts 196 with source region 1 and source region 2 shown as first top surface and second top surface in Illustrative Fig. 1) of two top surfaces of the backside contact (first top surface and second top surface) connecting to the two adjacent source/drains (source region 1 and source region 2, Illustrative Fig. 1).
Regarding claim 7, Shin teaches the semiconductor structure of claim 6, wherein the backside contact (backside contact, Illustrative Fig. 1) connects two adjacent source/drains (source region 1 and source region 2, Illustrative Fig. 1) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to the backside power rail (backside power rail, Illustrative Fig. 1), providing a current (a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the backside contact carries current between the backside power rail and semiconductor devices) from the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to the backside power rail (backside power rail, Illustrative Fig. 1), and wherein each of the two top surfaces (first top surface and second top surface, Illustrative Fig. 1) of the backside contact (backside contact, Illustrative Fig. 1) connect to a source/drain of the two adjacent source/drains (first source region and second source region, Illustrative Fig. 1).
Regarding claim 8, Shin teaches the semiconductor structure of claim 1, wherein the backside contact (backside contact, Illustrative Fig. 1) includes a portion of a semiconductor material (fin-type active structures F1, Illustrative Fig. 1, [0022]: “The plurality of in-type active structures Fl may include a semiconductor”) below and between the two adjacent source/drains (first source region and second source region, Illustrative Fig. 1).
Examiner notes that Shin teaches claims 1-2, 7-8 (see 35 U.S.C. 102 rejection above), but does not specifically cover claim 3, 6, and 13 as claims these claims include structural limitations that is not covered by Shin. Rejection are being made over Guler (US 2024/0321737 A1) for claims 1, 3, 6, and 13 as to cover claims 1-3, 6-8, and 13 in total.
Claims 1, 3, 6, and 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guler (US 2024/0321737 A1).
Regarding claim 1, Guler teaches a semiconductor structure (integrated circuit structure, Figs. 14A-B, [0017]) comprising:
two adjacent semiconductor devices (see semiconductor device 1 and semiconductor device 2, each comprising a nanoribbon stack 702, in Illustrative Fig. 2, which is an annotated version of Figs. 14A-B, [0058]) of a plurality of semiconductor devices (individual semiconductor devices, each comprising a nanoribbon stack 702, Illustrative Fig. 2);
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two adjacent source/drains (two of the source and drain regions 602 shown as source/drain 1 and source/drain 2 in Illustrative Fig. 2, [0057]) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 2); and
a backside contact (comprising backside contacts 1302 and conductive trace 1404a, shown as backside contact in Illustrative Fig. 2, [0069]) connects the two adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 2) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 2) to a backside power rail (while not shown in any of the figures, “the backside contacts may be formed to facilitate connection with backside power rails and/or other backside signal layers.” ([0022]).
Regarding claim 3, Guler teaches the semiconductor structure of claim 1, wherein the two adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 2) are electrically separated by a single diffusion barrier (dielectric wall 1002, Illustrative Fig. 2, [0062]).
Regarding claim 6, Guler teaches the semiconductor structure of claim 1, wherein the backside contact (backside contact, Illustrative Fig. 2) has an M-shape (the top and side surfaces of the backside contact have an M-like shape) in a cross-sectional view (the cross-section shown in Fig. 14B), and wherein the backside contact (backside contact, Illustrative Fig. 2) has two top surfaces (see top surface 1 and top surface 2 in Illustrative Fig. 2).
Regarding claim 13, Guler teaches the semiconductor structure of claim 1, wherein the two adjacent source/drains (source/drain 1 and source/drain 2, Illustrative Fig. 2) have a space (the distance between source/drain 1 and source/drain 2 corresponding the width of dielectric wall 1002, Illustrative Fig. 2) less than one contacted gate pitch between the two adjacent source/drains (center-to-center distance between the semiconductor device 1 and semiconductor device 2, Illustrative Fig. 2).
Claim 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park (US 2024/0321689 A1).
Regarding claim 15, Park teaches a semiconductor structure (semiconductor device 20, Fig. 3, [0066]) comprising:
two adjacent semiconductor devices (see semiconductor device 1 and semiconductor device 2 in Illustrative Fig. 3, which is an annotated version of Fig. 3: each device comprises an active device layer 240 ([0067]) and associated gate structure GST ([0048]) and source/drain pattern SD [0044]);
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a source/drain (source/drain, Illustrative Fig. 3) connecting to the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 3); and
a backside contact (second portion PV-2 of the power via PV labeled as backside contact in Illustrative Fig. 3, [0067]) connects the source/drain (source/drain, Illustrative Fig. 3) to a backside power rail (power rail PR labeled as power rail in Illustrative Fig. 3, [0067]), wherein a bottom surface (bottom surface, Illustrative Fig. 3) of the backside contact (backside contact, Illustrative Fig. 3) is larger than a top surface (bottom surface, Illustrative Fig. 3) of the backside contact (backside contact, Illustrative Fig. 3).
Regarding claim 16, Park teaches the semiconductor structure of claim 15, wherein the bottom surface (bottom surface, Illustrative Fig. 3: extended y the top surface of the power rail) of the backside contact (backside contact, Illustrative Fig. 3) has a width (width W1, Illustrative Fig. 3) of approximately one contacted gate pitch (gate pitch, Illustrative Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2024/0274679 A1) as applied to claims 1-2 and 7-8 above.
Regarding claim 4, Shin teaches the semiconductor structure of claim 1, wherein the backside contact (backside contact, Illustrative Fig. 1) has a slope of sidewalls (sidewall, Illustrative Fig. 1: the sidewalls have slopes) of the backside contact (backside contact, Illustrative Fig. 1).
Shin, however, is silent on the angle of the slope and therefore does not teach that the slope is between 40 and 80 degrees.
However, sidewalls of the backside contact of Shin have a slope which means that the slope of the sidewall is smaller than 90 degrees. Therefore, the range implied by Shin covers the range of slope angles provided by the current application, and it would have been obvious to select slope angle so that the slope to be within the quoted range of between 40 and 80 degrees, to optimize the device performance, such as electrical characteristics that can be affected by the resistance of the backside contact. In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed slope or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen slope or upon another variable recited in a claim, the Applicant must show that the chosen roughness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990). Therefore, the range of values provided does not hold an inventive subject matter.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shin (US 2024/0274679 A1) as applied to claims 1-2 and 7-8 above, and further in views of Lee (US 2024/0203882 A1) and Kim (US 2024/0258204 A1).
Regarding claim 14, Shin teaches the semiconductor structure of claim 1, further comprises:
a middle-of-line contact (upper via contacts VA, Fig. 2A, [0049]) connects to a source/drain (the rightmost source/drain structure 130, Fig. 2A) of one or more semiconductor devices (semiconductor device comprising the rightmost nanosheet stack NSS, Fig. 2A) of the plurality of semiconductor devices (semiconductor devices, each comprising a nanosheet stack NSS, Fig. 2A), wherein the source/drain (the rightmost source/drain structure 130, Fig. 2A) resides on the bottom dielectric isolation layer (bottom dielectric isolation BDI, Fig. 2A, [0057]).
Shin, however, does not teach that
the middle-of-line contact connects the source/drain of one or more semiconductor devices of the plurality of semiconductor devices to a back-end-of-line interconnect wiring layer;
a carrier wafer contacts the back-end-of-line interconnect wiring; and
a backside power delivery network is directly under the backside power rail.
Lee, on the other hand, teaches a semiconductor structure (semiconductor device structure 200, Fig. 2, [0056]), wherein
a middle-of-line contact (contact vias 207, Fig. 2, [0061]) connects the source/drain (first source-drain 216a, Fig. 2, [0059]) of one or more semiconductor devices (leftmost semiconductor device 201, Fig. 2, [0056]) of the plurality of semiconductor devices (semiconductor devices 201, Fig. 2) to a back-end-of-line interconnect wiring layer (back-end-of-line (BEOL) layers 206, Fig. 2, [0061]);
a carrier wafer (carrier wafer 215, Fig. 2, [0064]) contacts the back-end-of-line interconnect wiring (back-end-of-line (BEOL) layers 206, Fig. 2: carrier wafer 215 contacts the back-end-of-line (BEOL) layers 206 via the bonding oxide 205).
Lee further discloses that Lee’s device design improves power rail effectiveness and
prevent IR drop ([0004]). Therefore, a person of ordinary skill in the art before the effective filing date f the claimed invention would be motivated to include a back-end-of-line interconnect wiring layer connecting to a source/drain via a middle-of-line contact and a carrier wafer contacting the back-end-of-line interconnect wiring in the semiconductor structure of Shin, as taught by Lee, to improve the power rail effectiveness and prevent IR drop.
Neither Shin nor Lee, however, teaches
a backside power delivery network is directly under the backside power rail.
Kim, on the other hand, teaches a semiconductor device (semiconductor device 100, Figs. 1 and 5A-C, [0020]) wherein
a backside power delivery network (back side power delivery network
(BSPDN), [0051]: “The backside power structure 180 may form a BSPDN”, Fig. 5B) is directly under the backside power rail (power distribution line 182, Fig. 5B, [0070]).
Kim further discloses that semiconductor devices having a back side power delivery network (BSPDN) structure in which a power rail is disposed on a backside of a wafer increases the degree of device integration ([0003]) and improved device reliability ([0004]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a backside power delivery network directly under the backside power rail in the semiconductor structure of Shin in view of Lee, as taught by Kim, to facilitate integration of semiconductor devices and improve device performance.
Thus, the combination of Shin, Lee, and Kim meets all the limitations of claim 14.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 2024/0321689 A1) as applied to claims 1, 3, 6, and 13 above.
Regarding claim 17, while Park teaches the semiconductor structure of claim 15, wherein the backside contact (backside contact, Illustrative Fig. 2) has a slope of a sidewall (sidewall, Illustrative Fig. 2) of the backside contact (backside contact, Illustrative Fig. 2)
Park is silent on the angle of the slope and therefore does not teach that the slope is between 40 and 80 degrees (while the sloped sidewall implies that the slope of the sidewall is smaller than 90 degrees).
However, Park discloses that the thickness T1 of the first portion PV-1 is from about 10 nm to about 100 nm ([0036]), and the first width W1 of the first portion PV-1 is from about 10 nm to about 100 nm ([0036]). Because the width of the top surface of the first portion is larger than the width of the source/drain pattern SD by less than 50% (see Fig. 1), and the bottom surface of the first portion is about two times the width of the source/drain pattern SD, the slope can be estimated by trigonometry to be from about 22 degrees (100 nm width) to about 76 degrees (10 nm width) for the thickness of 10 nm, and about from 76 degrees (100 nm width) to about 88 degrees (10 nm width) for the thickness of 100 nm). Therefore, the slope according to Park’s disclosure is between about 22 degrees to about 88 degrees, which includes the ranges provided by the current application, and a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the slope of the sidewall can be optimized by routine experimentation to achieve desired electrical characteristics of the device (such as resistance of the contact and contact resistance associated device performance) while maintaining the structural constraints and integrity, and ease of manufacturing of the device(see MPEP 2144.05(II)). In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed slope range or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen slope or upon another variable recited in a claim, the Applicant must show that the chosen slope is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990). Therefore, the range of values provided does not hold an inventive subject matter.
Allowable Subject Matter
Claims 5 and 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7, disclosing that “the backside contact has a bottom contact area width of approximately two contacted gate pitches”, would be allowable if the width of the bottom contact area to be two contacted gate pitches is disclosed in an independent form or incorporated in claim 1.
Claim 9, disclosing that “the portion of the semiconductor material below and between the two adjacent source/drains contacts a bottom dielectric isolation layer under a single diffusion break”, would be allowable if this limitation is disclosed in an independent form or incorporated in a claim combining claims 1 and 8.
Claim 10, disclosing that “the two adjacent source/drains contact a plurality of inner spacers around a single diffusion break, and wherein the single diffusion break is between the two adjacent source/drains.”, would be allowable if this limitation is disclosed in an independent form or incorporated in claim 1.
Claim 11, disclosing that “a distance between each gate of the two adjacent semiconductor devices and the single diffusion break is less than the distance between each gate of the plurality of semiconductor devices adjacent to the two adjacent semiconductor devices.”, would be allowable if this limitation is disclosed in an independent form or incorporated in a claim combining claims 1 and 10.
Claim 12, disclosing that “the portion of the semiconductor material has an upside-down, cone shape”, would be allowable if this limitation is disclosed in an independent form or incorporated in a claim combining claims 1 and 8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Guler (US 2023/0275124 A1) teaches backside contact connecting source/drain regions of adjacent semiconductor devices, which is relevant to all claims.
Liaw (US 2023/0378190 A1) teaches backside connections for source/drain regions of adjacent semiconductor devices separated by diffusion barriers, which is relevant to all claims.
Liaw (US 2024/0055433 A1) teaches backside connections for source/drain regions of adjacent semiconductor devices separated by diffusion barriers, which is relevant to all claims.
Ju (US 2021/0351303 A1) teaches a backside contact for source/drain structures in a semiconductor device, which is relevant to claims 15-17.
Chu (US 2021/0399099 A1) teaches an epitaxial backside contact for a semiconductor device, which is relevant to claims 15-17.
Chang (US 2024/0064953 A1) teaches a backside contact for source/drain structures in a semiconductor device, which is relevant to claims 15-17.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812