DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The present amendment, filed on or after 3/25/2026, has been entered. The Applicant has amended claims 1, 3, 5, 7-11, and 13-17, and canceled claim 2. Claims 18-20 were previously canceled by the Applicant due to restriction requirement. Accordingly, claims 1 and 3-17 remain pending in the application.
Applicant’s amendment to the claim 13 failed to overcome the claim objection previously set forth in the Non-Final Office Action mailed on 1/28/ 2026, due to reasons stated below in Claim Objections.
Applicant' s amendment to claim 15 has also overcome the 25. U.S.C. 112(b) rejections made on claim 15 in the Non-Final Office Action mailed on 1/28/2026.
Claim Objections
Claim 13 is objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
In claim 13, the limitation that “a distance of a space between two immediately adjacent source/drains” is not clear. For examining purpose, “a distance of a space between two immediately adjacent source/drains” is considered to be “a width of a space between the two immediately adjacent source/drains”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites a limitation regarding “the plurality of semiconductor devices” on line 3. There is insufficient antecedent basis for this limitation in the claim, because “the plurality of semiconductor devices” has not been introduced in claim 11 or claims 1 and 10 on which claim 11 depends. For examining purpose, “the plurality of semiconductor devices” is considered to be “a plurality of semiconductor devices”.
Claim 14 recites a limitation regarding “the plurality of semiconductor devices” on line 4. There is insufficient antecedent basis for this limitation in the claim, because “the plurality of semiconductor devices” has not been introduced in claim 11 or claims 1 and 10 on which claim 11 depends. For examining purpose, “the plurality of semiconductor devices” is considered to be “a plurality of semiconductor devices”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 6-7, 10-11, 13, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 2024/0321737 A1) in view of Chang (US 2021/0343578 A1).
Regarding claim 1, Guler teaches a semiconductor structure (integrated circuit structure, Figs. 14A-B, [0017]) comprising:
two adjacent semiconductor devices (see semiconductor device 1 and semiconductor device 2, each comprising a nanoribbon stack 702, in Illustrative Fig. 1, which is an annotated version of Figs. 14A-B, [0058]);
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two immediately adjacent source/drains (two of the source and drain regions 602 shown as source/drain 1 and source/drain 2 in Illustrative Fig. 1, [0057]) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1); and
a backside contact (comprising backside contacts 1302 and conductive trace 1404a, shown as backside contact in Illustrative Fig. 1, [0069]) connects the two immediately adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 1) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to a backside power rail (while not shown in any of the figures, “the backside contacts may be formed to facilitate connection with backside power rails and/or other backside signal layers.” ([0022]).
Guler, however, does not teach that
the backside contact has a larger bottom contact area with the backside power rail than a combined area of two top surfaces of the backside contact connecting to the two immediately adjacent source/drains.
Chang, on the other, hand teaches a semiconductor structure (integrated circuit structure 100’, Fig. 33, [0078]) with backside contacts (backside vias 432, Fig. 33, [0095]) connecting the source/drains (source epitaxial structure 190S, Fig. 33, [0092[) to a backside power rail (backside power rail 305, Fig. 33, [0097]). Chang further teaches that that the bottom contact area of the backside contacts (backside vias 432, Fig. 33) to the backside power rail (backside power rail 305, Fig. 33) should be maximized to reduce the contact resistance at the interface, which reduces the RC time delay (Fig. 33, [0097]).
Therefore, the contact area is a result-effective variable that affects the device response at high frequencies and also at high power levels (see MPEP 2144.05). Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to operate the semiconductor structure of Guler at high frequencies or power levels would be motivated to make the bottom contact area as large as possible, which would lead to a bottom contact area to be larger than the combined areas of the two top surfaces of the backside contact (see dashed lines in Illustrative Fig. 1 showing how the backside contact can be extended to maximize the contact area in the semiconductor structure of Guler).
Regarding claim 3, Guler in view of Chang teaches the semiconductor structure of claim 1, wherein
Guler further teaches that the two adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 1) are electrically separated by a single diffusion barrier (dielectric wall 1002, Illustrative Fig. 1, [0062]).
Regarding claim 4, while Guler in view of Chang teaches the semiconductor structure of claim 1,
Guler does not teach that the backside contact has a slope of sidewalls of the backside contact that is between 40 and 80 degrees.
Chang, on the other, hand teaches a semiconductor structure (integrated circuit structure 100’, Fig. 33, [0078]) with backside contacts (backside vias 432, Fig. 33, [0095]) connecting the source/drains (source epitaxial structure 190S, Fig. 33, [0092[) to a backside power rail (backside power rail 305, Fig. 33, [0097]). Chang discloses that that the bottom contact area of the backside contacts (backside vias 432, Fig. 33) to the backside power rail (backside power rail 305, Fig. 33) should be increased to reduce the contact resistance at the interface, which reduces RC time delay (Fig. 33, [0097]). Chang further teaches that the bottom contact areas of the backside contact (backside vias 432, Fig. 33) can be increased by including a tapered portion (second portion 4322, Fig. 33, [0096]) over the portion (first portion 4321, Fig. 33, [0096]) contacting to a source/drain (source epitaxial structure 190S, Fig. 33, [0096]), and a wide portion (third portion 4323, FI. 33, [0096]) contacting the tapered portion (second portion 4322, Fig. 33). Chang further discloses that contacting the wide portion to the backside power rail (backside power rail 305, Fig. 33, [0097]) at the level 403h (Fig.33, [0097]) leads to an increased contact area with the backside power rail.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a tapered portion and a wide portion in the backside contact by forming the tapered portion and the wide portion on the bottom of the backside contact (bottom contact, Illustrative Fig. 1) of the semiconductor structure of Guler in view of Chang to increase the bottom contact area, as taught by Chang, which provides the benefit of reducing the contact resistance between the backside contact and the backside power rail, and therefore the RC time constant of the device. Thus, the combination of Guler and Chang leads to a semiconductor structure wherein the backside contact has a slope of sidewalls of the backside contact.
Guler and Chang, however, are silent on that the slope is between 40 degrees and 80 degrees.
However, sidewalls of the backside contact of Guler in view of Chang have a slope (tapered sidewalls) which means that the slope of the sidewall is smaller than 90 degrees. Therefore, the range implied by Guler in view of Chang covers the range of slope angles provided by the current application, and it would have been obvious to select slope angle so that the slope to be within the quoted range of between 40 and 80 degrees, to optimize the device performance (such as electrical characteristics that can be affected by the resistance of the backside contact) and manufacturing process (slopes with smaller angles might be more difficult to manufacture). In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed slope or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen slope or upon another variable recited in a claim, the Applicant must show that the chosen roughness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990). Therefore, the range of values provided does not hold an inventive subject matter.
Regarding claim 6, Guler in view of Chang teaches the semiconductor structure of claim 1, wherein
Guler further teaches that the backside contact (backside contact, Illustrative Fig. 1) has an M-shape (the top and side surfaces of the backside contact have an M-like shape) in a cross-sectional view (the cross-section shown in Fig. 14B), and wherein the backside contact (backside contact, Illustrative Fig. 1) has two top surfaces (see top surface 1 and top surface 2 in Illustrative Fig. 1).
Regarding claim 7, Guler in Chang teaches the semiconductor structure of claim 6, wherein
Guler further teaches that the backside contact (backside contact, Illustrative Fig. 1) connects the two immediately adjacent source/drains (source region 1 and source region 2, Illustrative Fig. 1) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to the backside power rail (backside power rail, Illustrative Fig. 1), providing a current (a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the backside contact carries current between the backside power rail and semiconductor devices) from the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) to the backside power rail (while not shown in any of the figures, “the backside contacts may be formed to facilitate connection with backside power rails and/or other backside signal layers.” ([0022]), and therefore, the backside contact contacts to a power rail), and wherein each of the two top surfaces (first top surface and second top surface, Illustrative Fig. 1) of the backside contact (backside contact, Illustrative Fig. 1) connect to a source/drain (source/drain 1 or source drain 2, Illustrative Fig. 1) of the two immediately adjacent source/drains (source/drain 1 and source drain 2, Illustrative Fig. 1).
Regarding claim 10, Guler in view of Chang teaches the semiconductor structure of claim 1, wherein
Guler further teaches that the two immediately adjacent source/drains (source/drain 1 and source/drain 2, Illustrative Fig. 1) contact a plurality of inner spacers (inner spacers, Illustrative Fig. 1) around a single diffusion break (dielectric wall 1002, Illustrative Fig. 1, [0062]), and wherein the single diffusion break (dielectric wall 1002, Illustrative Fig. 1) is between the two immediately adjacent source/drains (source/drain 1 and source/drain 2, Illustrative Fig. 1).
Regarding claim 11, Guler in view of Chang teaches the semiconductor structure of claim 10, wherein
Guler further teaches that a distance between each gate (gate electrode 804 of semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1, [0062]) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1) and the single diffusion break (dielectric wall 1002, Illustrative Fig. 1) is less than the distance between each gate (gate electrode 804 neighboring the semiconductor devices 1 and 2, Illustrative Fig. 1) of the plurality of semiconductor devices (semiconductor devices neighboring the semiconductor devices 1 and 2, Illustrative Fig. 1) adjacent to the two immediately adjacent semiconductor devices (semiconductor devices 1 and 2, Illustrative Fig. 1: because the diffusion break is between two gates, the distance between the gates is larger than the distance between the gate and the diffusion break).
Regarding claim 13, Guler in view of Chang teaches the semiconductor structure of claim 1, wherein
Guler further teaches that a distance of a space between two immediately adjacent source/drains (corresponding the width of dielectric wall 1002 between source/drain 1 and source/drain 2, Illustrative Fig. 1) less than one contacted gate pitch (center-to-center distance between gate electrodes 804, Illustrative Fig. 1) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 1).
Regarding claim 15, Guler teaches an electronic device (integrated circuit, Figs. 14A-B, [0017]) comprising:
a semiconductor structure (integrated circuit structure, Figs. 14A-B, [0017]) comprising:
two adjacent semiconductor devices (see semiconductor device 1 and semiconductor device 2, each comprising a nanoribbon stack 702, in Illustrative Fig. 2, which is an annotated version of Figs. 14A-B, [0058]);
two immediately adjacent source/drains (two of the source and drain regions 602 shown as source/drain 1 and source/drain 2 in Illustrative Fig. 2, [0057]) of two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 2); and
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a backside contact (comprising backside contacts 1302 and conductive trace 1404a, shown as backside contact in Illustrative Fig. 2, [0069]) connects the two immediately adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 2) of the two adjacent semiconductor devices (semiconductor device 1 and semiconductor device 2, Illustrative Fig. 2) to a backside power rail (while not shown in any of the figures, “the backside contacts may be formed to facilitate connection with backside power rails and/or other backside signal layers.” ([0022]).
Guler, however, does not teach that
the backside contact has a larger bottom contact area with the backside power rail than a combined area of two top surfaces of the backside contact connecting to the two immediately adjacent source/drains.
Chang, on the other, hand teaches a semiconductor structure (integrated circuit structure 100’, Fig. 33, [0078]) with backside contacts (backside vias 432, Fig. 33, [0095]) connecting the source/drains (source epitaxial structure 190S, Fig. 33, [0092[) to a backside power rail (backside power rail 305, Fig. 33, [0097]). Chang further teaches that that the bottom contact area of the backside contacts (backside vias 432, Fig. 33) to the backside power rail (backside power rail 305, Fig. 33) should be maximized to reduce the contact resistance at the interface, which reduces the RC time delay (Fig. 33, [0097]).
Therefore, the contact area is a result-effective variable that affects the device response at high frequencies and also at high power levels (see MPEP 2144.05). Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention who is aiming to operate the electronic device of Guler at high frequencies or power levels would be motivated to make the bottom contact area as large as possible, which would lead to a bottom contact area to be larger than the combined areas of the two top surfaces of the backside contact (see dashed lines in Illustrative Fig. 2 showing how the backside contact can be extended to maximize the contact area in the electronic device of Guler).
Regarding claim 16, Guler in view of Chang teaches the electronic device of claim 15, wherein
Guler further teaches that the two immediately adjacent source/drains (source/drain 1 and source/drain 2 in Illustrative Fig. 2) are electrically separated by a single diffusion barrier (dielectric wall 1002, Illustrative Fig. 2, [0062]: “Dielectric walls 1002 further extend along the first direction between adjacent source or drain regions 602 within the source/drain trench.”).
Regarding claim 17, while Guler in view of Chang teaches the semiconductor structure of claim 15,
Guler does not teach that the backside contact has a slope of sidewalls of the backside contact that is between 40 and 80 degrees.
Chang, on the other, hand teaches a semiconductor structure (integrated circuit structure 100’, Fig. 33, [0078]) with backside contacts (backside vias 432, Fig. 33, [0095]) connecting the source/drains (source epitaxial structure 190S, Fig. 33, [0092[) to a backside power rail (backside power rail 305, Fig. 33, [0097]). Chang discloses that that the bottom contact area of the backside contacts (backside vias 432, Fig. 33) to the backside power rail (backside power rail 305, Fig. 33) should be increased to reduce the contact resistance at the interface, which reduces RC time delay (Fig. 33, [0097]). Chang further teaches that the bottom contact areas of the backside contact (backside vias 432, Fig. 33) can be increased by including a tapered portion (second portion 4322, Fig. 33, [0096]) over the portion (first portion 4321, Fig. 33, [0096]) contacting to a source/drain (source epitaxial structure 190S, Fig. 33, [0096]), and a wide portion (third portion 4323, FI. 33, [0096]) contacting the tapered portion (second portion 4322, Fig. 33). Chang further discloses that contacting the wide portion to the backside power rail (backside power rail 305, Fig. 33, [0097]) at the level 403h (Fig.33, [0097]) leads to an increased contact area with the backside power rail.
Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a tapered portion and a wide portion in the backside contact by forming the tapered portion and the wide portion on the bottom of the backside contact (bottom contact, Illustrative Fig. 1) of the electronic device of Guler in view of Chang to increase the bottom contact area, as taught by Chang, which provides the benefit of reducing the contact resistance between the backside contact and the backside power rail, and therefore the RC time constant of the device. Thus, the combination of Guler and Chang leads to an electronic device wherein the backside contact has a slope of a sidewall of the backside contact.
Guler and Chang, however, are silent on that the slope is between 40 degrees and 80 degrees.
However, the sidewall of the backside contact of Guler in view of Chang has a slope (tapered sidewall) which means that the slope of the sidewall is smaller than 90 degrees. Therefore, the range implied by Guler in view of Chang covers the range of slope angles provided by the current application, and it would have been obvious to select slope angle so that the slope to be within the quoted range of between 40 and 80 degrees, to optimize the device performance (such as electrical characteristics that can be affected by the resistance of the backside contact) and manufacturing process (slopes with smaller angles might be more difficult to manufacture). In addition, to an ordinary artisan practicing the invention, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d 454, 105 USPQ 233, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed slope or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen slope or upon another variable recited in a claim, the Applicant must show that the chosen roughness is critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990). Therefore, the range of values provided does not hold an inventive subject matter.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Guler (US 2024/0321737 A1) in view of Chang (US 2021/0343578 A1) as applied to claims 1, 3-4, 6-7, 10-11, 13, and 15-17 above, and further in views of Lee (US 2024/0203882 A1) and Kim (US 2024/0258204 A1).
Regarding claim 14, Guler in view of Chang teaches the semiconductor structure of claim 1,
Wherein Guler teaches that the semiconductor structure further comprises:
a middle-of-line contact (one or more conductive vias 1104, Illustrative Fig. 1, [0064]) connects to a source/drain (source or drain region 602, Illustrative Fig. 1, Fig. 2A) of one or more semiconductor devices (semiconductor devices on the right side of the semiconductor device 2, Illustrative Fig. 1) of the plurality of semiconductor devices (Illustrative Fig. 1), wherein the source/drain (source or drain region 602 with the connective via 1104, Illustrative Fig. 1) resides on a bottom dielectric isolation layer (dielectric layer 1402, Illustrative Fig. 1, [0069]).
Guler and Chang, however, do not teach that
the middle-of-line contact connects the source/drain of one or more semiconductor devices of the plurality of semiconductor devices to a back-end-of-line interconnect wiring layer;
a carrier wafer contacts the back-end-of-line interconnect wiring; and
a backside power delivery network is directly under the backside power rail.
Lee, on the other hand, teaches a semiconductor structure (semiconductor device structure 200, Fig. 2, [0056]), wherein
a middle-of-line contact (contact vias 207, Fig. 2, [0061]) connects the source/drain (first source-drain 216a, Fig. 2, [0059]) of one or more semiconductor devices (leftmost semiconductor device 201, Fig. 2, [0056]) of the plurality of semiconductor devices (semiconductor devices 201, Fig. 2) to a back-end-of-line interconnect wiring layer (back-end-of-line (BEOL) layers 206, Fig. 2, [0061]);
a carrier wafer (carrier wafer 215, Fig. 2, [0064]) contacts the back-end-of-line interconnect wiring (back-end-of-line (BEOL) layers 206, Fig. 2: carrier wafer 215 contacts the back-end-of-line (BEOL) layers 206 via the bonding oxide 205).
Lee further discloses that Lee’s device design improves power rail effectiveness and
prevent IR drop ([0004]). Therefore, a person of ordinary skill in the art before the effective filing date f the claimed invention would be motivated to include a back-end-of-line interconnect wiring layer connecting to a source/drain via a middle-of-line contact and a carrier wafer contacting the back-end-of-line interconnect wiring in the semiconductor structure of Shin, as taught by Lee, to improve the power rail effectiveness and prevent IR drop.
Guler, Chang and Lee, however, do not teach
a backside power delivery network is directly under the backside power rail.
Kim, on the other hand, teaches a semiconductor device (semiconductor device 100, Figs. 1 and 5A-C, [0020]) wherein
a backside power delivery network (back side power delivery network
(BSPDN), [0051]: “The backside power structure 180 may form a BSPDN”, Fig. 5B) is directly under the backside power rail (power distribution line 182, Fig. 5B, [0070]).
Kim further discloses that semiconductor devices having a back side power delivery network (BSPDN) structure in which a power rail is disposed on a backside of a wafer increases the degree of device integration ([0003]) and improved device reliability ([0004]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to include a backside power delivery network directly under the backside power rail in the semiconductor structure of Guler in views of Chang and Lee, as taught by Kim, to facilitate integration of semiconductor devices and improve device performance.
Thus, the combination of Guler, Chang, Lee, and Kim meets all the limitations of claim 14.
Allowable Subject Matter
Claims 5, 8-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 5, disclosing that “the backside contact has a bottom contact area width of approximately two contacted gate pitches”, would be allowable if the width of the bottom contact area to be two contacted gate pitches is disclosed in an independent form or incorporated in claim 1. The closest prior art is, as indicated for claim 1, Guler in view of Chang. While Chang teaches that the area of the backside contact should be increased to decrease the contact resistance with the backside power rail ([0097]), the limit that the width of the contact area can be extended in the semiconductor structure of Guler in view of Chang is less than two contacted gate pitches (see Illustrative Fig. 1: otherwise, adjacent bottom contacts would touch each other). There has been no prior art identified that can by itself or in combination with others render claim 5 obvious with the inherited limitations from claim 1.
Claim 8, disclosing that “the backside contact includes a portion of a semiconductor material below and between two immediately adjacent source/drains”, would be allowable if this limitation is disclosed in an independent form or incorporated in claim 1. Regarding the closest prior art, Shin (US 20240274679 A1) is the closest prior art, as detailed in the office action mailed on 1/28/2026. After amending claim 1, Shin now fails to teach “two immediately adjacent source/drains”. There has been no prior art identified that can modify the semiconductor structure of Guler in view of Chang further to make the backside contact to include a portion of a semiconductor material below and between two immediately adjacent source/drains.
Claims 9 and 12 are dependent on objected claim 8, and therefore would be allowable if the objection on claim 8 is overcome.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 3, 5, 7-11, and 13-17, and canceled claim 2 per response dated on 3/25/2026. Applicant's arguments with respect to claims have been fully considered.
Applicant argues in substance:
The Office Action objected to Claim 13 for alleged indefiniteness related to the term "two adjacent source/drains have a space less than one contacted gate pitch between the two adjacent source/drains." (See, Office Action, pg. 2). Applicant has amended Claim 13 for clarification purposes and to recite, wherein a distance of a space between two adjacent source/drains is less than one contacted gate pitch of the two adjacent semiconductor devices.
The Examiner respectfully disagrees with the Applicant on that amended claim 13 overcame the claim objection. As explained in the office action above, amended claim 13 remains to be unclear.
The Office Action rejected Claims 1-2 and 7-8 under 35 U.S.C. §102(a)(b) as being anticipated by U.S. Publication No. 20240274679 to Shin et al. ("Shin"). Of the rejected claims, Claim 1 is the sole independent claim. Claim 1 recites, in part, "a backside contact connects the two immediately adjacent source/drains of the two adjacent semiconductor devices to a backside power rail." The Office Action relies on two of the lower contacts 196 as reading on the claimed element of a "backside contact." (See, Office Action, pgs. 4-5). Applicant respectfully disagrees with this portion of the rejection because the Office Action is relying on a plurality of separate lower contacts 196 rather than the single backside contact claimed.
The Examiner respectfully disagrees with applicant as also discussed during the Interview on 3/31/2026 (see Interview Summary). However, any further consideration of this issue is not necessary because amended claim 1 overcame the rejection based on Shin, and Shin is not used as a prior art in the current office action.
The Office Action also rejected Claims 1, 3, 6 and 13 under 35 U.S.C. §102(a)(2) as being anticipated by U.S. Publication No. 20240321737 to Guler et al. ("Guler"). Of these rejected claims, Claim 1 is the sole independent claim. Claim 1 has been amended to incorporate the elements of cancelled Claim 2, thus rendering the above rejection moot.
The Examiner agrees with the Applicant on that the amended claim 1 overcame the 35 U.S.C. 102 rejection based on Guler. However, claim 1 is now rejected under new grounds based on Guler combined with a new prior art Chang (US 2021/0343578 A1) in the current office action above. Claims 1, 3-7, 10-11, 13, and 15-17 are also rejected by the combination of Guler and Chang.
The Office Action also rejected Claims 15-16 under 35 U.S.C. §102(a)(2) as being anticipated by U.S. Publication No. 20240321689 to Park et al. ("Park"). Of these rejected claims, Claim 15 is the sole independent claim. Claim 15 has been amended to incorporate the elements of amended Claim 1, and Applicant respectfully submits that Park fails to disclose each of the elements of amended Claim 15 for at least the reasons discussed above with regard to Claim 1.
The Examiner agrees with the Applicant on that the amended claim 15 overcame the rejection made on claims 15-16 based on Park. However, claims 15-16 are now rejected under new grounds based on Guler and Chang.
The Examiner also notes that, upon further consideration, the status of 10-11, which were indicated as containing allowable subject matter in the previous office action, is changed. Claims 10-11 are now rejected based on Guler in view of Chang as detailed above in the office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Guler (US 2023/0275124 A1) teaches backside contact connecting source/drain regions of adjacent semiconductor devices, which is relevant to all claims.
Liaw (US 2023/0378190 A1) teaches backside connections for source/drain regions of adjacent semiconductor devices separated by diffusion barriers, which is relevant to all claims.
Liaw (US 2024/0055433 A1) teaches backside connections for source/drain regions of adjacent semiconductor devices separated by diffusion barriers, which is relevant to all claims.
Ju (US 2021/0351303 A1) teaches a backside contact for source/drain structures in a semiconductor device, which is relevant to claims 15-17.
Chu (US 2021/0399099 A1) teaches an epitaxial backside contact for a semiconductor device, which is relevant to claims 15-17.
Chang (US 2024/0064953 A1) teaches a backside contact for source/drain structures in a semiconductor device, which is relevant to claims 15-17.
The Examiner notes that this office action is non-final following the previous non-final office action mailed on 1/28/2026. The reason of this office action being a non-final is that, in the previous non-final office action, a double rejection was made for claim 1, the first based on Shin (US 2024/0274679 A1) and the second based on Guler (US 2024/0321737 A1). While remaining claims were examined fully considering Shin and its combination with other prior art, the same claims were examined from the perspective of Guler only, not considering Guler’s combination with other prior art. Therefore, the Applicant could have been misguided that incorporating claim 2 into claim 1, as the Applicant did in amended claim 1, could overcome the rejection by Guler. However, the Examiner already had a prior art that can be combined with Guler to reject amended claim 1. Therefore, the Examiner submits a second non-final office action to be fair to the Applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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