Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provision.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/23/2023 and 12/12/2024 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was pa/*tented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 12,13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KR 10-2016-0034717.
717 teaches:
a wiring substate (300) (a first substrate) on which a connection pad (336) is formed on a first surface (310a) there of (paragraph[0158]);
a chip body (330) (a second substrate) having a second surface (330a) opposing the first surface of the wiring surface (paragraphs [0158] and [0159]);
a chip (350) (element) comprising a chip body (paragraphs [0158] and [0159]);
shoulders (352) (connection member) formed on the wiring substrate (300) (paragraph [0094]);
a molding (sealing) layer (368a, 390) formed on the first surface of the wiring substrate to seal the chip (paragraph [0161]);
a redistribution insulating layer (394) covering the molding layer (paragraph [0160]);
a redistribution layer (394) connected to the connection pad (336) and disposed along the redirection insulating layer and the molding layer (paragraph [0160]);
a void (space) (374) is formed between the chip and the wiring substrate (paragraph [0162]);
the shoulders (connection member) serve as a boundary from the void and the molding layer between the chip and the wiring substrate (FIG.25);
the external terminal (384a) is exposed externally from the redirection insulating layer in a direction facing an upper side of the first surface (310a) of the wiring substrate (paragraph[0161]).
Claim 12:
positioning a connection pad (336) on a first surface of a first substrate (300);
mounting a second substrate (330), which has a first surface on which an element unit (350) is disposed, on the connection pad via a connecting member;
laminating a sealing layer (368a, 390) to enclose the second substrate (330), and dispose a space (374) between the first substrate (300) and the element unit (350);
exposing the connection pad (336) by removing a portion of the sealing layer (368a, 390);
connecting a redistribution layer (394) to the connection pad (336); and
positioning an insulating layer (394) to cover the sealing layer (368a,390), and externally expose a portion of the redistribution layer (394).
13. The method of claim 12, further comprising: positioning an external connection terminal (384a) to connect the external connection terminal to the exposed portion of the redistribution layer (394). (para 161 and Figure 25)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 5, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over 717.
‘717 fails to teach:
2. The package of claim 1, wherein the redistribution layer is connected to one surface of the external connection terminal, and is configured to extend along the interface between the sealing layer and the insulating layer to connect with the connection pad.
3. The package of claim 2, wherein the redistribution layer is configured to extend along a side incline of the sealing layer.
5. The package of claim 1, wherein the connecting member is a solder ball that connects the metal pad and the connection pad with each other.
7. The package of claim 1, wherein the redistribution layer is configured to connect the connecting member and the external connection terminal to each other by a through-via that passes through the sealing layer.
10. The package of claim 1, wherein the external connection terminal is a pillar that protrudes from the insulating layer.
Claim 2, ‘717 discloses the redistribution layer is connected to one surface of the external connection terminal and extends along the interface between the molding layer and the redistribution layer to be connected to the connection pad (paragraphs [0160] and [0161]).
Claim 3, ‘717 discloses referring to FIG. 25, the redistribution layer extends along a side inclined surface of the molding layer.
In regards to claims 2 and 3, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design the redistribution layer to connect to an external connection, because this is conventionally done in the art to provide electrical communication and/or power to the IC package.
Claim 5 ‘717 discloses a plurality of shoulders (36) are connected to a first shoulder pad (16) of the wiring substrate and a plurality of chip pads (34) of the chip (paragraphs [0046] to [0048]).
Claim 7 717 discloses a through region (314) having through holes (314a) penetrating a substrate body (310) is formed (paragraph [0102]), and the feature in which a through silicon via (392) may be formed (paragraph [0150]).
Claim 10 717 discloses referring to FIG. 25, the connection terminal (384a) already protrudes externally (paragraph [0020])
In regards to claims 5, 7 and 10, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a solder ball and a via to connect the redistribution layer, because this is conventionally done in the art to provide secure connections.
Claim(s) 6 and 11, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘717 as applied to claim 1 above, and further in view of KR 10-2021-0066380.
‘717 fails to teach:
6. The package of claim 1, wherein the element unit is a bulk-acoustic wave (BAW) resonator.
11. The package of claim 1, wherein the first substrate is mounted on the second substrate on a same surface of the second substrate on which the element unit is disposed.
14. The method of claim 13, further comprising attaching a support member to a second surface of the first substrate before mounting the second substrate on the connection pad.
Claim 6 ‘380 discloses a filter chip (102) is an acoustic wave filter, and the acoustic wave filter includes a surface acoustic wave filter (SAW) (paragraphs [0033] and [0038] to [0040], and FIG. 1)
Further Claims 11 and 14, ‘380 teaches the filter chip (102) is configured in plural in a cap PCB (120) (paragraphs [0041] and [0042], and FIG. 2)
In regards to claims 6 and 11,14, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a BAW and a mount a first substrate on a second substrate, because this is conventionally done in the art.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over 717 as applied to claim 1 above, and further in view of JP 2003-100937.
717 fails to teach:
8. The package of claim 1, further comprising a passive element disposed on a second surface of the first substrate, and configured to connect to the connection pad.
9. The package of claim 8, wherein the passive element is at least one of an inductor and a capacitor.
937 teaches a second grounding metal surface formed on a lower surface of a second substrate (20) and a passive component (110) mounted on a surface of the second substrate (20) (paragraph [0020] and FIG. 1)
‘937 discloses the passive component is a capacitor, an inductor, a resistor or the like (paragraph [0020])
In regards to claims 8 and 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a passive component, because it is conventionally done inn the art to adjust the capacitance of the package.
Claim(s) 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over 717 as applied to claim 1 above, and further in view of KR 10-2014-0043859.
‘717 fails to teach:
15. The method of claim 13, wherein the second substrate comprises a plurality of second substrates, and a dicing operation is performed between the plurality of second substrates.
16. The method of claim 15, further comprising removing the support member before the dicing operation between the plurality of second substrates.
‘859 discloses the feature in which referring to FIG. 4C, FIG. 4d and FIG 4e, a support member (140) is attached before dicing and removed again, and then, is removed by means of the laser cutting tool (152) (paragraph [0046]).
In regards to claims 8 and 9, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dice the substrate by laser, because it is conventionally done in the art to separate the devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
Prosecution Insights