Prosecution Insights
Last updated: April 19, 2026
Application No. 18/340,418

LOW REVERSE LEAKAGE CURRENT POWER SCHOTTKY DIODES HAVING REDUCED CURRENT CROWDING AT THE LOWER BLOCKING JUNCTION CORNERS

Non-Final OA §102
Filed
Jun 23, 2023
Examiner
HARRISON, MONICA D
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed, Inc.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
94%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allow Rate
857 granted / 936 resolved
+23.6% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
17 currently pending
Career history
953
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 936 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 2, 4-6, 9-11, 16, 17, 24, 26, 29, 30 and 33-63 are cancelled. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, 7, 8, 12, 15, 28, 31, 32 and 64 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al (9,929,284 B1). Regarding claim 1, Zhang et al discloses a Schottky diode (Figure 3B), comprising: a first contact (Figure 3B, reference 180); a second contact (Figure 3B, reference 110); and a semiconductor layer structure (Figure 3B, references 112, 120, 130, 140, 150, 160 and 170) between the first contact (Figure 3B, reference 180) and the second contact (Figure 3B, reference 110), the semiconductor layer structure (Figure 3B, references 112, 120, 230, 140, 150, 160 and 170) comprising: a current spreading layer having a first conductivity type (Figure 3B, reference 160); a drift region (Figure 3B, reference 230) between the second contact (Figure 3B, reference 110) and the current spreading layer (Figure 3B, reference 160), the drift region having the first conductivity type (Figure 3B, reference 230; N-type); and a first blocking junction having a second conductivity type (Figure 3B, reference 140, left; P-type) that is opposite the first conductivity type, the first blocking junction (Figure 3B, reference 140, left) extending downwardly from an upper surface of the semiconductor layer structure (Figure 3B, reference 170), wherein the current spreading layer has a first conductivity type dopant concentration that is at least 1.5 times greater than a first conductivity type dopant concentration of the drift region (column 8, lines 60-67 thru column 9, lines 1-13), and wherein the current spreading layer (Figure 3B, reference 160) vertically overlaps at least a portion of a lower half of the first blocking junction (Figure 3B, reference 140, left). Regarding claim 3, Zhang et al discloses further comprising a second blocking junction that is doped with dopants having the second conductivity type (Figure 3B, reference 140, right), the second blocking junction (Figure 3B, reference 140, right) extending downwardly from the upper surface of the semiconductor layer structure (Figure 3B, reference 170), where the first and second blocking junctions extend to a depth of between 1.0 and 2.0 microns into the semiconductor layer structure (Figure 3B, reference 140 left and right). Regarding claim 7, Zhang et al discloses wherein the first blocking junction is a channel implanted blocking junction (Figure 3B, reference 140, left). Regarding claim 8, Zhang et al discloses wherein the current spreading layer (Figure 3B, reference 160) extends farther downwardly into the semiconductor layer structure (Figure 3B, references 112, 120, 230, 140, 150, 160 and 170) than does the first blocking junction (Figure 3B, reference 140, left). Regarding claim 12, Zhang et al discloses wherein a bottom of the current spreading layer (Figure 3B, reference 160) extends at least as deep into the semiconductor layer structure (Figure 3B, references 112, 120, 130, 140, 150, 160 and 170) as a bottom of the first blocking junction (Figure 3B, reference 140, left), and a doping concentration of the current spreading layer at a depth into the semiconductor layer structure that is the same depth as the bottom of the first blocking junction is at least 1x1017/cm3 (column 8, lines 52-67 thru column 9, lines 1-13). Regarding claim 15, Zhang et al discloses wherein the current spreading layer is a buried current spreading layer (Figure 3B, reference 160) and the drift region is a lower drift region (Figure 3B, reference 130, lower), the semiconductor layer structure (Figure 3B, references 112, 120, 130, 140, 150, 160 and 170) further comprising an upper drift region (Figure 3B, reference 130, upper) that is between the current spreading layer (Figure 3B, reference 160) and the first contact (Figure 3B, reference 180). Regarding claim 28, Zhang et al discloses a Schottky diode (Figure 3B), comprising: a semiconductor layer structure(Figure 3B, references 112, 120, 130, 140, 150, 160 and 170) comprising: a lower drift region having a first conductivity type (Figure 3B, reference 230, lower); an upper drift region having the first conductivity type (Figure 2B, reference 130, upper); a current spreading layer having the first conductivity type (Figure 3B, reference 160) between the lower drift region and the upper drift region (Figure 3B, reference 130 upper and lower), where a first conductivity type dopant concentration of the current spreading layer (Figure 3B, reference 160) is higher than a first conductivity type dopant concentration of the lower drift region and is higher than a first conductivity type dopant concentration of the upper drift region (Figure 3B, reference 130 upper and lower; column 8, lines 52-67 thru column 9, lines 1-13); a first blocking junction having a second conductivity type (Figure 3B, reference 140, left) that is opposite the first conductivity type; and a second blocking junction having the second conductivity type (Figure 3B, reference 140, right), wherein the first and second blocking junctions (Figure 3B, reference 140 left and right) define a conductive region therebetween (Figure 3B, reference 152). Regarding claim 31, Zhang et al discloses wherein the first contact (Figure 3B, reference 180) is adjacent top surfaces of the first and second blocking junctions (Figure 3B, reference 140 left and right) and bottom surfaces of the first and second blocking junctions are between 1.0 and 2.0 microns (Figure 3B, reference 140 left and right) from an upper surface of the semiconductor layer structure (Figure 3B, references 112, 120, 130, 140, 150, 160 and 170). Regarding claim 32, Zhang et al discloses wherein a bottom surface of the current spreading layer (Figure 3B, reference 160) is farther from the first contact (Figure 3B, reference 180) than are bottom surfaces of the first and second blocking junctions (Figure 3B, reference 140, left and right). Regarding claim 64, Zhang et al discloses wherein a maximum width of an upper half of the first blocking junction exceeds a maximum width of a lower half of the first blocking junction (Figure 3B, reference 140, left). Allowable Subject Matter Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest a Schottky diode, comprising: wherein at least a first portion of the current spreading layer has a graded doping concentration of first conductivity type dopants, where in the first portion the doping concentration of first conductivity type dopants increases with increasing depth into the semiconductor layer structure (claim 13), further incorporated into independent claim 1 and in the context of its recited apparatus, along with its depending claims. Claims 18-23, 25, 27 and 65 is allowed over the prior art. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest a Schottky diode, comprising: a first blocking junction adjacent the first contact, the first blocking junction having a second conductivity type that is opposite the first conductivity type, wherein a first portion of the current spreading layer has a graded dopant concentration that increases with increasing distance from the first contact as described in independent claim 18 and in the context of its recited apparatus, along with its depending claims. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/ Primary Examiner, Art Unit 2815 mdh February 11, 2026
Read full office action

Prosecution Timeline

Jun 23, 2023
Application Filed
Feb 11, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
94%
With Interview (+2.6%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 936 resolved cases by this examiner. Grant probability derived from career allow rate.

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