DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (PG Pub. No. US 2020/0220018 A1) in view of Chen et al. (PG Pub. No. US 2021/0366786 A1).
Regarding claim 1, Jang teaches a semiconductor device (¶ 0064 & figs. 2, 9 among others: 100c) comprising:
an active region (¶ 0022: 105) extending on a substrate in a first direction that is parallel to an upper surface of the substrate (fig. 2: 105 extends on substrate 101 in x-direction parallel to upper surface of 101);
a plurality of channel layers (¶ 0022: 141, 142 and 143) on the active region and are spaced apart from each other in a vertical direction that is perpendicular to the upper surface of the substrate (fig. 2: 141/142/143 arranged on 105 and vertically spaced in z-direction to surface of 101);
a gate structure (¶ 0022: 160) intersecting the active region and the plurality of channel layers (fig. 2: 160 intersects 105 and 141/142/143) and extending on the substrate in a second direction that is parallel to the upper surface of the substrate (fig. 2: 160 extends on 101 in y-direction parallel to surface of 101), and surrounding each of the plurality of channel layers (fig. 2: 160 surrounds 141, 142 and 143); and
a source/drain region (¶ 0064: 150c) that is adjacent to the gate structure on the active region and contacts the plurality of channel layers (fig. 9: 150c adjacent to 160 on 105 and contacts layers 141/142/143),
wherein the source/drain region comprises:
a first epitaxial layer (¶ 0064: 151) including first layers that are on side surfaces of the plurality of channel layers, respectively (¶ 0065, fig. 9: 151 includes first portions on side surfaces of 141/142/143), and a second layer that is at a lower end of the source/drain region on the active region (¶ 0065, fig. 9: 151 includes a second portion at a bottom of epitaxial layer 152c), wherein the first epitaxial layer includes first impurities (¶ 0085: 151 comprises impurities);
a second epitaxial layer (¶ 0064: 152c) filling a space between the first layers and the second layer (fig. 9: 152c fills space between first and second portions of 151), wherein the second epitaxial layer includes second impurities (¶¶ 0049, 0065, 0087: 152c corresponds to 152 of fig. 6, which includes impurities) which are different from the first impurities (¶ 0058: 152, corresponding to 152c of fig. 9, comprises impurities with a different concentration than impurities of 151; therefore, the limitation of second impurities “different from” first impurities is met), and includes a recessed upper surface (fig. 9: 152c comprises a recessed upper surface); and
a third epitaxial layer (¶ 0064: 154c) on the second epitaxial layer (fig. 9: 154c arranged on 152c), wherein a portion of the third epitaxial layer does not include the second impurities (¶¶ 0047, 0051: 154, corresponding to 154c of fig. 9, comprises different impurities than 152, corresponding to 152c of fig. 9).
Jang does not teach the third epitaxial layer does not include the first impurities.
Chen teaches a semiconductor device (¶ 0079 & figs. 25A-25B) including a source/drain region (¶ 0015: 70, similar to 150c of Jang), the source/drain region comprising a first epitaxial layer with first impurities (¶ 0039: 70A), a second epitaxial layer with second impurities (¶ 0039: 70B) and a third epitaxial layer (¶ 0038: 70C), wherein the third epitaxial layer does not include the first impurities and the second impurities (¶ 0042: in at least one embodiment, 70C comprises undoped semiconductor material).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure a portion of the third epitaxial layer of Jang to not include first and second impurities, as a means to provide protection to underlying epitaxial layers while forming contact structures (98 of Chen, 180 of Jang).
Regarding claim 2, Jang in view of Chen teaches the semiconductor device of claim 1, wherein the first layers and the second layer are spaced apart from each other (Jang, fig. 9: first portions of 151 spaced apart from second portion of 151).
Regarding claim 3, Jang in view of Chen teaches the semiconductor device of claim 1, further comprising:
internal spacer layers (Jang, ¶ 0022: 130) that are on a side surface of the source/drain region adjacent to the gate structure in the first direction (Jang, fig. 9: 130 on a side surface of 150c adjacent to 140 in x-direction) and are respectively on lower surfaces of the plurality of channel layers (Jang, fig. 9: 130 disposed on lower surfaces of 141/142/143).
Regarding claim 4, Jang in view of Chen teaches the semiconductor device of claim 3, wherein the first layers protrude toward the second epitaxial layer from a side surface comprising the internal spacer layers and the plurality of channel layers (Jang, fig. 9: first portions of 151 protrude toward 152c from side surface comprising 130 and 141/142/143).
Regarding claim 5, Jang in view of Chen teaches the semiconductor device of claim 3, wherein each of the first layers is surrounded by the second epitaxial layer and a respective one of the plurality of channel layers (Jang, fig. 9: each first portion of 151 surrounded by 152c and 141/142/143).
Regarding claim 6, Jang in view of Chen teaches the semiconductor device of claim 1, wherein the first epitaxial layer includes a first material different from a second material included in the second epitaxial layer (Jang, ¶¶ 0032, 0058: material of 151 different in size, shape, and/or composition relative to material of 152c).
Regarding claim 7, Jang in view of Chen teaches the semiconductor device of claim 1, wherein the third epitaxial layer is in contact with a portion of the first epitaxial layer (Jang, fig. 9: 154c in electrical contact with 151).
Regarding claim 9, Jang in view of Chen teaches the semiconductor device of claim 1, wherein an upper end of the third epitaxial layer is disposed on a level, higher than a level of an upper surface of an uppermost channel layer, among the plurality of channel layers (Jang, fig. 9: upper end of 154 higher than upper surface of 143).
Regarding claim 10, Jang in view of Chen teaches the semiconductor device of claim 1, further comprising:
an interlayer insulating layer (Jang, ¶ 0022: 190) on the third epitaxial layer (Jang, fig. 9: 190 disposed on 154c); and
a contact plug (Jang, ¶ 0022: 180) penetrating through a portion of the interlayer insulating layer, the third epitaxial layer, and the second epitaxial layer (Jang, fig. 9: 180 penetrates through a portion of 190, 154c and 152c).
Regarding claim 11, Jang in view of Chen teaches the semiconductor device of claim 10, wherein the contact plug is spaced apart from the second epitaxial layer by the third epitaxial layer (Jang, fig. 9: 180 spaced apart from 152c by 154c).
Regarding claim 12, Jang in view of Chen teaches the semiconductor device of claim 10, including a contact plug (Jang, ¶ 0022: 180).
Jang in view of Chen as applied to claim 10 above does not teach wherein the contact plug includes a metal-semiconductor compound layer, and
the metal-semiconductor compound layer is in contact with the second epitaxial layer and the third epitaxial layer.
However, Chen teaches a contact plug (¶ 0062: 96/98) including a metal-semiconductor compound layer (silicide 96), and
the metal-semiconductor compound layer is in contact with a second epitaxial layer and a third epitaxial layer (fig. 21A: 96 contacts 70B and 70C).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the contact plug of Jang in view of Chen to further include a metal-semiconductor compound layer, as a means to reduce contact resistance of the source/drain region.
Regarding claim 13, Jang in view of Chen teaches the semiconductor device of claim 12, wherein the third epitaxial layer includes a first portion, disposed below the contact plug, and a second portion on a side surface of the contact plug (Jang, fig. 9: 154c includes a portion below 180 and a portion on a side surface of 180), and
the first portion is spaced apart from the second portion by the contact plug (Jang, fig. 9: portions of 154c spaced apart by 180).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Chen as applied to claim 1 above, and further in view of Yin et al (PG Pub. No. US 2022/0157969 A1).
Regarding claim 8, Jang in view of Chen teaches the semiconductor device of claim 1, comprising a second layer (Jang, bottom portion of 151) and a gate structure (Jang, 160).
Jang in view of Chen does not teach wherein an upper end of the second layer is disposed on a level, higher than a level of a lowermost layer of the gate structure.
Yin teaches a semiconductor device (¶ 0038 & fig. 20: 200) including an upper end of a second layer (¶ 0028: bottom portion of 238) disposed on a level, higher than a level of a lowermost layer of a gate structure (fig. 20: bottom portion of 238 higher than lowermost layer of gate 260).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to arrange an upper end of the second layer of Jang in view of Chen on a level, higher than a level of a lowermost layer of the gate structure, as a means to improve hole mobility, reduce defects and reduce contact resistance (Yin, ¶ 0032).
Claims 14-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong in view of Hsu et al. (PG Pub. No. US 2020/0168723 A1).
Regarding claim 14, Jang teaches a semiconductor device comprising:
an active region (105) extending on a substrate (101) in a first direction that is parallel to an upper surface of the substrate (fig. 7);
a plurality of channel layers (141/142/143) on the active region (fig. 7) and
a gate structure (160) intersecting the active region and the plurality of channel layers (fig. 7) and extending on the substrate in a second direction that is parallel to the upper surface of the substrate (fig. 7), and surrounding each of the plurality of channel layers (figs. 7, 9); and
a source/drain region (150c) that is adjacent to the gate structure on the active region and contacts the plurality of channel layers (fig. 9),
wherein the source/drain region comprises:
a first epitaxial layer (151) including first layers that are on side surfaces of the plurality of channel layers (first portions of 151 disposed on 141/142/143), respectively, and a second layer that is at a lower end of the source/drain region on the active region (second portion of 151 on bottom of 150c), wherein the second layer is separated from the first layers (fig. 9);
a second epitaxial layer (152c), filling a space between each of the first layers and the second layer (fig. 7: 152c fills space between first and second portions of 151), the second epitaxial layer includes a recessed upper surface (fig. 9: upper surface of 152c recessed); and
a third epitaxial layer (154c) on the second epitaxial layer (fig. 9: 154c disposed on 152c),
a portion of the second epitaxial layer is in contact with the active region (fig. 9: portion of 152c contacts 105), and
the third epitaxial layer is spaced apart from the first epitaxial layer (fig. 9: 154c spaced apart from 151).
Jang does not teach the source/drain region further comprises a fourth epitaxial layer between a lower portion of the third epitaxial layer and the recessed upper surface of the second epitaxial layer, the third epitaxial layer is spaced apart from the first epitaxial layer by the fourth epitaxial layer.
Hsu teaches a semiconductor device (figs. 23A-23B) including a source/drain region (¶ 0013: 82), the source/drain region comprising a fourth epitaxial layer (¶ 0047: 84B) between a lower portion of a third epitaxial layer (¶ 0040: 82B) and an upper surface of a second epitaxial layer (¶¶ 0047-0048, fig. 23B: 84B disposed between epitaxial layers 82B and 82C), the third epitaxial layer spaced apart from the first epitaxial layer by the fourth epitaxial layer (fig. 23B: 82C spaced apart from 82B by 84B).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the source/drain region of Jang to further include a fourth epitaxial layer, as a means to enhance stress in respective channel regions, thereby improving performance (Hsu, ¶ 0036), and/or improve the epitaxial growth of source/drain structures (Hsu, ¶ 0043).
Regarding claim 15, Jang in view of Hsu teaches the semiconductor device of claim 14, wherein the fourth epitaxial layer has a thickness substantially uniform along the lower portion of the third epitaxial layer and the recessed upper surface of the second epitaxial layer (Hsu, fig. 23B: 84B comprises a substantially uniform thickness along the lower portion of 82C and the recessed upper surface of 82B), and the thickness is in a range of about 1 angstrom (A) to about 2 nanometers (nm) (Hsu, ¶ 0043: thickness of 84B about 2Å).
Regarding claim 16, Jang in view of Hsu teaches the semiconductor device of claim 14, wherein a portion of the third epitaxial layer does not include impurities (Jang, ¶ 0034: in at least one embodiment, 154 does not include first impurities, meeting the broadest reasonable interpretation of “does not include impurities”), and
the fourth epitaxial layer includes silicon-germanium (Hsu, ¶ 0047: 84B includes Si1-xGex).
Regarding claim 18, Jang in view of Hsu teaches the semiconductor device of claim 14, wherein an uppermost portion of the third epitaxial layer is disposed on a level, higher than a level of an uppermost portion of the plurality of channel layers (Jang, fig. 9: uppermost portion of 154c higher than level of uppermost portion of 141/142/143).
Regarding claim 19, Jang in view of Hsu teaches the semiconductor device of claim 14, wherein the plurality of channel layers includes a first channel layer as a lowermost channel layer, a second channel layer as a channel layer directly above the first channel layer (Jang, fig. 9: lowermost channel 141, second channel layer 142 directly above 141), and
a lowermost portion of the third epitaxial layer is disposed on a level, lower than a level of a lower surface of the second channel layer (Jang, fig. 9: lowermost portion of 154c is disposed on a level, lower than a level of a lower surface of 142).
Regarding claim 20, Jang teaches a semiconductor device comprising:
an active region (105) extending on a substrate (101) in a first direction that is parallel to an upper surface of the substrate (fig. 7);
a plurality of channel layers (141/142/143) on the active region (fig. 7) and
a gate structure (160) intersecting the active region and the plurality of channel layers (fig. 7) and extending on the substrate in a second direction that is parallel to the upper surface of the substrate (fig. 7), and surrounding each of the plurality of channel layers (figs. 7, 9); and
a source/drain region (150c) that is adjacent to the gate structure on the active region and contacts the plurality of channel layers (fig. 9),
wherein the source/drain region comprises:
a first epitaxial layer (151) including first layers on side surfaces of the plurality of channel layers (first portions of 151 disposed on 141/142/143), respectively, and a second layer that is at a low end of the source/drain region on the active region (second portion of 151 on bottom of 150c),
a second epitaxial layer (152c), filling a space between each of the first layers and the second layer (fig. 7: 152c fills space between first and second portions of 151), the second epitaxial layer includes a recessed upper surface (fig. 9: upper surface of 152c recessed); and
a third epitaxial layer (154c) on the second epitaxial layer (fig. 9: 154c disposed on 152c),
each of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer includes a silicon epitaxial layer (¶¶ 0058, 0032, 0029: 151, 152c and 154c comprise silicon epitaxy).
Jang does not teach the source/drain region further comprising a fourth epitaxial layer between the second epitaxial layer and the third epitaxial layer, the fourth epitaxial layer includes a silicon-germanium layer, and the fourth epitaxial layer has a thickness in a range of about 1 angstrom (A) to about 2 nanometers (nm).
Hsu teaches a semiconductor device (figs. 23A-23B) including a source/drain region (¶ 0013: 82), the source/drain region comprising a fourth epitaxial layer (¶ 0047: 84B) between a second epitaxial layer (¶ 0047: 82C) and a third epitaxial layer (¶¶ 0047-0048, fig. 23B: 84B disposed between epitaxial layers 82C and 82B), the fourth epitaxial layer includes a silicon-germanium layer (¶ 0047: 84B includes Si1-xGex), and the fourth epitaxial layer has a thickness is in a range of about 1 angstrom (A) to about 2 nanometers (nm) (¶ 0043: thickness of 84B about 2Å).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the source/drain region of Jang to further include a fourth epitaxial layer, as a means to enhance stress in respective channel regions, thereby improving performance (Hsu, ¶ 0036), and/or improve the epitaxial growth of source/drain structures (Hsu, ¶ 0043).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Hsu as applied to claim 14 above, and further in view of Yin.
Regarding claim 17, Jang in view of Hsu teaches the semiconductor device of claim 14, comprising a plurality of channel layers (Jang, 141, 142, 143) and a source/drain region (Jang, 150c).
Jang in view of Hsu does not teach wherein a thickness of each of the plurality of channel layers in the vertical direction decreases in a direction toward the source/drain region.
Yin teaches a semiconductor device (fig. 20: 200) including a plurality of channel layers (¶ 0027: 2080, similar to 141, 142, 143 of Jang) and a source/drain region (¶ 0033: 244, similar to 150c of Jang), wherein a thickness of each of the plurality of channel layers in the vertical direction decreases in a direction toward the source/drain region (fig. 20 among others: thickness of each 2080 in the vertical direction decreases in a direction toward 244).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the channel layers of Jang in view of Hsu with decreasing thickness, as a means to optimize formation of the first epitaxial layer on end portions of the channel layers (Yin, ¶ 0028), providing the first epitaxial layer with facets (Yin, ¶ 0029), minimizing defects and contact resistance (Yin, ¶ 0032).
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818