DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on August 9, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 26, 2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vertical Non-volatile Memory Devices With Improved Coupling.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-17) in the reply filed on November 10, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-11, 14, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2020/0373325).
Claim 1, Kim discloses (Fig. 16) a vertical non-volatile memory device, comprising: a cell substrate (22, base may be semiconductor substrate, Para [0027]); a mold structure (12, stack, Para [0027]) that includes a first insulation pattern (bottommost 18, first material may be silicon oxide, Para [0024], hereinafter “ins1”), a first gate electrode (bottommost 62 of 64, second material electrically conductive of gate, Para [0056] –[0061], hereinafter “g1”), and a second insulation pattern (middle 18, hereinafter “ins2”) which are sequentially stacked on the cell substrate (ins1, g1, and ins2 are sequentially stacked on22); a semiconductor pattern (46, channel material of semiconductor, Para [0050]) that extends through the mold structure (46 extends through 12 in vertical direction) in a first direction (vertical direction) intersecting a top surface of the cell substrate (vertical direction intersects top surface of 22); a first charge insulation layer (bottommost 32, insulative material, Para [0065], hereinafter “c1”) between the first insulation pattern and the semiconductor pattern (c1 is between ins1 and 46); a second charge insulation layer (middle 32, hereinafter “c2”) spaced apart from the first charge insulation layer (c2 is spaced apart from c1) and between the second insulation pattern and the semiconductor pattern (c2 is between ins2 and 46); a charge storage layer (bottommost 42, charge-trapping material, Para [0065], hereinafter “store”) between the first charge insulation layer and the second charge insulation layer (store is vertically between c1 and c2) and between the first gate electrode and the semiconductor pattern (store is laterally between g1 and 46); and a first blocking insulation layer (40, charge-blocking material, Para [0066]) between the first gate electrode and the charge storage layer (40 is between g1and store), wherein a first length in the first direction of the first gate electrode (length in vertical direction of g1, hereinafter “L1”) is shorter than a second length in the first direction of a first surface of the charge storage layer which is in contact with (length in vertical direction of first surface of 42 contacting 40, hereinafter “L2”) the first blocking insulation layer (L1 is shorter than L2). Claim 2, Kim discloses (Fig. 16) the vertical non-volatile memory device of claim 1, wherein the first blocking insulation layer (40) is between the first charge insulation layer and the second charge insulation layer (40 is between c1 and c2). Claim 8, Kim discloses (Fig. 16) the vertical non-volatile memory device of claim 1, wherein the first charge insulation layer (c1) includes a material different from that of the first insulation (ins1) pattern (32 may be a different material than 18, Para [0036]). Claim 9, Kim discloses (Fig. 16) the vertical non-volatile memory device of claim 8, wherein the second charge insulation layer (c2) includes a material different from that of the second insulation (ins2) pattern (32 may be a different material than 18, Para [0036]).
Claim 10, Kim discloses (see annotated Fig. 16 below) a vertical non-volatile memory device, comprising: a cell substrate (22, base may be semiconductor substrate, Para [0027]); a mold structure a mold structure (12, stack, Para [0027]) that includes a first gate electrode (bottom 62 of 64, second material electrically conductive of gate, Para [0056] –[0061], hereinafter “g1”), an insulation pattern (bottommost 18, first material may be silicon oxide, Para [0024], hereinafter “ins1”), and a second gate electrode (top 62 of 64, second material electrically conductive of gate, Para [0056] –[0061], hereinafter “g2”), which are sequentially stacked on the cell substrate (g1, ins1, and g2 are sequentially stacked on 22); a semiconductor pattern (46, channel material of semiconductor, Para [0050]) that extends through the mold structure (46 extends through 12 in vertical direction) in a first direction (vertical direction) intersecting a top surface of the cell substrate (vertical direction intersects top surface of 22); a first charge storage layer (bottom 42, charge-storage layer, Para [0064], hereinafter “cs1”) between the first gate electrode and the semiconductor pattern (cs1 is laterally between g1 and 46); a second charge storage layer (top 42, charge-storage layer, Para [0064], hereinafter “cs2”) spaced apart from the first charge storage layer (cs2 is vertically spaced apart from cs1) and between the second gate electrode and the semiconductor pattern (cs2 is laterally between g2 and 46); a first blocking insulation layer (bottom 52, dielectric-barrier material, hereinafter “b1”) between the first gate electrode and the first charge storage layer (b1 is laterally between g1 and cs1); and a second blocking insulation layer (top 52, dielectric-barrier material, hereinafter “b2”) spaced apart from the first blocking insulation layer (b2 is vertically spaced apart from b1) and between the second gate electrode and the second charge storage layer (b2 is between g2 and cs2), wherein a first distance (L1) between the first charge storage layer and the second charge storage layer (L1 is vertical distance between cs1 and cs2 is labeled in the figure below) is shorter (L1 is shorter than L2) than a second distance (L2) between the first gate electrode and the second gate electrode (L2 is vertical distance between g1 and g2).
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Claim 11, Kim discloses (see annotated Fig. 16 above) the vertical non-volatile memory device of claim 10, wherein a third distance (L3) between the first blocking insulation layer and the second blocking insulation layer (L3 is vertical distance between b1 and b2 is labeled in the figure above) is shorter than the second distance (L3 is shorter than L2).
Claim 14, Kim discloses (see annotated Fig. 16 above) the vertical non-volatile memory device of claim 10, further comprising a charge insulation layer (middle 32, insulative material, Para [0065]) between the first charge storage layer and the second charge storage layer (middle 32 is vertically between cs1 and cs2). Claim 16, Kim discloses (see annotated Fig. 16 above) the vertical non-volatile memory device of claim 14, wherein the charge insulation layer (middle 32) includes a material different from that of the insulation (ins1) pattern (32 may be a different material than 18, Para [0036]). Claim 17, Kim discloses (see annotated Fig. 16 above) the vertical non-volatile memory device of claim 14, wherein the charge insulation layer (middle 32) is between the first blocking insulation layer and the second blocking insulation layer (portion of middle 32 is between b1 and b2).
Allowable Subject Matter
Claims 3-7, 12-13, and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Kim (US 2020/0373325), Kim (US Pat. No. 10,593,695), Daycock (US Pat. No. 10,,083,981), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3 (from which claims 4-6 depend), wherein a third length in the first direction of a second surface of the charge storage layer which is opposite to the semiconductor pattern is longer than the second length.
Regarding Claim 7, wherein a length of the charge storage layer in the first direction increases toward the semiconductor pattern.
Regarding Claim 12, wherein the first distance decreases as the first and second charge storage layers extend closer to the semiconductor pattern.
Regarding Claim 13, wherein a fourth distance between the first barrier layer and the second barrier layer is shorter than the first distance.
Regarding Claim 15, wherein a surface of the first charge storage layer is in contact with the charge insulation layer and has a concave shape.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US Pat. No. 10,593,695) discloses (Fig. 17) a mold structure 62 over a substrate 22, semiconductor channel 46, tunneling insulation 38, block insulation layer 52. Kim does not disclose a second charge insulation layer apart from the first charge insulation layer.
Daycock (US Pat. No. 10,,083,981) discloses (Fig. 2) a mold structure 15 over a substrate 52, semiconductor channel 48, tunneling insulation 46, block insulation layer 53. Daycock does not disclose a second charge insulation layer apart from the first charge insulation layer.
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/G.G.R/Examiner, Art Unit 2812