Last updated: July 17, 2026

Application No. 18/341,124

METHODS OF TRAINING DEEP LEARNING MODELS FOR OPTICAL PROXIMITY CORRECTION, OPTICAL PROXIMITY CORRECTION METHODS, AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME

Non-Final OA

Filed

Jun 26, 2023

Priority

Nov 14, 2022 — RE 10-2022-0151854

Examiner

AISAKA, BRYCE M

Art Unit

2851

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Samsung Electronics Co., Ltd.

OA Round

1 (Non-Final)

Interview Optional

— +10.5% interview lift. Interview already conducted in this application's prosecution history. This examiner has a 87% grant rate with +10.5% interview lift. Since an interview has already been tried, recommend written response with narrowed claims based on precedent claim evolution patterns.

Based on 743 resolved cases, 2023–2026

Examiner Intelligence

AISAKA, BRYCE M View full profile →

Grants 87% — above average

Career Allowance Rate

649 granted / 743 resolved

+19.3% vs TC avg

Moderate +10% lift

Without

With

+10.5%

Interview Lift

resolved cases with interview

Typical timeline

2y 4m

Avg Prosecution

21 currently pending

Career history

751

Total Applications

across all art units

Statute-Specific Performance

§101

18.7%

-21.3% vs TC avg

§103

37.5%

-2.5% vs TC avg

§102

14.9%

-25.1% vs TC avg

§112

25.2%

-14.8% vs TC avg

Black line = Tech Center average estimate • Based on career data from 743 resolved cases

Prosecution Timeline

Jun 26, 2023

Application Filed

Apr 22, 2026

Non-Final Rejection mailed

May 21, 2026

Applicant Interview (Telephonic)

May 21, 2026

Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

18/058,009

Patent 12679412

SAFETY AND PERFORMANCE FOR LOGIC DESIGN IN AUTONOMOUS VEHICLES

3y 7m to grant Granted Jul 14, 2026

18/090,584

Patent 12670305

DESIGN FOR TESTABILITY CIRCUITRY PLACEMENT WITHIN AN INTEGRATED CIRCUIT DESIGN

3y 6m to grant Granted Jun 30, 2026

18/119,844

Patent 12670306

DETECTION METHOD, SYSTEM, ELECTRONIC EQUIPMENT, AND STORAGE MEDIUM OF PRODUCT TEST DATA

3y 3m to grant Granted Jun 30, 2026

18/073,482

Patent 12664338

DEEP LEARNING-ENABLED INVERSE DESIGN OF MM-WAVE IMPEDANCE MATCHING CIRCUITS AND POWER AMPLIFIERS

3y 6m to grant Granted Jun 23, 2026

17/741,677

Patent 12658561

SYMMETRIC MULTI-IC MODULES USING HIERARCHICAL DIGITAL RECONFIGURATION OF INTEGRATED CIRCUIT CHIPS

4y 1m to grant Granted Jun 16, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2

Expected OA Rounds

87%

Grant Probability

98%

With Interview (+10.5%)

2y 4m (~0m remaining)

Median Time to Grant

Low

PTA Risk

Based on 743 resolved cases by this examiner. Grant probability derived from career allowance rate.