Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A in the reply filed on 11/10/2025 is acknowledged. Claim 3-4 and 8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 states in part “….wherein a porosity in a part of the bonding layer on an inside of the first outer edge is higher than a porosity in a part of the bonding layer on an inside of the second outer edge and on an outside of the first outer edge.” Examiner is interpreting this to mean that there are metal particles outside the first outer edge. But the first outer edge extends on the outside of the bonding interface between the bonding layer and the conductive plate. Outside of this is the sealing member. Thus, Examiner is not able to determine the meaning of this limitation. The specification recites the same limitation [see Para. [0027]) without adding further clarification. For the purposes of this examination, Examiner is interpreting the claim to read “…….wherein a porosity in a part of the bonding layer on an inside of the first outer edge is higher than a porosity in a part of the bonding layer on an inside of the second outer edge
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 6 are rejected under 35 U.S.C. 102a1 as being anticipated by US20190006265A1 (Yamada).
Regarding Claim 1, Yamada discloses a semiconductor device (Fig. 4, el. 10, Para. [0067]) comprising: a conductive plate (Fig. 4, el.1 , Para. [0064]) having a main surface (see annotated Fig. 4 below); a semiconductor chip (Fig. 4, el. 3, Para. [0063]) deposited to be opposed to the main surface of the conductive plate (see annotated Fig. 4 below); and a bonding layer (Fig. 4, el. 2, Para. [0065]) including porous sintered material (Para. [0065], sintered silver paste is inherently porous) and arranged between the conductive plate and the semiconductor chip (Fig. 4), wherein a first outer edge of a bonding interface between the bonding layer and the conductive plate is located on an inside of an outer circumference of the semiconductor chip (see annotated Fig. 4 below) and is located on an inside of a second outer edge of a bonding interface between the bonding layer and the semiconductor chip (see annotated Fig. 4 below).
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Regarding Claim 5, Yamada discloses the semiconductor device of claim 1, wherein a surface of the bonding layer toward the conductive plate on an outside of the first outer edge is convex toward the conductive plate (see annotated Fig. 4 above).
Regarding Claim 6, Yamada discloses the semiconductor device of claim 1, wherein a stress-concentrated portion is provided in a part at the first outer edge (see annotated Fig. 4 above, and Para. [0070])).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of US20220045027A1 (Ochi).
Regarding Claim 2, Yamada discloses the semiconductor device of Claim 1.
Yamada does not disclose that an outer edge of the bonding layer toward the semiconductor chip projects outward from the outer circumference of the semiconductor chip.
Ochi discloses a bonding layer (Fig. 1, el. 5, Para. [0048]) where an outer edge of the bonding layer projects outward fromm the outer circumference of the semiconductor chip (see annotated Fig. 1 below and Para. [0048])
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It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to modify the bonding layer of Yamada to have an outer edge of the bonding layer project outward from the outer circumference of the semiconductor chip, as disclosed Ochi. As disclosed by Ochi, these kinds of configurations can enhance reliability (Para. [0048]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of US20180197833A1 (Sakakibara).
Regarding Claim 7, Yamada discloses the semiconductor of claim 1.
Yamada does not disclose that a porosity in a part of the bonding layer on an inside of the first outer edge is higher than a porosity in a part of the bonding layer on an inside of the second outer edge and on an outside of the first outer edge.
Sakakibara discloses a bonding layer that has a higher porosity portion and a lower porosity portion (Figs. 2 and 3, Para. [0030]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to include a higher porosity material in the part of the bonding layer closer to the conductive plate, to reduce thermal stress (Sakakibara, Para. [0006]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of US20150130085A1 (Hino).
Regarding Claim 9, Yamada discloses the semiconductor device of Claim 1.
Yamada does not disclose a sealing member provided to seal the semiconductor chip and the bonding layer wherein the first outer edge has a point at which three of the bonding layer, the conductive plate. and the sealing member overlap with each other.
Hino discloses a sealing member provided to seal a semiconductor chip and a bonding layer (Fig. 1, Paras. [0018-0021]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use sealing as in Hino to seal the semiconductor device and bonding layer of Yamada. Doing so would necessarily create a point at which the bonding layer, sealing member, and conductive plate overlap. Adding a sealing layer has the benefit of protecting the device and bonding layer from environmental stress.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899