DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 07 January 2026, with respect to specification, drawings, and claims 1-20 have been fully considered and are persuasive. The objections to specification, drawings, and claims and the 35 USC § 112 rejections of claims 1-20 have been withdrawn.
However, the examiner has found new objections to specification and drawings and rejections under 35 USC § 112 and § 102/103. In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 9 requires a “sequence of steps,” that is used to arrange the semiconductor chips on the substrate. Although this may be illustrated in Fig. 1A, the terminology of “a sequence of steps” is not used in par. [0029] of the instant application to describe the arrangement of the chips. Claim 20 requires “lateral extents” and/or “thickness profiles” of the solder protrusions that are not defined in the specification nor illustrated in the figures.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, and by extension, dependent claims 2-10, recite a limitation of “substrate wiring patterns including connection pads extending along at least one of a top surface and a bottom surface of each of the plurality of base insulating layers.” It is not clear whether it is just the connection pads that extend along said surfaces or if any other element of the wiring pattern extend along said surfaces. For the purpose of compact prosecution, the examiner will cite art that teaches the latter.
Claim 1, and by extension, dependent claims 2-10, define “a top surface of the package base substrate” (line 3) twice in the limitations of “the substrate cavity extending from a top surface of the package base substrate” and “wherein the plurality of semiconductor chips are is stacked in a direction that is perpendicular to a plane of the package substrate and protrudes upwards above a top surface of the package base substrate” (line 15). It is not clear if these two elements are the same top surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 2, and by extension, dependent claims 3-8, require “a bottom surface of the package base substrate” (line 3), which has been previously defined in parent claim 1 limitation of “the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate” (lines 2-4). It is not clear if these two elements are the same bottom surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 4, and by extension, dependent claim 8, require "a bottom surface of the package base substrate” (lines 3-4), which has been previously defined in parent claim 1 limitation of “the substrate cavity extending from a top surface of the package base substrate downwardly toward a bottom surface of the package base substrate” (lines 2-4). It is not clear if these two elements are the same bottom surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 6 require "a bottom of the substrate cavity” (line 2), which has been previously defined in parent claim 1 limitation of “a plurality of semiconductor chips disposed at a bottom of the substrate cavity” (3rd paragraph, line 1) It is not clear if these two elements are the same bottom surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 7, and by extension, dependent claim 8, require "a top surface of the uppermost base insulating layer” (line 2), which has been previously defined in parent claim 1 limitation of “a top solder resist layer at least partially covering a top surface of an uppermost base insulating layer” (lines 9-10). It is not clear if these two elements are the same top surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 9 require "a direction that is parallel to a plane of the package base substrate” (lines 2-3), which has been previously defined in parent claim 1 limitation of “wherein a portion of one or more of the plurality of semiconductor chips extends beyond the substrate cavity in a direction that is parallel to the plane of the package base substrate” (5th paragraph). It is not clear if these two directions are the same or a different one. For the purpose of compact prosecution, the examiner will cite the same direction for both limitations.
Claim 11, and by extension, dependent claims 12-17, recite a limitation of “a plurality of substrate wiring patterns including connection pads extending along top and bottom surfaces of each of the plurality of base insulating layers.” It is not clear whether it is just the connection pads that extend along said surfaces or if any other element of the wiring pattern extend along said surfaces. For the purpose of compact prosecution, the examiner will cite art that teaches the latter.
Claim 13 require "a bottom of the substrate cavity” (lines 4-5), which has been previously defined in parent claim 11 limitation of “a plurality of semiconductor chips stacked on a bottom of the substrate cavity” (9th paragraph, line 1). It is not clear if these two elements are the same bottom surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 14 require “wherein the plurality of upper connection pads are disposed at a level further from the package base substrate than an upper surface of the lowermost semiconductor chip among the plurality of semiconductor chips” (4th paragraph), that contradicts the requirement in parent claim 11 wherein the connection pads are part of the package base substrate (since these pads are part of the substrate wiring patterns). Due to this contradiction, the meaning of the claim is unclear and the limitation has no metes and bounds. For the purpose of compact prosecution, the examiner will cite art that teaches connection pads as part of the package base substrate.
Claim 14 require "a top surface of the uppermost base insulating layer” (3rd paragraph, lines 1-2), which has been previously defined in parent claim 11 limitation of “a top solder resist layer at least partially covering a top surface of an uppermost base insulating layer” (6th paragraph, line 1). It is not clear if these two elements are the same top surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim 18, and by extension, dependent claims 19-20, define “a top surface of the package base substrate” twice in the limitations of “a substrate cavity formed within the top solder resist layer and extending downwardly from a top surface of the package base substrate” (lines 9-10 ) and “protruding upwards over a top surface of the package base substrate” (3rd paragraph, lines 2-3). It is not clear if these two elements are the same top surface or a different one. For the purpose of compact prosecution, the examiner will cite the same element for both limitations.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 7, 11-12, 14 and 17 are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Ohba (US 2015/0235994 A1).
Regarding claim 1, Ohba teaches a semiconductor package (¶ [0002]: MCP ) comprising:
a package base substrate (201; ¶ [0037]) including a substrate cavity (111) formed therein, the substrate cavity extending from a top surface (top surface of 201) of the package base substrate downwardly toward a bottom surface (surface of 201 that is coplanar to lowermost adhesive 105; see Fig. 2-3) of the package base substrate, the package base substrate further including a plurality of base insulating layers (219a&219b), a plurality of substrate wiring patterns (123,124,223a-223d,225) including connection pads (223a, 223b,223c,223d, 225, middle 123; note: middle 123 are connection pads since these horizontal metal layers connect adjacent vias) extending along at least one of a top surface (wiring pattern found on top surfaces of 219a and 219b; see 112b rejection above) and a bottom surface (wiring pattern found on bottom surfaces of 219a and 219b; see 112b rejection above) of each of the plurality of base insulating layers (see also Fig. 5), a plurality of substrate conductive vias (124) passing through at least one of the plurality of base insulating layers and connected to the plurality of substrate wiring patterns (see ¶ [0040]), and a top solder resist layer (topmost 221; see ¶ [0040] ) at least partially covering a top surface (top surface of 219a) of an uppermost base insulating layer (219a) among the plurality of base insulating layers and a bottom solder resist layer (bottommost 221) at least partially covering a bottom surface (bottom surface of 219b) of a lowermost base insulating layer (219b) among the plurality of base insulating layers;
a plurality of semiconductor chips (203, 205) disposed at a bottom (bottom surface of 111) of the substrate cavity, wherein the plurality of semiconductor chips are stacked in a direction (vertical direction in Figs. 2-3 ) that is perpendicular to a plane (horizontal plane of Figs. 2-3) of the package substrate and protrudes upwards above a top surface (Fig. 2 shows chip stack 203 &205 extends above the top surface of package base substrate 201) of the package base substrate; and
a plurality of bonding wires (215, 217) electrically connecting the plurality of semiconductor chips to the package base substrate (Fig. 2, ¶ [0037]: 217 connects 205 to substrate 201; Fig. 3, ¶ [0045]: 215 connects 203 to substrate 201),
wherein a portion of one or more of the plurality of semiconductor chips extends beyond the substrate cavity in a direction (horizontal direction in Figs. 2-3) that is parallel to the plane of the package base substrate (Fig. 2 shows 205 extending horizontally beyond the width of the cavity 111).
Regarding claim 2, the semiconductor package of claim 1, wherein the connection pads include a plurality of lower connection pads (225 in Figs. 2-3) disposed adjacent to a bottom surface (bottom surface of 201) of the package base substrate, and a plurality of upper connection pads (223a-223d and middle 123 in Figs. 2-3) disposed adjacent to the top surface (topmost surface of 201) of the package base substrate, and wherein one or more of the plurality of upper connection pads (223a-223d) are connected to the plurality of bonding wires (217, 215).
Regarding claim 3, the semiconductor package of claim 2, wherein the substrate cavity penetrates through the top solder resist layer (Figs. 2-3 show 111 penetrating through topmost 221) and extends into the plurality of base insulating layers (111 extends all the way to the level of the bottommost insulating layer 219b).
Regarding claim 5, the semiconductor package of claim 3, wherein the substrate cavity penetrates through the top solder resist layer (Figs. 2-3 show cavity 111 penetrating through topmost 221) and through at least one base insulating layer from the uppermost base insulating layer among the plurality of base insulating layers (said figures show cavity 111 penetrating through 219a).
Regarding claim 7, the semiconductor package of claim 3, wherein the plurality of upper connection pads (223a, 223b, 223c, 223d) are disposed on a top surface (top surface of 219a) of the uppermost base insulating layer (219a) among the plurality of base insulating layers.
Regarding claim 11, Ohba teaches a semiconductor package (¶ [0002]: MCP) comprising:
a package base substrate (201; ¶ [0037]), including: a plurality of base insulating layers (219a & 219b);
a plurality of substrate wiring patterns (123,124,223a-223d,225) including connection pads (223a, 223b, 223c, 223d, 225; middle 123; note: middle 123 are also connection pads since they are flat metal wiring that connect underlying vias) extending along top (top surfaces of 219a and 219b) and bottom surfaces (bottom surfaces of 219a and 219b) of each of the plurality of base insulating layers (see also Fig. 5);
a plurality of substrate conductive vias (124) passing through at least one of the plurality of base insulating layers and connected to the plurality of substrate wiring patterns (see ¶ [0040]);
a top solder resist layer (topmost 221) at least partially covering a top surface (top surface of 219a) of an uppermost base insulating layer (219a) among the plurality of base insulating layers;
a bottom solder resist layer (bottommost 221) at least partially covering a bottom surface (bottom surface of 219b) of a lowermost base insulating layer (219b) among the plurality of base insulating layers; and
a substrate cavity (111; see Fig. 1) formed within the plurality of base insulating layers and passing through the top solder resist layer;
a plurality of semiconductor chips (203 & 205) stacked on a bottom (bottom of 111) of the substrate cavity, wherein a lower portion (203) of the plurality of semiconductor chips is disposed within the substrate cavity and wherein an upper portion (205) of the plurality of semiconductor chips is disposed outside the substrate cavity; and
a plurality of bonding wires (215, 217) for connecting the plurality of semiconductor chips to the package base substrate (Fig. 2, ¶ [0037]: 217 connects 205 to substrate 201; Fig. 3, ¶ [0045]: 215 connects 203 to substrate 201 ).
Regarding claim 12, the semiconductor package of claim 11, wherein the substrate cavity (111; see Fig. 1) passes through the top solder resist layer (topmost 221; Fig. 2-3) and passes through at least one base insulating layer (219b) from the uppermost base insulating layer among the plurality of base insulating layers.
Regarding claim 14, the semiconductor package of claim 12, wherein the plurality of semiconductor chips includes a plurality of chip pads (107a, 107b, 103a, 103b) connected to one end of the plurality of bonding wires,
wherein the connection pads include a plurality of upper connection pads (223a, 223b, 223c, 223d) connected to the other end of the plurality of bonding wires,
wherein the plurality of upper connection pads are positioned on a top surface (top surface of 219a) of the uppermost base insulating layer (219a) among the plurality of base insulating layers, and
wherein the plurality of upper connection pads are disposed at a level further from the package base substrate than an upper surface of the lowermost semiconductor chip among the plurality of semiconductor chips (pads 223a-223d are part of base package substrate 201; also see 112b rejection above).
Regarding claim 17, the semiconductor package of claim 11, wherein a portion (205) of one or more of the plurality of semiconductor chips extends beyond the substrate cavity in a direction (horizontal direction of Fig. 2) that is parallel to a plane (horizontal plane of Fig. 2) of the package base substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4, 6, 13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ohba (US 2015/0235994 A1) as applied to claims 1 and/or 12 above, and further in view of Tamaki (US 2006/0027841 A1).
Regarding claim 4, Ohba teaches the semiconductor package of claim 3, but does not teach: wherein the package base substrate further includes a pad trench distinct from the substrate cavity, the pad trench being disposed within the substrate cavity and extending downwardly toward a bottom surface of the package base substrate from the bottom of the substrate cavity, and wherein the plurality of upper connection pads are positioned on a bottom of the pad trench.
Tamaki, in the same field of invention, teaches a device (see Fig. 33) wherein the package base substrate (30) further includes a pad trench (cavities of layer 121 that is filled with pads 6) distinct from the substrate cavity (cavity of substrate 30 that is occupied by semiconductor devices 1 and 2), the pad trench being disposed within the substrate cavity (this is shown in Fig. 33) and extending downwardly toward a bottom surface (bottom surface of 30) of the package base substrate from the bottom of the substrate cavity (upper surface of 121 is the bottom of the cavity), and
wherein the plurality of upper connection pads are positioned on a bottom (bottom of each cavity of layer 121) of the pad trench.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tamaki into the device of Ohba to add at least one pad trench inside the cavity of the package substrate, with the plurality of upper connection pads positioned on a bottom surface of the pad trench. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of connecting the lowest of the plurality of semiconductor chips directly to the package substrate using the pads that are disposed in the pad trenches (Tamaki ¶ [0164]-[0165]) for the further purpose of avoiding shorts in the package (¶ [0194] ), thus increasing the reliability of the device.
Regarding claim 6, Ohba teaches the semiconductor package of claim 3, and further teaches a plurality of upper connection pads (middle 123) at a level that is coplanar to the bottom of the substrate cavity (111; see Figs. 2-3). However, Ohba does not teach: wherein the plurality of upper connection pads are disposed on a bottom of the substrate cavity.
Tamaki, in the same field of invention, teaches a device (Fig. 33) wherein the plurality of upper connection pads (6 are upper pads, as contrasted to 12 which are lower pads) are disposed on a bottom (bottom surface) of the substrate cavity (cavity of substrate 30 that is occupied by semiconductor devices 1 and 2).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tamaki into the device of Ohba to add upper connection pads that are disposed on a bottom surface of the substrate cavity. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of connecting the lowest of the plurality of semiconductor chips directly to the package substrate using the pads that are disposed in the pad trenches (Tamaki ¶ [0164]-[0165]) for the further purpose of avoiding shorts in the package (¶ [0194] ), thus increasing the reliability of the device.
Regarding claim 13, Ohba teaches the semiconductor package of claim 12, wherein the connection pads include a plurality of upper connection pads (223a, 223b, 223c, 223d) connected to the plurality of bonding wires (215, 217). However, Ohba does not teach: wherein the plurality of upper connection pads are is disposed on a bottom of the substrate cavity.
Tamaki, in the same field of invention, teaches a device (Fig. 33) wherein the plurality of upper connection pads (6; see Fig. 33) are is disposed on a bottom (bottom surface of cavity 15) of the substrate cavity (15 is a cavity of substrate 30).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tamaki into the device of Ohba to add a plurality of upper connection pads on a bottom surface of the cavity of the package substrate. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of using the upper connection pads to connect the bonding wires directly to the wiring pattern of the lowermost base insulating level of the package substrate (Tamaki ¶ [0164]-[0165]) for the further purpose of avoiding shorts in the package (¶ [0194]), thus increasing the reliability of the device.
Regarding claim 15, Ohba teaches the semiconductor package of claim 11, wherein the substrate cavity (111, see Fig. 1) passes through the top solder resist layer (Fig. 2-3 shows cavity 111 passes through uppermost 221) and passes through an upper portion (upper portion of 219) of the uppermost base insulating layer (219a, which is the uppermost 219) among the plurality of base insulating layers. However, Ohba does not teach: without extending to a bottom surface of the uppermost base insulating layer.
Tamaki, in the same field of invention, teaches a device (see Fig. 33) wherein the substrate cavity (15 is a cavity of substrate 30) does not extend to a bottom surface (bottom surface of 31&121) of the uppermost base insulating layer (31&121 constitute the uppermost base insulating layer).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tamaki into the device of Ohba to not extend the cavity to a bottom surface of the uppermost base insulating layer. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of adding connecting pads on the a surface of a lowermost base insulating layer (121) of the package substrate for the further purpose of connecting the bonding wires directly to the wiring pattern of the lowermost insulating layer of the package substrate (Tamaki ¶ [0164]-[0165]) and for the further purpose of avoiding shorts in the package (¶ [0194]), thus increasing the reliability of the device.
Regarding claim 16, Ohba teaches the semiconductor package of claim 15, wherein the connection pads include a plurality of upper connection pads (223a-223d; see Figs. 2-3) connected to the plurality of bonding wires (215, 217). However, Obha does not teach: wherein the package base substrate further includes a pad trench distinct from the substrate cavity, the pad trench being disposed beneath and in communication with the substrate cavity and extending toward a bottom of the package base substrate from the bottom of the substrate cavity, and passing through at least one base insulating layer from the uppermost base insulating layer among the plurality of base insulating layers, and wherein the plurality of upper connection pads are positioned on a bottom of the pad trench.
Tamaki, in the same field of invention, teaches a device (Fig. 33) wherein the package base substrate further includes a pad trench (trenches within layer 121 occupied by pads 6) distinct from the substrate cavity (cavity of 30 occupied by devices 1 & 2), the pad trench being disposed beneath and in communication with the substrate cavity (see Fig. 33) and extending toward a bottom (bottom of 30) of the package base substrate (30) from the bottom (bottom surface of abovementioned cavity) of the substrate cavity, and passing through at least one base insulating layer (121) from the uppermost base insulating layer (121&31) among the plurality of base insulating layers (all dielectric layers of 30), and wherein the plurality of upper connection pads (6) are positioned on a bottom (bottom surface of abovementioned trench) of the pad trench.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Tamaki into the device of Ohba to add a pad trench in the manner described above. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of connecting the plurality of bonding wires directly to the wiring pattern of the lowermost base insulating layer (121) of the package substrate (Tamaki ¶ [0164]-[0165]) for the further purpose of avoiding shorts in the package (¶ [0194] ), thus increasing the reliability of the device.
Claims 8, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ohba (US 2015/0235994 A1) as applied to claim 1 above, and in further view of Jensen (US 2011/0180919 A1).
Regarding claim 8, Ohba teaches the semiconductor package of claim 7, wherein the plurality of semiconductor chips each include a plurality of chip pads (107a, 107b, 103a, 103b) connected to the plurality of bonding wires. However, Obha does not teach: wherein the plurality of chip pads of a lowermost semiconductor chip among the plurality of semiconductor chips are disposed at a level closer to the package base substrate than a level at which the plurality of upper connection pads are disposed.
Jensen, in the same field of invention, teaches a device (Fig. 5B) wherein the plurality of chip pads (lowermost chip pad 98) of a lowermost semiconductor chip (lowermost chip 94) among the plurality of semiconductor chips are disposed at a level (lower level) closer to the package base substrate (bottom surface of 26) than a level (higher level) at which the plurality of upper connection pads (other chip pads 98) are disposed.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jensen into the device of Ohba to set the connection pads of the lowermost semiconductor chip at a lower level compared to the connection pads of the other chips. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of stacking chips having different sizes vertically (Jensen ¶ [0067]) in a sequence of steps in order to create vertical separation between wires (99) that may create shorts (¶ [0068] ), thereby improving the reliability of the device.
Regarding claim 9, Obha teaches the semiconductor package of claim 1, wherein each of the plurality of semiconductor chips are offset (vertical edges of 203 and 205 are offset from each other ) from one another in a direction (horizontal direction) that is parallel to a plane (horizontal plane in Figs. 2-3) of the package base substrate. However, Ohba does not teach the plurality of semiconductor chips to collectively form a sequence of steps.
Jensen, in the same field of invention, teaches a device (Fig. 5B) wherein the plurality of semiconductor chips (94) collectively form a sequence of steps (see Fig. 5B).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jensen into the device of Ohba to stack the semiconductor chips in a form of a sequence of steps. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of stacking chips having different sizes vertically (Jensen ¶ [0067]) in a sequence of steps in order to create vertical separation between wires (99) that may create shorts (¶ [0068] ), thereby improving the reliability of the device.
Regarding claim 10, Ohba teaches the semiconductor package of claim 1, but does not teach: wherein at least a portion of the plurality of bonding wires is positioned within the substrate cavity.
Jensen, in the same field of invention, teaches a package (Fig. 5B) wherein at least a portion of the plurality of bonding wires (99) is positioned within the substrate cavity (cavity of 27 that is occupied by dies 94).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Jensen into the device of Ohba to set the plurality of bonding wires within the substrate cavity. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of stacking chips having different sizes vertically (Jensen ¶ [0067]) in a sequence of steps in order to create vertical separation between wires (99) that may create shorts (¶ [0068] ), thereby improving the reliability of the device.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ohba (US 2015/0235994 A1) in view of Huang (US 2022/0367334 A1).
Regarding claim 18, Ohba teaches a semiconductor package (¶ [0002] : MCP) comprising:
a package base substrate (201; ¶ [0037]) including a plurality of base insulating layers (219a & 219b), a plurality of substrate wiring patterns (123 & 124) extending along at least one of a top surface (top surfaces of 219a & 219b) and a bottom surface (bottom surfaces of 219a & 219b) of each of the plurality of base insulating layers, a plurality of substrate conductive vias (124) passing through at least one of the plurality of base insulating layers and connected to the plurality of substrate wiring patterns (¶ [0040]), a top solder resist layer (topmost 221) at least partially covering a top surface (top surface of 219a) of an uppermost base insulating layer (219a) among the plurality of base insulating layers, a bottom solder resist layer (bottommost 221) at least partially covering a bottom surface (bottom surface of 219b) of a lowermost base insulating layer (219b) among the plurality of base insulating layers, and a substrate cavity (111; see Fig. 1) formed within the top solder resist layer and extending downwardly from a top surface (top surface of 201) of the package base substrate toward an inside (cavity 111 is in the middle of 201) of the package base substrate;
a plurality of semiconductor chips (203 & 205) stacked on a bottom (bottom of 111) of the substrate cavity in a direction perpendicular (vertical direction of Figs. 2-3 ) to a plane (horizontal plane of Figs. 2-3) of the package base substrate, and protruding upwards over a top surface (205 is above the top surface of 201) of the package base substrate;
a plurality of bonding wires (215, 217) connecting the plurality of semiconductor chips to the package base substrate (Fig. 2, ¶ [0037]: 217 connects 205 to substrate 201; Fig. 3, ¶ [0045]: 215 connects 203 to substrate 201 ); and
a mold layer (220) covering the top surface of the package base substrate and filling the substrate cavity, wherein the mold layer covers the plurality of semiconductor chips and the plurality of bonding wires (Figs. 2-3 show 220 covering 203&205, 215, and 217).
However, Obha does not teach: wherein the substrate cavity is defined by a solder protrusion of the top solder resist layer, wherein the solder protrusion corresponds to a thickened region of the top solder resist layer, wherein a portion of the top solder resist layer including the solder protrusion has the greatest thickness within the top solder resist layer, and wherein a thickness of the thickest portion of the top solder resist layer is greater than a thickness of the thickest portion of the bottom solder resist layer.
Huang, in the same field of invention, teaches a device wherein the substrate cavity (cavity of the lower structure in Fig. 1C wherein die is set) is defined by a solder protrusion (stepped protrusion of SM10 from the top surface of BP) of the top solder resist layer (SM10), wherein the solder protrusion corresponds to a thickened region (regions having height T10-2, T10-1, and T10A-1) of the top solder resist layer, wherein a portion (portion having height T10-2) of the top solder resist layer including the solder protrusion has the greatest thickness within the top solder resist layer, and wherein a thickness (T10-2 is 35 microns; see Table 1 under ¶ [0062] ) of the thickest portion of the top solder resist layer is greater than a thickness (height of SMB in Fig. 1A is 20 microns; see Table 1 under ¶ [0062] ) of the thickest portion of the bottom solder resist layer (SMB).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the device of Ohba to add a solder protrusion to the top solder resist layer in the manner described above. The ordinary artisan would have been motivated to modify Ohba in the manner set forth above for at least the purpose of eliminating the need of a solder-on-pad process which requires solder bumps to be formed on a bump pad, thus simplifying the process, improving the yield, and thereby reducing the cost of manufacturing the device (Huang ¶ [0035] ).
Regarding claim 19, the semiconductor package of claim 18, wherein at least one side surface of the solder protrusion has a stepped thickness profile (step profile of SM10; see Huang Fig. 1C).
Regarding claim 20, the semiconductor package of claim 18, wherein the solder protrusion includes a first solder protrusion (left protrusion of SM10 in Huang Fig. 1C) and a second solder protrusion (right protrusion of SM10) separated from each other, and
wherein a shape (shape of the left protrusion) of the first solder protrusion and a shape (shape of the right protrusion) of the second solder protrusion are asymmetric based on different lateral extents or thickness profiles when viewed in a direction (direction into the page of Fig. 1C) that is parallel to a plane (horizontal plane of Fig. 1C) of the package base substrate across a center (said horizontal plane cuts through the center of package as shown in Fig. 1A) of the package base substrate.
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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