DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-15 in the reply filed on 10/14/2025 is acknowledged. The traversal is on the grounds that an examination can be made without serious burden. This is not agreed upon because the two inventions listed are independent and distinct and there would be a serious search and examination burden if restriction were not required in view of the following: (a) the inventions have acquired a separate status in the art in view of their different classification; and (b) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries).
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation “the molding layer having outer walls coplanar with sidewalls of the first chip structure” in lines 12-13. The limitation is ambiguous as the outer walls of the molding layer 114 is coplanar with sidewalls of the second semiconductor chip structure 20 and not the first chip structure 30 (See Fig. 3). Correction/clarification is required.
Claims 11-15 are rejected for being dependent on claim 10.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 7 & 9 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Lim (US Patent 9,673,183).
Regarding claim 1, Lim teaches a semiconductor package comprising:
a first semiconductor chip (112 or 110) including a first surface (116 or 114) and a second surface (130 or 128) that are opposite to each other (Fig. 8);
connection terminals 120 on the first surface of the first semiconductor chip 120 (Fig. 8);
a first dielectric layer 132 on the second surface 130 of the first semiconductor chip 112 (Fig. 8);
a second semiconductor chip (memory die 1) on the first dielectric layer 132 and including a third surface (bottom surface of memory die 1) opposite to the second surface and a fourth surface (top surface of memory die 1) opposite to the third surface (Fig. 8);
a second dielectric layer (column 7 line 24-26) on the third surface of the second semiconductor chip (memory die 1) and in contact with the first dielectric layer (see Fig. 8 below);
a third semiconductor chip (memory die 2) on the fourth surface of the second semiconductor chip (memory die 1, see Fig. 8); and
a first adhesive layer between the second semiconductor chip (memory die 1) and the third semiconductor chip (memory die 2, column 7, line 24-26 and see Fig. 8 below),
the first dielectric layer 132 and the second dielectric layer including no wirings (there is no wiring in the first dielectric layer and the second dielectric layer (Fig. 8).
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Regarding claim 2, Lim teaches the semiconductor package of claim 1, wherein the first surface 116 of the first semiconductor chip 112 is an active surface of the first semiconductor chip 112, the fourth surface of the second semiconductor chip (memory die 1) is an active surface of the second semiconductor chip (note the chip pad and wire bond connection on memory die 1 that illustrates an active surface), and the third semiconductor chip (memory die 2) has an active surface opposite to the first adhesive layer on the third semiconductor chip (note the chip pad and wire bond on memory die 2 that illustrates an active surface, see Fig. 8).
Regarding claim 5, Lim teaches the semiconductor package of claim 1, wherein the first semiconductor chip 112 is smaller in width than the second semiconductor chip (memory die 1, see Fig. 8).
Regarding claim 7, Lim teaches the semiconductor package of claim 1, further comprising: a plurality of semiconductor chips (e.g. memory die 3- memory die 8) on the third semiconductor chip (memory die 2) and attached by a second adhesive layer (note unlabeled adhesive layers between the memory dies), wherein the second semiconductor chip, the third semiconductor chip, and the plurality of semiconductor chips form a terraced stack (see Fig. 8).
Regarding claim 9, Lim teaches the semiconductor package of claim 1, further comprising: a substrate 124; and a wire 176 configured to connect the second semiconductor chip and the third semiconductor chip with the substrate 124, wherein the first semiconductor chip 112 is on the substrate, and the connection terminals 120 are between the first semiconductor chip 112 and the substrate 124 (Fig. 8).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 & 8 are rejected under 35 U.S.C. 103 as being unpatentable over Lim as applied to claim 1 above, and in further view of Mao (US Pub. 2019/0035705).
Regarding claim 6, Lim is silent on the semiconductor package of claim 1, wherein the second semiconductor chip is smaller in thickness than the third semiconductor chip. However, Mao teaches in Para [0025] and Fig. 1A-1B a multi-stack memory dies wherein the semiconductor chips in the chip stacks can be of different sizes (for instance a second semiconductor chip within a stack can be smaller in thickness than a third semiconductor chip within the stack). This has the advantage of providing semiconductor chips of different memory capacities. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lim with the semiconductor dies/chips of varying thickness, as taught by Mao, so as to provide memory dies/chips of varying memory/storage capacity.
Regarding claim 8, Lim is silent on the semiconductor package of claim 7, wherein a first plurality of semiconductor chips among the second semiconductor chip, the third semiconductor chip, and the plurality of semiconductor chips, form ascending stepped stacks in a first direction adjacent to the third semiconductor chip, while a second plurality of semiconductor chips not included in the first plurality of semiconductor chips form descending stepped stacks in the first direction. However, MAO teaches wherein a first plurality of semiconductor chips among the second semiconductor chip, the third semiconductor chip, and the plurality of semiconductor chips, form ascending stepped stacks in a first direction adjacent to the third semiconductor chip, while a second plurality of semiconductor chips not included in the first plurality of semiconductor chips form descending stepped stacks in the first direction (Fig. 1A or Fig. 1B). This has the advantage of including additional memory dies to optimize further miniaturization and increase storage capacity. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lim with chip die stacks in ascending and descending step shape, as taught by Mao, so as to form device features as small as possible with large enough thickness to allow proper device operation, in order to save on material and processing costs and allow for increased storage/memory capacity.
Allowable Subject Matter
Claims 10-15 are allowable pending resolution of 112 issues.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 10, the prior art of record fails to teach or suggest, a semiconductor package, comprising: a first chip structure including a first semiconductor chip and a first dielectric layer on the first semiconductor chip, the first chip structure having a first width; a second chip structure including a second semiconductor chip and a second dielectric layer on the second semiconductor chip, the second chip structure having a second width greater than the first width; and a molding layer on the second chip structure and surrounding the first chip structure, the first dielectric layer being in contact with the second dielectric layer, and the molding layer having outer walls coplanar with sidewalls of the first chip structure.
Claims 11-15 are allowed as being directly or indirectly dependent of the allowed independent base claim 10.
Claims 3-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818