DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 08/25/2026.
Currently claims 1-16 and 21-24 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Group II (claims 9–16), in the reply filed 08/25/2026, is acknowledged. The new claims 21-24 are accepted for prosecution. Claims 9–16 and 21–24 are examined on the merits herein.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/27/2023 and 11/20/2024 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 15 is rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 15, the instant claim recites that “the first control line and the fourth control line are substantially perpendicular to the first opening.” An “opening” is a three-dimensional void; the claim does not identify the reference feature or direction of the opening (e.g., its axis of elongation, its sidewall, or its depth direction) against which perpendicularity is to be measured. The metes and bounds of “substantially perpendicular to the first opening” are therefore unclear. Clarification/correction is required. For purposes of examination, the limitation is interpreted as requiring the first and fourth control lines to extend in directions substantially perpendicular to the direction in which the first opening extends toward the substrate.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0227416 A1 (Lilak) and further in view of US 2009/0116270 A1 (Scheuerlein).
Regarding claim 9, Lilak discloses, an integrated circuit (IC) device, comprising:
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an insulator material (306; insulator layer) over a substrate (301) (Fig. 3A; [0049]);
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a first opening (635, left, as annotated on Fig. 6A; [0055]) extending through the insulator material (306/606) towards the substrate (301) and having a first channel material (675) on sidewalls of the first opening (635, left);
a second opening (635, right, as annotated on Fig. 6A; [0055]) extending through the insulator material (306/606) towards the substrate (301) and having a second channel material (675) on sidewalls of the second opening (635, right);
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a first transistor (170/150, bottom, as annotated on Fig. 1A; [0033]) having a channel region (175) in a first portion of the first channel material (675);
a second transistor (170/150, top, as annotated on Fig. 1A; [0033]) having a channel region (175) in a second portion of the first channel material (675), the second portion being further away from the substrate than the first portion (as evident in Fig. 1A); and
a third transistor (in the second opening with a similar transistor 170/150, bottom, as annotated on Fig. 1A; [0033]) having a channel region in a portion of the second channel material (675),
wherein a first source or drain (S/D) region of the first transistor is coupled to a first control line, a first S/D region of the second transistor is coupled to a second control line, a first S/D region of the third transistor is coupled to a third control line (bit lines 605, each layer of the stack having its own bit line illustrated as a staircase of stacked bit lines; [0056]);
a second S/D region of the first transistor, a second S/D region of the second transistor and a second S/D region of the third transistor are coupled to another control line (668; capacitor electrode; Lilak couples the second end of each channel to a per-cell capacitor electrode; Fig. 6D; [0059]).
But Lilak fails to teach explicitly, a single, common fourth control line coupled to the second S/D region of each transistor.
However, in analogous art, Scheuerlein discloses, a capacitorless one-transistor memory array in which a common line (202; common bit line; Scheuerlein Fig. 3; [0052]) is coupled to a source/drain region shared by a plurality of memory cells.
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Note: To the extent Lilak forms the channel regions of the vertically-stacked first and second transistors as discrete per-layer segments rather than “a first portion” and “a second portion” of one continuous “first channel material,” forming those channel regions as continuous portions of a single sidewall channel film lining the opening is a matter of obvious fabrication/design choice that yields the predictable result of a shared vertical channel gated by the common word line (MPEP 2144.04).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lilak and Scheuerlein before him/her, to modify the teachings of a 3D stacked memory device as taught by Lilak and to include the teachings of a common line coupled to a source/drain region shared by a plurality of memory cells as taught by Scheuerlein since (1) coupling the second S/D regions of the stacked transistors to a single common control line and adopting capacitorless floating-body storage reduces cell area and process complexity by eliminating the per-cell capacitor while increasing memory density; (2) since the modification amounts to a simple substitution of Scheuerlein's known capacitorless common-line one-transistor cell for Lilak's one-transistor-one-capacitor cell (MPEP 2144.06); and (3) with a reasonable expectation of success, yielding the predictable result of a denser three-dimensional stacked-transistor memory array. Absent this teaching in Lilak, a person with ordinary skill in the art would be motivated to reach out to Scheuerlein while forming the 3D stacked memory device of Lilak.
Regarding claim 10, Lilak discloses, the IC device according to claim 9, wherein at least a portion of the first opening includes a first conductive material, at least a portion of the second opening includes a second conductive material, the first conductive material is a part of a gate stack of the first transistor and a part of a gate stack of the second transistor, and the second conductive material is a part of a gate stack of the third transistor. Here Lilak teaches word line disposed in each first trench and serving as the gate electrode for the plurality of vertically-stacked memory cells of that trench (615/715; word line; Figs. 6E, 7; [0060] – [0061]), together with the gate dielectric (677; gate dielectric; Fig. 6D; [0060]).
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Regarding claim 11, the combination of Lilak and Scheuerlein teaches, the IC device according to claim 10, wherein the first conductive material in the first opening is a fifth control line, and the second conductive material in the second opening is a sixth control line (Lilak’s word lines 615 serving as individual control (gate) lines; Fig. 6E; [0060]).
Regarding claim 12, the combination of Lilak and Scheuerlein teaches, the IC device according to claim 11, wherein the fifth control line and the sixth control line are substantially perpendicular to the substrate (Lilak’s word lines 715 extending vertically through the stack, perpendicular to the substrate, to gate the vertically-stacked cells; Fig. 7; [0061]).
Regarding claim 13, the combination of Lilak and Scheuerlein teaches, the IC device according to claim 9, wherein the first control line, the second control line, and the third control line are substantially parallel to one another and substantially parallel to the substrate (Lilak's per-layer bit lines 605, each extending horizontally within its layer parallel to the substrate; Fig. 6; [0056]).
Regarding claim 14, the combination of Lilak and Scheuerlein teaches, the IC device according to claim 13, wherein the fourth control line is substantially perpendicular to the first control line and substantially parallel to the substrate (the common line of Scheuerlein arranged transverse to the bit lines and parallel to the substrate; (202; common bit line; Scheuerlein Fig. 3; [0052]), (605; bit line; Lilak Fig. 6; [0056])).
Regarding claim 15, (as interpreted above under § 112(b)), the combination of Lilak and Scheuerlein teaches, the IC device according to claim 9, wherein the first control line and the fourth control line are substantially perpendicular to the first opening and substantially perpendicular to one another (Lilak's bit line and the common line of Scheuerlein extending transverse to the direction the trench/opening extends and transverse to one another (605; bit line; Lilak Fig. 6; [0056]), (202; common bit line; Scheuerlein Fig. 3; [0052]), (635; first trench; Lilak Fig. 6A; [0055])).
Regarding claim 16, the combination of Lilak and Scheuerlein teaches, the IC device according to claim 9, wherein the first transistor is a first floating body memory cell, the second transistor is a second floating body memory cell, and the third transistor is a third floating body memory cell (Scheuerlein's capacitorless one-transistor cell that stores charge in a floating body residing in the transistor channel region (122; floating body; Scheuerlein Fig. 1; [0038]), (121; channel region; Scheuerlein Fig. 1; [0038])).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lilak and Scheuerlein before him/her, to modify the teachings of a 3D stacked memory device as taught by Lilak and to include the teachings of a common line coupled to a source/drain region shared by a plurality of memory cells as taught by Scheuerlein because (1) storing the memory state in the floating body of the transistor eliminates the separate storage capacitor of Lilak, reducing area and process complexity; (2) since the modification amounts to a simple substitution of Scheuerlein's known floating-body one-transistor memory cell for the one-transistor-one-capacitor cell of Lilak (MPEP 2144.06); and (3) with a reasonable expectation of success, yielding the predictable result of a capacitorless three-dimensional floating-body memory. Absent this teaching in Lilak, a person with ordinary skill in the art would be motivated to reach out to Scheuerlein while forming the 3D stacked memory device of Lilak.
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0227416 A1 (Lilak) and further in view of US 2009/0116270 A1 (Scheuerlein).
Regarding claim 21, Lilak discloses, an integrated circuit (IC) package (package of computing device 1100; Fig. 11; [0070] – [0076]), comprising:
an IC die (a die that includes IC device 300/600), comprising an IC device (300/600; Fig. 3A/6A); and
a further component (the substrate is a device layer / BEOL metal layer of a semiconductor die; [0033], [0048] and/or computing device 1100 has several components which are often individual ICs; Fig. 11; [0070] – [0076]), coupled to the IC die (300/600),
wherein the IC device (300/600) includes:
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an insulator material (306) over a substrate (301) (Fig. 3A; [0049]);
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a first opening (635, left, as annotated on Fig. 6A; [0055]) extending through the insulator material (306/606) towards the substrate (301) and having a first channel material (675) on sidewalls of the first opening (635, left);
a second opening (635, right, as annotated on Fig. 6A; [0055]) extending through the insulator material (306/606) towards the substrate (301) and having a second channel material (675) on sidewalls of the second opening (635, right);
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a first transistor (170/150, bottom, as annotated on Fig. 1A; [0033]) having a channel region (175) in a first portion of the first channel material (675);
a second transistor (170/150, top, as annotated on Fig. 1A; [0033]) having a channel region (175) in a second portion of the first channel material (675), the second portion being further away from the substrate than the first portion (as evident in Fig. 1A); and
a third transistor (in the second opening with a similar transistor 170/150, bottom, as annotated on Fig. 1A; [0033]) having a channel region in a portion of the second channel material (675),
wherein a first source or drain (S/D) region of the first transistor is coupled to a first control line, a first S/D region of the second transistor is coupled to a second control line, a first S/D region of the third transistor is coupled to a third control line (bit lines 605, each layer of the stack having its own bit line illustrated as a staircase of stacked bit lines; [0056]);
a second S/D region of the first transistor, a second S/D region of the second transistor and a second S/D region of the third transistor are coupled to another control line (668; capacitor electrode; Lilak couples the second end of each channel to a per-cell capacitor electrode; Fig. 6D; [0059]).
But Lilak fails to teach explicitly, a single, common fourth control line coupled to the second S/D region of each transistor.
However, in analogous art, Scheuerlein discloses, a capacitorless one-transistor memory array in which a common line (202; common bit line; Scheuerlein Fig. 3; [0052]) is coupled to a source/drain region shared by a plurality of memory cells.
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Note: To the extent Lilak forms the channel regions of the vertically-stacked first and second transistors as discrete per-layer segments rather than “a first portion” and “a second portion” of one continuous “first channel material,” forming those channel regions as continuous portions of a single sidewall channel film lining the opening is a matter of obvious fabrication/design choice that yields the predictable result of a shared vertical channel gated by the common word line (MPEP 2144.04).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lilak and Scheuerlein before him/her, to modify the teachings of a 3D stacked memory device as taught by Lilak and to include the teachings of a common line coupled to a source/drain region shared by a plurality of memory cells as taught by Scheuerlein since (1) coupling the second S/D regions of the stacked transistors to a single common control line and adopting capacitorless floating-body storage reduces cell area and process complexity by eliminating the per-cell capacitor while increasing memory density; (2) since the modification amounts to a simple substitution of Scheuerlein's known capacitorless common-line one-transistor cell for Lilak's one-transistor-one-capacitor cell (MPEP 2144.06); and (3) with a reasonable expectation of success, yielding the predictable result of a denser three-dimensional stacked-transistor memory array. Absent this teaching in Lilak, a person with ordinary skill in the art would be motivated to reach out to Scheuerlein while forming the 3D stacked memory device of Lilak.
Regarding claim 22, the combination of Lilak and Scheuerlein teaches, the IC package according to claim 21, wherein the further component is one of a package substrate, an interposer, or a further IC die (IC package that houses computing device 1100 has several components which are often individual ICs; Fig. 11; [0070] – [0076]).
Regarding claim 23, the combination of Lilak and Scheuerlein teaches, the IC package according to claim 21, wherein at least a portion of the first opening includes a first conductive material, at least a portion of the second opening includes a second conductive material, the first conductive material is a part of a gate stack of the first transistor and a part of a gate stack of the second transistor, and the second conductive material is a part of a gate stack of the third transistor. Here Lilak teaches word line disposed in each first trench and serving as the gate electrode for the plurality of vertically-stacked memory cells of that trench (615/715; word line; Figs. 6E, 7; [0060] – [0061]), together with the gate dielectric (677; gate dielectric; Fig. 6D; [0060]).
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Regarding claim 24, the combination of Lilak and Scheuerlein teaches, the IC package according to claim 21, wherein the first control line, the second control line, and the third control line are substantially parallel to one another and substantially parallel to the substrate (Lilak's per-layer bit lines 605, each extending horizontally within its layer parallel to the substrate; Fig. 6; [0056]).
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
1. US 2020/0194443 A1 (Chen) – A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.
2. US 2019/0189357 A1 (Chavan) – 3D DRAM capacitor structures with leaker devices in openings; pertinent to opening/container fabrication.
3. US 2022/0231030 A1 (Chiang) – A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
09/16/2026
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