DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-7, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20180301459 A1, hereinafter Kim)
With regards to claim 1, Kim discloses an integrated circuit device (FIGS. 7A-15E) comprising:
a substrate (substrate 100) that has a first active region (active region ACT under 112a) and a second active region (active region ACT under 112b) spaced apart from the first active region; (see FIG. 15E)
a device isolation layer (isolation layer 102) between the first active region and the second active region;
a direct contact (direct contact DC) electrically connected to the first active region in a direct contact opening that extends through portions of the first active region and the device isolation layer; (See FIG. 15E, showing the extension)
a plurality of cell patterns (cell patterns comprising regions 112a and 112b) that have a pillar shape and extend from a lower surface of the direct contact opening on the second active region; (see FIG. 15E, showing the extension) and
a buried contact plug (buried contact BC) that extends through portions of the plurality of cell patterns and is electrically connected to the second active region, (see FIG. 15E)
wherein the plurality of cell patterns comprise:
a plurality of first cell groups (groups of left regions 112b, see FIGS. 7 and 15E) that are arranged along a first horizontal direction and each comprise a plurality of first cell patterns (left regions 112b, see FIG. 15E) arranged in a row along a second horizontal direction perpendicular to the first horizontal direction; and
a plurality of second cell groups (groups of right regions 112b, see FIGS. 7 and 15E) that are spaced apart from the plurality of first cell groups, are arranged along the first horizontal direction, and each comprise a plurality of second cell patterns (left regions 112b, see FIG. 15E) arranged in a row along the second horizontal direction, and
wherein respective side surfaces of the plurality of second cell patterns have respective concave portions that are recessed inward along respective side surfaces of the plurality of first cell patterns that are adjacent to respective ones of the plurality of second cell patterns. (see FIG. 15E, where the right region 112b is recessed inward along the locations of adjacent left regions 112b)
With regards to claim 2, Kim discloses the integrated circuit device of claim 1, wherein the concave portions of the respective side surfaces of the plurality of second cell patterns are spaced apart from the plurality of first cell patterns that are adjacent thereto by a first separation distance, and
the plurality of first cell patterns and the plurality of second cell patterns are spaced apart from each other by at least the first separation distance. (see FIG. 15E, showing the spacing between the cells comprising regions 112a)
With regards to claim 5, Kim discloses the integrated circuit device of claim 1, wherein the plurality of first cell patterns are equally spaced apart from each other in the first horizontal direction and in the second horizontal direction to form first cell matrices,
wherein the plurality of second cell patterns are equally spaced apart from each other in the first horizontal direction and in the second horizontal direction to form second cell matrices that intersect the first cell matrices. (see FIGS. 7 and 15E, showing the equal spacings of the cells)
With regards to claim 6, Kim discloses the integrated circuit device of claim 5, wherein, in a plan view, four second cell patterns from among the plurality of second cell patterns surround a first cell pattern from among the plurality of first cell patterns and are asymmetrical with respect to the first cell pattern. (see FIGS. 7 and 15E, showing the patterns surrounding the first patterns)
With regards to claim 7, Kim discloses the integrated circuit device of claim 5, wherein a distance between adjacent ones of the plurality of first cell patterns is equal to a distance between adjacent ones of the plurality of second cell patterns. (see FIGS. 7 and 15E, showing the equidistant spacing)
With regards to claim 10, Kim discloses the integrated circuit device of claim 1, further comprising:
a plurality of wordlines (word lines WL) that are on the substrate, and are in a plurality of wordline trenches that extend in the first horizontal direction,
wherein the plurality of cell patterns overlap portions of the plurality of wordlines in a vertical direction. (See FIG. 7C, showing the overlap of the word lines and the cell regions)
Allowable Subject Matter
Claims 3-4 and 8-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
None of the cited references teach or suggest, either alone or in combination, at least “wherein a planar area of each of the plurality of second cell patterns is less than a planar area of each of the plurality of first cell patterns,” as recited in claims 11 and 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
YOON (US 20190103302 A1) – memory device with curved active regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812