Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 20 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on October 3rd, 2025. Claims 1-19 are examined below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 17, the underlined element of “each of the driver circuits and a pixel group driven by the driver circuit has a spacing (#1) therebetween and the spacing (#2) is half of the foldable area, spacings (#3), both in the same non-foldable area..” is unclear of the specific scope intended by term “spacing”. The first spacing (#1) is plural due to the multiple spacings needed for each individual driver circuit and pixel group. The second spacing (#2) further limits the scope of one spacing (interpreted from the specific term of ‘the spacing’), but it never distinguishes which spacing from the plurality of spacings is half of the foldable area. Lastly, the third spacing (#3) returns to being plural, but the context of the unfinished limitation does not clearly read what the spacings placement are in relation to the non-foldable area/foldable area. It is suggested for the Applicant to make clear exactly what is meant by defining features for the spacings.
Claim 18 includes all the limitations of claim 17, therefore, are rejected for the same reason described above.
These claims are rejected below as best understood.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-2, 7-15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable by Li et al. (US-10520978-B1 referred as Li) in view of Yang et al. (US-20210233455-A1 referred as Yang).
Regarding claim 1. Li discloses a foldable display panel comprising:
a foldable area and a plurality of non-foldable areas located at both sides of the foldable area in a width direction of the foldable display panel ([col 8 line 63 - col 9 line 12], figure 10, the foldable display panel #100 contains a foldable area #20 and the plurality of nonfoldable areas #101-102 located on both sides of the foldable area #20);
a plurality of pixel groups, comprising a plurality of first pixel groups located in the foldable area and a plurality of second pixel groups located in the plurality of non-foldable areas ([col 6 lines 44 - 63], figure 10, the foldable display panel #100 includes a plurality of pixels with the first pixel groups in the foldable area #20 and the second pixel groups in the nonfoldable area #101-102); and
a plurality of driver circuits located in the plurality of non-foldable areas and for driving the plurality of pixel groups, wherein the plurality of driver circuits comprises a plurality of first driver circuits for driving the plurality of first pixel groups and a plurality of second driver circuits for driving the plurality of second pixel groups ([col 6 lines 44 - 63], figure 6, the plurality of pixel groups include a plurality of pixel driving circuits which are electrically connected as specified in the specifications. The plurality of driver circuits consists of first driver circuits for the first pixel group and the second driver circuit for the second pixel group as stated in [col 6 lines 44 - 63]).
Li lacks each pixel group of the plurality of pixel groups comprises sub-pixels of different colors which are arranged in columns, each driver circuit of the plurality of driver circuits corresponds to a same column of sub-pixels that are disposed in a same column, and each driver circuit of the plurality of driver circuits is located between two adjacent sub-pixels of the plurality of second pixel groups in a same column.
Yang discloses each pixel group of the plurality of pixel groups comprises sub-pixels of different colors which are arranged in columns, each driver circuit of the plurality of driver circuits corresponds to a same column of sub-pixels that are disposed in a same column, and each driver circuit of the plurality of driver circuits is located between two adjacent sub-pixels of the plurality of second pixel groups in a same column ([0078], figure 3B, each pixel group of the plurality of pixel groups comprises of sub-pixels #R/#G/#B of different colors and arranged in columns. Each driver circuit #RSC/GSC/BSC (connected to the display panel #310 as a data driver) corresponds to a same column of subpixels that are disposed on the same column. Each driver circuit #RSC/GSC/BSC is located between two adjacent sub-pixels #R/#G/#B depending on its placement as illustrated. From the plurality of the entire second pixel group seen on the device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li to include the pixels groups to contain subpixels connected to the circuit drivers as taught by Yang in order to reduce stress points on the circuit driver, provide more pixels per square inch, and to enhance the illumination of the RGB colors.
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Regarding claim 2. Li as modified discloses a substrate ([col 7 lines 55 - 66], figure 8 annotated above, the substrate is illustrated as the bottom layer of which all other elements are disposed over);
a driver device layer located on the substrate, wherein the driver circuits are disposed in the driver device layer ([col 7 lines 55 - 66], figure 8 annotated above, the driver device layer #M5 is seen located on the substrate. The #M5 region makes up the pixel driving circuit as further described in ([col 7 lines 45 - 66] and figure 7);
a first electrode layer located at a side of the driver device layer away from the substrate, wherein the first electrode layer comprises a plurality of first electrodes located in the foldable area and a plurality of second electrodes located in the non-foldable areas ([col 7 lines 45 - 64], figure 8, a first electrode layer #19(220) is seen at a side of the driver device layer #M5 away from the substrate. (35), figure 6, the first electrode layer #19(220) comprises a plurality of first electrodes #181 on the foldable area #101 and second electrodes (#181, #182) on the nonfoldable area #102); and
a connection line layer located between the first electrode layer and the driver device layer, wherein the connection line layer comprises first connection lines, through which the first driver circuits are connected to the plurality of first electrodes respectively ([col 8 lines 1 - 10], figure 8, the connection line layer #220 is located in between the first electrode layer #19(220) and the driver device layer #M5. The connection layer further comprises of a first connection line #183 which connects to the first driver circuit in the foldable area #20 in figure 6).
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Regarding claim 7. Li as modified discloses wherein the foldable area comprises a first foldable area and a second foldable area which are disposed side by side along the width direction ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the foldable area #20 comprises of a first foldable area #20a, and a second foldable area #20b), and the non-foldable areas comprise a first non-foldable area adjacent to the first foldable area and a second non-foldable area adjacent to the second foldable area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the nonfoldable areas comprise of a first nonfoldable area #101a adjacent to the first foldable area #20a and also a second nonfoldable area #102a adjacent to the second foldable area #20b); the first pixel groups comprise first sub-pixels located in the first foldable area and second sub-pixels located in the second foldable area ([col 6 lines 44 - 54], figure 6, the first pixel groups comprise of first subpixels located in the first foldable area #20a and second subpixels #20b in the second foldable area as stated in [col 6 lines 44 - 63]); and the first driver circuits comprise first sub-circuits for driving the first sub-pixels and second sub-circuits for driving the second sub-pixels, wherein the first sub-circuits are located in the first non-foldable area, and the second sub-circuits are located in the second non-foldable area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the first driver circuits comprise of first subcircuits #51 for driving the first subpixels and the second subcircuit #52 for driving the second subpixels. The first subcircuits #51 are located in the first nonfoldable area #101 and the second subcircuits #52 are located in the second nonfoldable area #102 as stated in [col 6 lines 44 - 63]);
Regarding claim 8. Li as modified discloses wherein along the width direction, an extension size of the first foldable area and/or second foldable area is half of an extension size of the foldable area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the width of the first foldable area #20a is half of the extension size of the foldable area #20).
Regarding claim 9. Li as modified discloses wherein the first sub-circuits are uniformly distributed in the first non-foldable area and; the second sub-circuits are uniformly distributed in the second non-foldable area ([col 8 line 63 - col 9 line 12], figure 10, the first sub circuits #51 in the first nonfoldable area #101 are uniformly distributed and the second sub-circuits #52 are uniformly distributed in the second non-foldable area #102).
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Regarding claim 10. Li as modified discloses wherein the first non-foldable area comprises a first transition area adjacent to the first foldable area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the first nonfoldable area #101 comprises a first transition area #101a adjacent to the first foldable area #20a) and a first main display area located at a side of the first transition area away from the first foldable area, and wherein the first sub-circuits are located in the first transition area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the first main display area #101b is located at a side of the first transition area #101a away from the first foldable area #20a. It is stated that the first sub circuit #51 is only kept within the first nonfolding region #101).
Regarding claim 11. Li as modified discloses wherein the second pixel groups comprise first transition sub-pixels located in the first transition area, the second driver circuits comprise first transition circuits for driving the first transition sub-pixels, and the first transition circuits are located in the first transition area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second pixel group comprise of first transition sub pixels in the transition area #101a. The second driver circuit comprise of first transition circuits for the first transition subpixels. And the first transition circuit is located in the first transition area #101a as stated in [col 6 lines 44 - 63]); and the second pixel groups comprise first main sub-pixels located in the first main display area, the second driver circuits comprise first main circuits for driving the first main sub-pixels, and the first main circuits are located in the first main display area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second pixel group comprises of first main sub pixels located in the first main display area #101b. the second driver circuit comprises of first main circuits for driving the first main subpixels. The first main circuits is located in the first main display area #101b as stated in [col 6 lines 44 - 63]).
Regarding claim 12. Li as modified discloses wherein, the second non-foldable area comprises a second transition area adjacent to the second foldable area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second nonfoldable area #102 comprises a second transition area #102a adjacent to the second foldable area #20b) and a second main display area located at a side of the second transition area away from the second foldable area, and wherein the second sub-circuits are located in the second transition area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second main display area #102b is located at a side of the second transition area #102a. The second subcircuits #52 is located in the first nonfolding area #101 and the first transition area #101a but not within the foldable are #20 as stated in [col 8 line 63 - col 9 line 12]).
Regarding claim 13. Li as modified discloses wherein the second pixel groups comprise second transition sub-pixels located in the second transition area, the second driver circuits comprise second transition circuits for driving the second transition sub-pixels, and the second transition circuits are located in the second transition area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second pixel groups comprise of second transition subpixels located in the second transition area #102a. The second driver circuits comprise second transition circuits for driving the second transition subpixels. The second transition circuits is located in the second transition area).
Regarding claim 14. Li as modified discloses wherein the second pixel groups comprise second main sub-pixels located in the second main display area, the second driver circuits comprise second main circuits for driving the second main sub-pixels, and the second main circuits are located in the second main display area ([col 8 line 63 - col 9 line 12], figure 10 annotated above, the second pixel group comprises of second main subpixels located in the second main display area #102b with second driver circuits comprising of second main circuits for driving the second main sub pixels. The second main circuits are located in the second main display area #102b).
Regarding claim 15. Li as modified discloses wherein each of the driver circuits and a pixel group driven by the driver circuit are displaced along the width direction ([col 8 line 63 - col 9 line 12], figure 10, the driver circuit comprising of the first driver circuit and the second driver circuit is displaced throughout the width direction); and the connection line layer further comprises second connection lines for connecting the second electrodes and the second driver circuits respectively ([col 6 lines 44 - 54], figure 8, the connection line #19(220) further comprises of a second connection line #181 and #182 for connecting to the second driver circuits in the nonfolding regions as seen in figure 6).
Regarding claim 19. Li as modified discloses wherein the driver circuits are not disposed in the foldable area ([col 8 line 63 - col 9 line 12], figure 10, the driver circuit #51 and #52 are not disposed on the foldable area #20 as mentioned in the specifications).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US-10520978-B1 referred as Li) and Yang et al. (US-20210233455-A1 referred as Yang), in further view of Park (US-20190340959-A1).
Regarding claim 3. Li as modified lacks a first flattened layer located between the driver device layer and the connection line layer; wherein the driver device layer comprises a plurality of first through holes located in the foldable area, and at least a part of the first flattened layer is filled in the plurality of first through holes.
Park discloses a first flattened layer located between the driver device layer and the connection line layer ([0107], figure 3, the first flattened layer #325 is in between the drive device layer ([0107] described driver device layer consisting of #ACT, #GE, #SE, #DE) and the connection line layer #LE); wherein the driver device layer comprises a plurality of first through holes located in the foldable area, and at least a part of the first flattened layer is filled in the plurality of first through holes ([0111], figure 3, the drive device layer (#ACT, #GE, #SE, #DE) includes holes #CNT1 located as a plurality in each drive device layer throughout the display device #100 in the display module #210 and including in the foldable area #FR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include a driver device layer with a through hole and first flattened layer as taught by Park in order to increase manufacturing speed, hole etching precision, and to increase versatility.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US-10520978-B1 referred as Li), Yang et al. (US-20210233455-A1 referred as Yang), and Park (US-20190340959-A1) as applied to claim 3, in further view of Bang et al. (US-20210173446-A1 referred as Bang).
Regarding claim 4. Li as modified lacks a first inorganic insulation layer located at a side of the driver device layer faced to the substrate, wherein the first inorganic insulation layer comprises second through holes located in the foldable area, the second through holes are connected to the first through holes, and at least a part of the first flattened layer is filled in the second through holes.
Park discloses a first inorganic insulation layer located at a side of the driver device layer faced to the substrate ([0103], figure 3, the first inorganic insulation layer #322 is located at a side of the driver device layer (#ACT, #GE, #SE, #DE) facing the substrate #311 (as stated in [0100])).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include a first inorganic insulation layer as taught by Park in order to increase electrical protection, circuit integrity, and with an enhanced device lifetime.
Li as modified by Park still lacks wherein the first inorganic insulation layer comprises second through holes located in the foldable area, the second through holes are connected to the first through holes, and at least a part of the first flattened layer is filled in the second through holes.
Bang discloses wherein the first inorganic insulation layer comprises second through holes located in the foldable area, the second through holes are connected to the first through holes, and at least a part of the first flattened layer is filled in the second through holes ([0092], figure 8B, the first inorganic insulation layer #IL comprises of second through holes #H3 in the foldable area. The second through holes #H3 are connected to the first through holes #H2. Part of the first flattened layer is filled in the second through holes #H2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified by Park to include a first inorganic insulation layer, and first flattened layer with second through holes as taught by Bang in order to increase electrical protection, circuit integrity, and provide an enhanced device lifetime.
Regarding claim 5. Li as modified lacks wherein the driver device layer comprises an active layer and a plurality of conduction layers, and a second inorganic insulation layer is provided between the active layer and the conduction layers as well as between adjacent ones of the conduction layers.
Park discloses wherein the driver device layer comprises an active layer and a plurality of conduction layers, and a second inorganic insulation layer is provided between the active layer and the conduction layers as well as between adjacent ones of the conduction layers ([0107], figure 3, the driver device layer comprises of an active layer #GE, a plurality of conduction layers #SE and #DE and also a second inorganic insulation layer #323 which is in between the active layers and the conduction layers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include active, conduction and a second inorganic insulation layer as taught by Park in order to increase device versatility, provide thermal protection in the circuit, and to increase the devices lifetime.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US-10520978-B1 referred as Li), Yang et al. (US-20210233455-A1 referred as Yang), and Park (US-20190340959-A1) as applied to claim 3 in further view of Liang (US-20210234117-A1).
Regarding claim 6. Li as modified lacks further comprising: a second flattened layer and a pixel definition layer, wherein the second flattened layer is located between the connection line layer and the first electrode layer, and the pixel definition layer is located at a side of the first electrode layer away from the connection line layer and comprises a body part and pixel openings, wherein the first electrodes and the second electrodes are disposed corresponding to the respective pixel openings, and the pixel openings are provided to be filled with light-emitting materials.
Park discloses further comprising: a pixel definition layer, wherein the pixel definition layer is located at a side of the first electrode layer away from the connection line layer and comprises a body part and pixel openings, wherein the first electrodes and the second electrodes are disposed corresponding to the respective pixel openings, and the pixel openings are provided to be filled with light-emitting materials. ([0108] [0115], figure 3, the pixel definition layer #PDL is at the side of the first electrode layer #UE away from the connection line #LE. The pixel definition layer #PDL includes a first electrode #UE and second electrode #LE disposed corresponding to the respective pixel openings. The pixel openings is filled with light emitting material #IL).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to the pixel definition layer, first and second electrodes and light emitting material as taught by Park in order to increase device versatility, provide quicker circuitry response, and enhance manufacturing speed.
Li as modified by Park still lacks a second flattened layer, wherein the second flattened layer is located between the connection line layer and the first electrode layer.
Liang discloses a second flattened layer, wherein the second flattened layer is located between the connection line layer and the first electrode layer ([0031], figure 2, the second flattened layer #11 is located in between the connection layer #8 and the first electrode layer #12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified by Park to include of the second flattened layer in order as taught by Park in order to increase device weight distribution, reach greater connection reach, and to reduce material usage in manufacturing.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US-10520978-B1 referred as Li), Yang et al. (US-20210233455-A1 referred as Yang), and Park (US-20190340959-A1) in further view of Jeong (US-20170194409-A1).
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Regarding claim 16. Li as modified lacks wherein there is a first spacing between each of the driver circuits and a pixel group driven by the driver circuit, and a value of the first spacing gradually decreases in a direction from the foldable area to the non-foldable area adjacent to the foldable area.
Jeong discloses wherein there is a first spacing between each of the driver circuits and a pixel group driven by the driver circuit, and a value of the first spacing gradually decreases in a direction from the foldable area to the non-foldable area adjacent to the foldable area ([0067], figure 2 annotated above, the first spacing from each driver circuit (#PD4, #PD3, #PD2) has a width space that is decreasing as the circuitry approaches from the nonfoldable area #NA1 to the foldable area #BA as seen in width #space2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include of pixel driving circuit with a decreasing width to the pixels as taught by Jeong in order to increase device weight distribution, reduce failure of device, and to enhance the circuitries safety.
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Regarding claim 17. Li as modified lacks wherein along the width direction, each of the driver circuits and a pixel group driven by the driver circuit has a spacing therebetween and the spacing is half of the foldable area, the spacings, both in the same non-foldable area, and from the non-foldable area to the foldable area, are the same, and.
Jeong discloses wherein along the width direction, each of the driver circuits and a pixel group driven by the driver circuit has a spacing therebetween and the spacing is half of the foldable area, the spacings, both in the same non-foldable area, and from the non-foldable area to the foldable area, are the same, and ([0054], figure 1 annotated above with a clearer view of #X in figure 2, each of the driver circuits #PD2 and a pixel group #PX4 contains a spacing therebetween as #spacing5. The spacing #spacing5 is half of the foldable areas #BA).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include a pixel driving circuit to have a distance to the pixel as wide as half the foldable region as taught by Jeong in order to increase circuitry protection, include additional access points, and to increase the device longevity.
Regarding claim 18. Li as modified lacks wherein each of the non-foldable areas comprises an edge display area adjacent to a non-display area, and driver circuits for driving pixel groups within the edge display area are located in the non-display area.
Park discloses wherein each of the non-foldable areas comprises an edge display area adjacent to a non-display area, and driver circuits for driving pixel groups within the edge display area are located in the non-display area ([0067], figure 1, as stated, the nondisplay areas #NDA holds driver circuits that provide signal for the display area #DPA).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Li as modified to include the pixel driving circuitry within the non display area as taught by Jeong in order to increase circuitry protection, to increase the device lifetime, and to make repairs easier to conduct.
Response to Amendment
Applicant's arguments filed 01/27/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art of Yang et al.. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818