DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 12/12/2025, with respect to the drawing objections and the 35 USC 112(b) Rejections have been fully considered and are persuasive. The drawing objections and the 35 USC 112(b) Rejections have been withdrawn.
Applicant's arguments filed Remarks, filed 12/12/2025, with respect to the 35 USC 102(a)(2) and/or 103 on 1 and dependent claims have been fully considered but they are not persuasive. The applicant argues that Yang does not teach the widths, the examiner respectfully disagrees the claimed features as written is disclosed within the prior art of record as shown below and illustrated in fig. 14A [See annotation of fig. 14A below].
Applicant’s arguments, see Remarks, filed 12/12/2025, with respect to the rejection(s) of claims 10 and 17 under 35 USC 102(a)(2) and/or 103 have been fully considered and are persuasive, in view the applicants amendment and argument, See examiners interpretation of the structural limitation implied by the functional limitation that was amended above, if the applicant disagrees with this interpretation the examiner recommends to explicitly claiming the structure. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20220109046 A1 Hong et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20240282670 A1 Yang et al hereafter “Yang”.
Claim 1 Yang teaches A semiconductor structure, comprising:
a first stacked device (Left side of fig. 14A) comprising:
a first field-effect transistor (Represented by the Lower Left Side of fig. 14A) comprising one or more first nanosheet layers (Left 110C Fig. 14A);
a second field-effect transistor (Represent by the upper left side of fig. 14A) vertically stacked above the first field-effect transistor [illustrated fig. 14A], the second field-effect transistor comprising one or more second nanosheet layers (Left 120C fig. 14A); and
a first dielectric insulator layer (left 140 fig. 14A) positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width [sufficiently illustrated fig. 14A]; and
a second stacked device (Right side of fig. 14A) adjacent the first stacked device [illustrated fig. 14A], the second stacked device comprising:
a third field-effect transistor (Represented by the lower right side of fig. 14A) comprising one or more third nanosheet layers (right 110C fig. 14A);
a fourth field-effect transistor (Represented by the upper right side of fig. 14A) vertically stacked above the third field-effect transistor [illustrated fig. 14A], the fourth field-effect transistor comprising one or more fourth nanosheet layers (right 120C fig. 14A); and
a second dielectric insulator layer (right 140 fig. 14A) positioned between the third field-effect transistor and the fourth field-effect transistor, the second dielectric insulator layer having a second width [Sufficiently illustrated fig. 14A] less than the first width of the first dielectric insulator layer [See annotation below, met under broadest reasonable interpretation fig. 14A illustrates at least one second width that is less than at least one first width, wherein the term “a” may refer to either “an individual” or “a collective” in “a first width and “a second width”, in this case Yang teaches at least two first widths and at least two second widths];
wherein the first width of the first dielectric insulator layer is equal to a third width [see annotation below] of the one or more first nanosheet layers, and the second width of the second dielectric insulator layer is equal to a fourth width [see annotation below] of the one or more fourth nanosheet layers [sufficiently illustrated fig. 14A].
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Annotated fig. 14A: highlighting the first width, the second width, the third width, and the fourth width
Claim 3 Yang teaches the semiconductor structure according to claim 1, further comprising a third dielectric insulator layer (Left 131 fig. 14A) disposed on a bottom surface of the first stacked device (bottom most surface of left 115 fig. 14A)and a fourth dielectric insulator layer (right 141 fig. 14A) disposed on a bottom surface of the second stacked device (bottom most surface of right 115 fig. 14A).
Claim 4 Yang teaches the semiconductor structure according to claim 1, wherein the first stacked device and the second stacked device are separated by an isolation dielectric pillar (116 fig. 14A) [sufficiently illustrated fig. 14A].
Claim 5 Yang teaches the semiconductor structure according to claim 1, wherein the first field-effect transistor further comprises a first gate structure (left 115 fig. 14A) and the second field-effect transistor further comprise a second gate structure (left 125 fig. 14A) separated from the first gate structure by the first dielectric insulator layer [sufficiently illustrated fig. 14A].
Claim 8 Yang teaches the semiconductor structure according to claim 1, wherein the second stacked device further comprises a third gate structure (comprising right 125 and right 115 fig. 14A) disposed over the third field-effect transistor and the fourth field-effect transistor [sufficiently illustrated fig. 14A].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 15-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as applied the claims above, and further in view of US 20220109046 A1 Hong et al.
Claim 10 Yang teaches a semiconductor structure, comprising:
a first stacked device (Represented by the left side of fig. 14A) comprising:
a first field-effect transistor (represented by the lower left side of fig. 14A) comprising a first gate structure (left 115 fig. 14A);
a second field-effect transistor (represented by the upper left side of fig. 14A) vertically stacked above the first field-effect transistor [sufficiently illustrated fig. 14A], the second field-effect transistor comprising a second gate structure (left 125 fig. 14A); and
a first dielectric insulator layer (left 140 fig. 14A) positioned between the first field-effect transistor and the second field-effect transistor and separating the first gate structure from the second gate structure [sufficiently illustrated fig. 14A]; and
a second stacked device (represented by the right side of fig. 14A) adjacent the first stacked device [sufficiently illustrated fig. 14A], the second stacked device comprising:
a third field-effect transistor (represented by the lower right side of fig. 14A);
a fourth field-effect transistor (represented by the upper right side of fig. 14A) vertically stacked above the third field-effect transistor [sufficiently illustrated fig. 14A];
a second dielectric insulator layer (right 140 fig. 14A) positioned between the third field-effect transistor and the fourth field-effect transistor [sufficiently illustrated fig. 14A]; and
a third gate structure (comprising right 125 and right 115 fig. 14A) disposed over the third field-effect transistor, the fourth field-effect transistor and the second dielectric insulator layer.
Yang does not explicitly teach wherein the third gate structure is a same gate structure functionally shared between the third field-effect transistor and the fourth field-effect transistor.
Hong teaches a similar device wherein a gate structure (comprising 325 and 315 fig. 3C) is a same gate structure functionally shared between a third field-effect transistor (comprising at least 310 fig. 3C) and a fourth field-effect transistor (comprising at least 320 fig. 3C). wherein the third field-effect transistor is separated from the fourth field-effect transistor by a dielectric layer (330 fig. 3C)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device Yang teaches with the device Hong teaches such that “the third gate structure is a same gate structure functionally shared between the third field-effect transistor and the fourth field-effect transistor” to enable the third field-effect transistor and the fourth field-effect transistor to receive a same input signal and/or to form an inverter circuit [Paragraph 0069 Hong] and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is stacked transistor devices for forming logic circuits.
Claim 15 Yang in view of Hong teaches the semiconductor structure according to claim 10, wherein the first dielectric insulator layer has a first width [sufficiently illustrated fig. 14A] and the second dielectric insulator layer has a second width [sufficiently illustrated fig. 14A] less than the first width of the first dielectric insulator layer [limitation met under broadest reasonable interpretation, see annotation below].
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Annotated fig. 14A: highlighting the second with less than the first width
Claim 16 Yang in view of Hong teaches the semiconductor structure according to claim 10, wherein the first stacked device and the second stacked device are separated by an isolation dielectric pillar (116 fig. 14A).
Claim 17 Yang teaches an integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a first stacked device (represented by the left side of fig. 14A) comprising:
a first field-effect transistor (represented by the lower left side of fig. 14A) comprising a first gate structure (left 115 fig. 14A);
a second field-effect transistor (represented by the upper left side of fig. 14A) vertically stacked above the first field-effect transistor [sufficiently illustrated fig. 14A], the second field-effect transistor comprising a second gate structure (left 125 fig. 14A); and
a first dielectric insulator layer (left 140 fig. 14A) positioned between the first field-effect transistor and the second field-effect transistor and separating the first gate structure from the second gate structure [sufficiently illustrated fig. 14A]; and
a second stacked device (represented by the right side of fig. 14A) adjacent the first stacked device [illustrated fig. 14A], the second stacked device comprising:
a third field-effect transistor (represented by the lower right side of fig. 14A);
a fourth field-effect transistor (represented by the upper right side of fig. 14A) vertically stacked above the third field-effect transistor [illustrated fig. 14A];
a second dielectric insulator layer (right 140 fig. 14A) positioned between the third field-effect transistor and the fourth field-effect transistor [sufficiently illustrated fig. 14A]; and
a third gate structure (comprising right 125 and right 115 fig. 14A) disposed over the third field-effect transistor, the fourth field-effect transistor and the second dielectric insulator layer [sufficiently illustrated fig. 14A];
Yang does not explicitly teach wherein the third gate structure is a same gate structure functionally shared between the third field-effect transistor and the fourth field-effect transistor.
Hong teaches a similar device wherein a gate structure (comprising 325 and 315 fig. 3C) is a same gate structure functionally shared between a third field-effect transistor (comprising at least 310 fig. 3C) and a fourth field-effect transistor (comprising at least 320 fig. 3C). wherein the third field-effect transistor is separated from the fourth field-effect transistor by a dielectric layer (330 fig. 3C)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device Yang teaches with the device Hong teaches such that “the third gate structure is a same gate structure functionally shared between the third field-effect transistor and the fourth field-effect transistor” to enable the third field-effect transistor and the fourth field-effect transistor to receive a same input signal and/or to form an inverter circuit [Paragraph 0069 Hong] and/or combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case it is stacked transistor devices for forming logic circuits.
Claim 20 Yang in view of Hong teaches the integrated circuit according to claim 17, wherein the first dielectric insulator layer has a first width [sufficiently illustrated fig. 14A] and the second dielectric insulator layer has a second width [sufficiently illustrated fig. 14A] less than the first width of the first dielectric insulator layer [met under broadest reasonable interpretation, see annotation below].
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Annotated fig. 14A: highlighting the second with less than the first width
Claims 6-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Yang as applied to the claims above, and further in view of US 11996411 B2 Huang et al hereafter “Huang”.
Claim 6 Yang teaches the semiconductor structure according to claim 5, further comprising a first frontside gate contact (128 fig. 14A) connected to the first gate structure [illustrated fig. 14A, met in view of the drawings as presented by the applicant, see 112 above]
Yang does not teach the first frontside gate contact is connected to a frontside back-end-of-the-line layer.
Huang teaches a first frontside gate contact (right 220 fig. 2) connected to a first gate structure (right 204 fig. 2) and a frontside back-end-of-the-line layer (comprising 218 fig. 2, explicitly disclosed Column 3 lines 42-51).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the frontside back-end-of-the-line layer as Huang teaches such that the first frontside gate contact is connected to a frontside back-end-of-the-line layer to electrically address the gate from the front side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claim 7 Yang in view of Huang teaches the semiconductor structure according to claim 6,
Yang does not teach a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer.
Huang teaches a backside gate contact (214 fig. 2) connected to the second gate structure (208 fig. 2, met in the same manner as illustrated in the figures of the instant application, see 112 above). And a backside back-end-of-the-line layer (comprising 212 fig. 2).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the backside contact and the backside back-end-of-the-line layer as Huang teaches such that “a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer” to electrically address the second gate from the back side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claim 9 Yang teaches the semiconductor structure according to claim 8, further comprising a second frontside gate contact (128 fig. 14A) connected to the third gate structure
Yang does not teach the second front side gate contact connected to a frontside back-end-of-the-line layer.
Huang teaches a second front side gate contact (220 left fig. 2) connected to a third gate structure (comprising 204 and 208 fig. 2) and a frontside back-end-of-the-line layer (218 fig. 2)
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the frontside back-end-of-the-line layer as Huang teaches such that the second frontside gate contact is connected to a frontside back-end-of-the-line layer to electrically address the gate from the front side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claims 12-14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Hong as applied to the claims above, and further in view of Huang.
Claim 12 Yang in view of Hong teaches the semiconductor structure according to claim 10, further comprising a first frontside gate contact (right 128 fig. 14A) connected to the third gate structure
Yang in view of Hong does not teach the first frontside gate contact connected to a frontside back-end-of-the-line layer.
Huang teaches a first frontside gate contact (right 220 fig. 2) connected to a first gate structure (right 204 fig. 2) and a frontside back-end-of-the-line layer (comprising 218 fig. 2, explicitly disclosed Column 3 lines 42-51).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the frontside back-end-of-the-line layer as Huang teaches such that the first frontside gate contact is connected to a frontside back-end-of-the-line layer to electrically address the gate from the front side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claim 13 Yang in view of Hong and Huang teaches the semiconductor structure according to claim 12, further comprising a second frontside gate contact (left 128 fig. 14A) connected to the first gate structure [sufficiently illustrated fig. 14A, matches the structure as disclosed in the instant application] and the frontside back-end-of-the-line layer [met in view the frontside back-end-of-the line layer of Huang 218 fig. 2, the first frontside gate contact (right 220 fig. 2) connects to the frontside back-end of the line layer (218 fig. 2) and a first gate (204 fig. 2), when modified Yang would necessarily include the disclosed structure].
Claim 14 Yang in view of Hong and Huang teaches the semiconductor structure according to claim 13,
Yang does not teach a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer.
Huang teaches a backside gate contact (214 fig. 2) connected to the second gate structure (208 fig. 2, met in the same manner as illustrated in the figures of the instant application, see 112 above). And a backside back-end-of-the-line layer (comprising 212 fig. 2).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the backside contact and the backside back-end-of-the-line layer as Huang teaches such that “a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer” to electrically address the second gate from the back side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claim 18 Yang in view of Hong the integrated circuit according to claim 17, wherein the at least one of the one or more semiconductor structures further comprises a first frontside gate contact (right 128 fig. 14A) connected to the third gate structure
Yang does not teach the first frontside gate contact connected to a frontside back-end-of-the-line layer.
Huang teaches a first frontside gate contact (right 220 fig. 2) connected to a first gate structure (right 204 fig. 2) and a frontside back-end-of-the-line layer (comprising 218 fig. 2, explicitly disclosed Column 3 lines 42-51).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the frontside back-end-of-the-line layer as Huang teaches such that the first frontside gate contact is connected to a frontside back-end-of-the-line layer to electrically address the gate from the front side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Claim 19 Yang in view of Hong and Huang teaches the integrated circuit according to claim 18, wherein the at least one of the one or more semiconductor structures further comprises a second frontside gate contact (left 128 fig. 14A) connected to the first gate structure [illustrated fig. 14A, met in the same manner as disclosed in the figures] and the frontside back-end-of-the-line layer [met in view the frontside back-end-of-the line layer of Huang 218 fig. 2, the first frontside gate contact (right 220 fig. 2) connects to the frontside back-end of the line layer (218 fig. 2) and a first gate (204 fig. 2), when modified Yang would necessarily include the disclosed structure].
Yang does not teach a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer.
Huang teaches a backside gate contact (214 fig. 2) connected to the second gate structure (208 fig. 2, met in the same manner as illustrated in the figures of the instant application, see 112 above). And a backside back-end-of-the-line layer (comprising 212 fig. 2).
It would have been obvious to one of ordinary skill in the art to modify Yang by adding in the backside contact and the backside back-end-of-the-line layer as Huang teaches such that “a backside gate contact connected to the second gate structure and a backside back-end-of-the-line layer” to electrically address the second gate from the back side and/or the for the benefit of improved interconnection architecture and/ improved performance (Huang column 5 lines 26-43).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WCT/Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893