DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “each of the walls”, the term is vague and indefinite, because walls in not mentioned in the claim prior, so the term “the walls” means all the sidewalls? Does that include top and bottom walls as well? The term need clarification. For the examination purpose, the examiner is
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over ERDOEL et al. (US PGpub: 2022/0415830 A1), herein after ERDOEL, in view of
Fang et al. (US PGpub: 2021/0273196 A1), herein after Fang.
Regarding claim 1, ERDOEL teaches, in claims, Paragraphs [0078]-[0088], FIG. 2A-7, paragraphs [0036]-[0052], an integrated circuit (IC) device comprising:
an interconnect structure (containing metal layer 110, 131, 110, ) in a metal layer (205) of the IC device, the interconnect structure comprising a conductive material (205 is conductive); and
a waveguide structure (210) comprising a top wall, a bottom wall, and a pair of side walls, each of the walls comprising the conductive material (205), wherein one of the top wall and the bottom wall is in the metal layer of the IC device (PCB).
The cross section of the top, bottom and sidewall cross-section of the structure are not shown clearly. However, from FIG. 2E, 141 sidewalls, top wall and sidewalls are shown to be rectangular. So, the cryosections can be accommodated to fit the device needs in order to meet device functionality.
Regarding claim 2, ERDOEL teaches the IC device of claim 1, wherein the waveguide structure is a rectangular waveguide (210) , and the rectangular waveguide is coupled to a coplanar waveguide (is coupled to coplanar waveguide 131 via 106) .
Regarding claim 3, ERDOEL teaches the IC device of claim 2, wherein the one of the top wall and the bottom wall in the metal layer of the IC device is patterned to provide a transition to the coplanar waveguide (see FIG. 6 where metal layer which is conductive transitioning to coplanar waveguide 131).
Regarding claim 4, ERDOEL teaches the IC device of claim 1, wherein a dielectric material (130, FIG. 4A) is in a region bounded by the top wall, the bottom wall, and the pair of side walls.
Regarding claim 5, ERDOEL teaches the IC device of claim 1, wherein a semiconductor material (110, FIG. 4A) is in a region bounded by the top wall, the bottom wall, and the pair of side walls.
Regarding claim 6, ERDOEL teaches the IC device of claim 1, wherein the top wall is in the metal layer (205) of the IC device, the metal layer is over a substrate (PCB 200), and the pair of side walls extend from the metal layer into the substrate (FIG. 4A).
Regarding claim 7, ERDOEL teaches the IC device of claim 6, the IC device further comprising a device layer (110) between the substrate and the metal layer, the device layer having a plurality of transistors (die 110 has multiple transistor), wherein the pair of side walls extend through the device layer.
Regarding claim 8, ERDOEL teaches the IC device of claim 6, wherein the metal layer (205) is over a front side of the substrate, and the bottom wall is a portion of a back metallization layer on a back side of the substrate (bottom wall is by PCB substrate).
Regarding claim 9, ERDOEL teaches the IC device of claim 1, wherein the top wall is in a first metal layer (205) and the bottom wall is in a second metal layer (150), both the first metal layer and the second metal layer over a support structure (141) of the IC device(FIG. 7).
Regarding claim 10, ERDOEL teaches an integrated circuit (IC) device comprising:
an interconnect structure (containing metal layer 110, 131, 110, ) in a metal layer (205) of the IC device, the interconnect structure comprising a conductive material (205 is conductive); and
a waveguide structure (210) at least partially in the layer of the IC device, the waveguide structure comprising:
a base comprising a first conductive material (205);
a top comprising a second conductive material (150) ; and
a plurality of vias (141, FIG. 6)), each of the plurality of vias extending between the base and the top (as in FIG. 7).
A top is just a terminology and considering figure upside down will make it a top and it contains metallic waveguide. The Figures depicted from different embodiments taken in order to meet the clam limitation. The embodiments of different figures of ERDOEL can be combined so that device functionality is met and the device can be made minimizing the cost.
Regarding claim 11, ERDOEL teaches the IC device of claim 10, wherein the plurality of vias comprise the second conductive material (L3 or L4 as in FIG. 2E).
Regarding claim 12, ERDOEL teaches the IC device of claim 10, wherein the plurality of vias comprise a first set of vias arranged in a first row over a first side of the base and a second set of vias (132) arranged in a second row over a second side of the base.
Regarding claim 13, ERDOEL teaches the IC device of claim 10, wherein the first conductive material and the second conductive material comprise a same metal (141 having 142 (as in FIG. 2G), L2 or L3 and 132 can comprise same metal).
Regarding claim 14, ERDOEL teaches the IC device of claim 10, wherein a dielectric material (130) is within the waveguide structure between the base and the top.
Regarding claim 15, ERDOEL teaches the IC device of claim 10, wherein a semiconductor material (110) is within the waveguide structure between the base and the top.
Regarding claim 16, ERDOEL teaches the IC device of claim 10, wherein the top of the waveguide structure (210) is in the layer of the IC device, and the layer is a metal layer (150, 150 is metallic waveguide).
Regarding claim 17, ERDOEL teaches the IC device of claim 16, wherein the plurality of vias (141) extends into a substrate below the metal layer (150, FIG. 7).
Regarding claim 18, ERDOEL teaches the IC device of claim 17, wherein the base (205) is a portion of a back metallization layer on a back side of the substrate (as in FIG. 6 and 7).
Regarding claim 19, ERDOEL teaches A device comprising:
a support structure (142);
a metal layer over the support structure, the metal layer comprising a dielectric material and a conductive material (The laminate substrate 130 includes a stack of metal layers L1, L2, L3 and L4 in laminate. A prepreg layer P1 (e.g., a dielectric material) is arranged between metal layers L1 and L2. A dielectric core 133 is a dielectric substrate arranged between metal layers L2 and L3. Another prepreg layer P2 is arranged between metal layers L3 and L4. The substrate integrated waveguide 131 is built between metal layers L2 and L3. It includes metal layer L2 as a top wall or a top metal plate, metal layer L3 as a bottom wall or a bottom metal plate,… as in Paragraph [0037]); and
a structure (141) at least partially within the support structure and at least partially within the metal layer, the structure comprising: a top wall in the metal layer, the top wall comprising the conductive material, a bottom wall, and a pair of side walls extending between the top wall and the bottom wall, wherein a cross-section of the top wall, the bottom wall, and the pair of side walls is substantially rectangular (FIG. 2E).
The cross section of the top, bottom and sidewall cross-section of the structure are not shown clearly. However, from FIG. 2E, 141 sidewalls, top wall and sidewalls are shown to be rectangular. So, the cryosections can be accommodated to fit the device needs in order to meet device functionality.
Regarding claim 20, ERDOEL teaches the device of claim 19, wherein the dielectric material (133) is inside at least a portion of an area bounded by the top wall, the bottom wall, and the pair of side walls (see FIG. 2F, 133 is inside partially bounded by an area surrounded by side walls).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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