Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki (PGPub No. 20210320049) in further view of Haji (PGPub No. 20180240759).
Regarding claim 1, Suzuki teaches a solid state drive (SSD) apparatus comprising: a case including an upper wall and a lower wall; a substrate in the case; a first semiconductor chip on the first surface of the substrate (Fig. 6 points to a semiconductor storage device 1 (SSD apparatus) comprising an upper housing 30U (upper wall), a lower housing 30D (lower wall), an insulating substrate 300, and a DRAM 25 (first semiconductor chip).).
Suzuki alone fails to teach a plurality of first connection pads in or on a first surface of the substrate facing the upper wall of the case; and a first shielding structure electrically connecting the upper wall of the case to the plurality of first connection pads, wherein the first shielding structure comprises a plurality of first unit shielding structures surrounding the first semiconductor chip and spaced apart from each other with gaps therebetween, and wherein each of the plurality of first unit shielding structures comprises an elastic body.
Suzuki in combination with Haji teaches a plurality of first connection pads in or on a first surface of the substrate facing the upper wall of the case (Figs. 1-3 of Haji point to bond pads 16 and 18 (first connection pads).); and a first shielding structure electrically connecting the upper wall of the case to the plurality of first connection pads (Figs. 6-7 and [0050] of Suzuki point to a plate spring 16 (first shielding structure) connected to a ground electrode GM (first connection pad(s)) and the lower housing 30D (upper wall). The terms “upper” and “lower” as used in both Suzuki and the claimed invention are interpreted as spatial terms that may be used interchangeably depending on the chosen orientation.), wherein the first shielding structure comprises a plurality of first unit shielding structures surrounding the first semiconductor chip and spaced apart from each other with gaps therebetween (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures).), and wherein each of the plurality of first unit shielding structures comprises an elastic body (Figs. 6-7 of Suzuki point to a plate spring 16 (first unit shielding structure(s)).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that additional connection pads and elastic shielding structures are formed in order to provide total coverage against electromagnetic interference while also relieving any internal stress.
Regarding claim 2, Haji teaches wherein the upper wall of the case, the plurality of first unit shielding structures, and the plurality of first connection pads are electrically grounded (Figs. 3A-3B, [0045], and [0048] point to a grounded structure formed by the shielding structure 12 (upper wall), the vertical shield contacts 24 and 26 (first unit shielding structures), and the bond pads 16 and 18 (first connection pads).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the upper wall, first unit shielding structures, and first connection pads are all electrically grounded in order to reduce electromagnetic emissions by electrically shorting them through the ground conductive material.
Regarding claim 3, Haji teaches wherein a space between the substrate and the upper wall of the case comprises: a first accommodation space surrounded by the first shielding structure with the first semiconductor chip in the first accommodation space (Figs. 1 and 3 point to a first area (first accommodation space) defined by a first electronic component 20 (first semiconductor chip) surrounded by a number of the vertical shield contacts 24 and 26 (first shielding structure).); and a second accommodation space outside the first shielding structure, wherein the first accommodation space and the second accommodation space communicate with each other through the gaps of the first shielding structure (Id. points to a second area (second accommodation space) best defined by a second electronic component 22 and the remaining vertical shield contacts 24 and 26.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the first shielding structure is formed to create a first area around the first semiconductor chip while maintaining gaps that connect to the surrounding outer area in order to create multiple, physically separated paths for electromagnetic emissions to follow, which would reduce/prevent any leakage that might damage said chip.
Regarding claim 4, Haji teaches a second semiconductor chip on the first surface of the substrate in the second accommodation space (Figs. 1 and 3 point to the second electronic component 22 (second semiconductor chip).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that a second semiconductor chip is formed in the second accommodation space in order to better regulate electromagnetic emissions and prevent overburdening of the first shielding structure.
Regarding claim 5, Haji teaches wherein each of the plurality of first unit shielding structures comprises a surface mounting gasket or a pogo-pin (Fig. 1 points to vertical shield contacts 24 and 26 (pogo-pin).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that each of the plurality of first unit shielding structures comprises a pogo-pin shape in order to create continuous, low-impedance ground connection(s) that tolerate gaps, misalignments, and/or vibration.
Regarding claim 6, Suzuki in combination with Haji teaches wherein the plurality of first unit shielding structures are physically and electrically coupled to the plurality of first connection pads (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures) and bond pads 16 and 18 (first connection pads).), wherein each of the plurality of first unit shielding structures is in contact with the upper wall of the case by a restoring force of the elastic body (Figs. 6-7 and [0050] of Suzuki point to a plate spring 16 (first shielding structure(s)) connected to the lower housing 30D (upper wall), which has an effect of relieving the stress generated inside the insulating substrate 300.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the plurality of first unit shielding structures is physically and electrically coupled to the plurality of first connection pads and elastically connected to the upper wall in order to provide total coverage against electromagnetic interference while also relieving any internal stress.
Regarding claim 7, Suzuki in combination with Haji teaches wherein each of the plurality of first unit shielding structures further comprises a conductor in contact with the upper wall of the case by the restoring force of the elastic body (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures). Figs. 6-7 and [0050] of Suzuki further point to a plate spring 16 (first shielding structure(s)) connected to the lower housing 30D (upper wall), which has an effect of relieving the stress generated inside the insulating substrate 300.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the conductive material of each of the first unit shielding structures is elastically connected to the upper wall in order to better relieve any internal stress.
Regarding claim 8, Suzuki in combination with Haji teaches wherein the plurality of first unit shielding structures are physically and electrically coupled to the upper wall of the case, wherein each of the plurality of first unit shielding structures is in contact with a corresponding first connection pad among the plurality of first connection pads by a restoring force of the elastic body (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures). Figs. 6-7 and [0050] of Suzuki further point to a plate spring 16 (first shielding structure(s)) connected to the lower housing 30D (upper wall), which has an effect of relieving the stress generated inside the insulating substrate 300.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the plurality of first unit shielding structures is physically and electrically coupled to the upper wall and elastically connected to the plurality of first connection pads in order to provide total coverage against electromagnetic interference while also relieving any internal stress.
Regarding claim 9, Suzuki in combination with Haji teaches wherein each of the plurality of first unit shielding structures further comprises a conductor in contact with a corresponding first connection pad among the plurality of first connection pads by the restoring force of the elastic body (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures). Figs. 6-7 and [0050] of Suzuki further point to a plate spring 16 (first shielding structure(s)) connected to the lower housing 30D (upper wall), which has an effect of relieving the stress generated inside the insulating substrate 300.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that the conductive material of each of the first unit shielding structures is elastically connected to the corresponding first connection pad in order to better relieve any internal stress.
Regarding claim 10, Haji teaches wherein the first shielding structure further comprises a single bracket on which the plurality of first unit shielding structures are mounted, wherein the single bracket is coupled to the case (Figs. 1-3 of Haji point to the vertical shield contacts 24 and 26 (first unit shielding structures) and the shielding structure 12 (case). It is considered obvious that one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the formation of a bracket to be a result effective variable affecting the physical stability of the first unit shielding structures. Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that a mounting bracket is coupled to the case in order to improve physical stability by better attaching the first unit shielding structures to the case.
Regarding claim 11, Haji teaches wherein the plurality of first unit shielding structures are electrically connected to each other through the single bracket (Figs. 1-3 of Haji point to the vertical shield contacts 24 and 26 (first unit shielding structures) and the shielding structure 12 (case). It is considered obvious that one of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the formation of a bracket to be a result effective variable affecting the physical stability of the first unit shielding structures. Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Furthermore, it is also considered obvious that a bracket comprising conductive material such as a metal, which is commonly used in the art, could be used, which would naturally create an electrical connection between each of the first unit shielding structures.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that a mounting bracket is coupled to the case in order to both improve physical stability by better attaching the first unit shielding structures to the case and create a common electrical path between each of the first unit shielding structures.
Regarding claim 12, Suzuki teaches a third semiconductor chip on a second surface of the substrate opposite to the first surface of the substrate (Fig. 5 points to an integrated circuit 10H (third semiconductor chip).).
Suzuki alone fails to teach a second shielding structure including a plurality of second unit shielding structures between the second surface of the substrate and the lower wall of the case, wherein the plurality of second unit shielding structures surround the third semiconductor chip and are spaced apart from each other with gaps therebetween, wherein the substrate further comprises a plurality of second connection pads that are electrically grounded and in or on the second surface of the substrate, wherein the plurality of second unit shielding structures electrically connect the lower wall of the case to the plurality of second connection pads, and wherein each of the plurality of second unit shielding structures comprises an elastic body.
Suzuki in combination with Haji teaches a second shielding structure including a plurality of second unit shielding structures between the second surface of the substrate and the lower wall of the case, wherein the plurality of second unit shielding structures surround the third semiconductor chip and are spaced apart from each other with gaps therebetween, wherein the substrate further comprises a plurality of second connection pads that are electrically grounded and in or on the second surface of the substrate, wherein the plurality of second unit shielding structures electrically connect the lower wall of the case to the plurality of second connection pads, and wherein each of the plurality of second unit shielding structures comprises an elastic body (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (second unit shielding structures) and bond pads 16 and 18 (second connection pads). Figs. 6-7 and [0050] of Suzuki further point to a plate spring 16 (elastic body) connected to a ground electrode GM (first connection pad(s)) and the lower housing 30D (lower wall). It is considered obvious that the structure(s) disclosed could be duplicated to form a second shielding structure corresponding to the integrated circuit 10H (third semiconductor chip) previously mentioned in order to provide the same benefits as the first shielding structure.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that a third semiconductor chip is formed opposite to the first and second chips, along with a corresponding second shielding structure, in order to optimize use of the area provided by the case while still providing total coverage against electromagnetic interference and relieving any internal stress.
Regarding claim 13, Suzuki teaches an external connector connected to the substrate, wherein the external connector is exposed to outside of the case through an opening of the case (Fig. 6 and [0030] point to a connector 100 (external connector) comprising connectors 100U and 100D, which are connected to the insulating substrate 300 (the substrate) via a flexible substrate 200.).
Regarding claim 14, Suzuki in combination with Haji teaches an electronic component on the first surface of the substrate between neighboring ones of the plurality of first unit shielding structures (Figs. 1-3 of Haji point to vertical shield contacts 24 and 26 (first unit shielding structures) surrounding a first electronic component 20 (first semiconductor chip). Figs. 5-6 of Suzuki point to an integrated circuit 10E (electronic component). It is considered obvious that one of ordinary skill in the art could alter the preexisting gap(s) between the first unit shielding structures such that the electronic component was positioned between them in order to better optimize the provided area.) Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that an electronic component was further formed in order to in order to enable faster communication between the electronic component and the first semiconductor chip via shorter electrical pathways.
Regarding claim 15, Suzuki in combination with Haji teaches wherein the substrate further comprises a signal transmission line extending across a region between neighboring ones of the plurality of first connection pads (Figs. 1-3 of Haji point to bond pads 16 and 18 (first connection pads) surrounding a first electronic component 20 (first semiconductor chip). Fig. 3B and [0104] point to a connection (signal transmission line) between the DRAM 25 (first semiconductor chip) and a memory controller 20 which allows for various reading/writing operations.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that a signal transmission line was formed in order to allow for further communication with the first semiconductor chip.
Regarding claim 16, Haji teaches wherein the substrate further comprises conductive connection lines extending between neighboring ones of the plurality of first connection pads (Figs. 1-3 and [0014-15] point to bond pads 16 and 18 (first connection pads) on a module substrate 14, which are electrically coupled to ground. In light of this, it is considered obvious that said substrate 14 comprises conductive connection lines that collectively couple the bond pads/first connection pads to ground.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Suzuki and Haji, such that conductive lines extend among the plurality of first connection pads through the underlying substrate in order to create an electrically grounding structure that protects the surrounding components against electromagnetic interference.
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899