Prosecution Insights
Last updated: April 19, 2026
Application No. 18/342,200

SINGLE-MASK STACK ETCHING METHODS FOR FORMING STAIRCASE STRUCTURES

Non-Final OA §102§103
Filed
Jun 27, 2023
Examiner
KNUDSON, BRAD ALLAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
73 granted / 83 resolved
+20.0% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
42 currently pending
Career history
125
Total Applications
across all art units

Statute-Specific Performance

§103
53.7%
+13.7% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 83 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The disclosure is objected to because of the following informalities: Paragraph [0039] recites “…and then the layer 205-c and the layer 205-d may be pulled back (e.g., using respective etching operations) to form a staircase structure”, which should be “…and then the layer 205-c and the layer 205-b may be pulled back (e.g., using respective etching operations) to form a staircase structure”, in accordance with Fig. 2 and the preceding paragraphs. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-5, and 8 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Machida, Masahiko et al. (JP 2002/110631-A; hereinafter Masahiko). Regarding claim 1, Masahiko discloses a method (in particular, ¶ [0020-42, 0043-57]; entire document) comprising: forming a stack of materials on a semiconductor substrate (¶ [0044-51]), the stack of materials comprising a first material (ITO Film 4; Fig 3; ¶ [0027], a second material (metal film 5; Fig 3; ¶ [0027]), and a third material (6, comprising 61,62,63; Fig 3; ¶ [0045]); performing a first etching operation (First Etching (a), {4-2a}; Fig 3; ¶ [0027-32, {0052}]), wherein the first etching operation removes a first portion (as shown in Fig 3 and described in ¶ [0027-32]) of the first material; performing a second etching operation (Second Etching (b, {4-2b}); Fig 4; ¶ [0033-37, {0054}]), wherein the second etching operation removes a first portion (as shown in Fig 4 and described in ¶ [0033-37]) of the second material; performing a third etching operation (4-2d; ¶ [0056]), wherein the third etching operation removes a first portion (layer 61; ¶ [0056]) of the third material; performing a fourth etching operation (¶ [0046]), wherein the fourth etching operation removes a second portion (the portion of the blanket deposited metal film 5 not patterned into signal lines and electrodes {¶ [0046-47]) of the second material; and performing a fifth etching operation (Third Etching (c), {4-2c}; Fig 5; ¶ [0040-42, {0055}]), wherein the fifth etching operation removes a second portion (as shown in Fig 5 and described in ¶ [0040-42]) of the first material. Regarding claim 3, Masahiko discloses the method of claim 1, wherein removing the first portion of the first material (4; Fig 3) exposes a portion of a bottom surface of a fourth material (resist pattern 9; Fig 3; ¶ [0051-52]) comprising a photoresist layer, the portion of the bottom surface of the fourth material corresponding to an overhung region of the fourth material (as shown in Fig 3, and in a specific example, 0.2 µm side etching {beneath the overhung resist pattern 9}; ¶ [0031-32]). Regarding claim 4, Masahiko discloses the method of claim 1, wherein removing the first portion of the second material (5; Fig 4) exposes a portion of a bottom surface of the first material (4; Fig 4), the portion of the bottom surface of the first material corresponding to an overhung region of the first material (as shown in Fig 4; and, film 4 is about 0.2 µm interior to an edge of film 9, while film 5 is about 0.9 µm from the same edge of film 9; ¶ [0031-32, 0037]) Regarding claim 5, Masahiko discloses the method of claim 4, wherein removing the second portion of the first material (4; Fig 5) comprises removing at least the overhung region of the first material (as shown in Fig 5 versus Fig 4; the “eaves portion”; ¶ [0041]). Regarding claim 8, Masahiko discloses the method of claim 1, wherein removing the first portion of the first material, the first portion of the second material, and the first portion of the third material forms an inverted staircase structure in the stack of materials. (The removing the first portion of the first material and the first portion of the second material form the structure shown in Fig. 4, where films 9 and 4 form an inverted staircase structure. The removing the first portion of the third material is done in a sequence such that it does not contribute to the inverted staircase structure of films 9, and 4; however, the consequence of the removing of each of the first portions would result in the same inverted staircase structure of films 9, and 4; in this regard, the limitation is considered met.) Claims 1-2, 9, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Machida, Masahiko et al. (JP 2002/110631-A; hereinafter Masahiko) (2nd interpretation). Regarding claim 1 (2nd interpretation), Masahiko discloses a method (in particular, ¶ [0020-42, 0043-57]; entire document) comprising: forming a stack of materials on a semiconductor substrate (¶ [0044-51]), the stack of materials comprising a first material (ITO Film 4; Fig 3; ¶ [0027], a second material (metal film 5; Fig 3; ¶ [0027]), and a third material (6, comprising 61,62,63; Fig 3; ¶ [0045]); performing a first etching operation (First Etching (a), {4-2a}; Fig 3; ¶ [0027-32, {0052}]), wherein the first etching operation removes a first portion (as shown in Fig 3 and described in ¶ [0027-32]) of the first material; performing a second etching operation (Second Etching (b), {4-2b}); Fig 4; ¶ [0033-39, {0054}]), wherein the second etching operation removes a first portion (as shown in Fig 4 and described in ¶ [0033-37]) of the second material; performing a third etching operation (4-2d; ¶ [0056]), wherein the third etching operation removes a first portion (layer 61; ¶ [0056]) of the third material; performing a fourth etching operation (Third Etching (c), “overhanging portions” of metal film 5 after Second Etching (b) can be removed by the third etching; ¶ [0040]), wherein the fourth etching operation removes a second portion (“overhanging portions”) of the second material; and performing a fifth etching operation (Third Etching (c), {4-2c}; Fig 5; ¶ [0040-42, {0055}]), wherein the fifth etching operation removes a second portion (as shown in Fig 5 and described in ¶ [0040-42]) of the first material. Regarding claim 2, Masahiko discloses the method of claim 1 (2nd interpretation), further comprising: forming a fourth material (resist pattern 9; Fig 3; ¶ [0051-52]) on a surface of the first material, wherein a position of the fourth material is static for a duration of the first etching operation, the second etching operation, the third etching operation, the fourth etching operation, and the fifth etching operation (resist pattern 9 is not removed until after completion of 4-2a through 4-2d; ¶ [0057]). Regarding claim 9, Masahiko discloses the method of claim 1 (2nd interpretation), wherein removing the second portion of the second material and removing the second portion of the first material forms a staircase structure in the stack of materials. (As shown in Fig 5, film 5 forms a step below film 4, that is, a staircase structure.) Regarding claim 17, Masahiko discloses a product formed by a method (array substrate; in particular, ¶ [0020-42, 0043-57]; entire document) comprising: forming a stack of materials on a semiconductor substrate (¶ [0044-51]), the stack of materials comprising a first material (ITO Film 4; Fig 3; ¶ [0027], a second material (metal film 5; Fig 3; ¶ [0027]), and a third material (6, comprising 61,62,63; Fig 3; ¶ [0045]); performing a first etching operation (First Etching (a), {4-2a}; Fig 3; ¶ [0027-32, {0052}]), wherein the first etching operation removes a first portion (as shown in Fig 3 and described in ¶ [0027-32]) of the first material; performing a second etching operation (Second Etching (b), {4-2b}); Fig 4; ¶ [0033-39, {0054}]), wherein the second etching operation removes a first portion (as shown in Fig 4 and described in ¶ [0033-37]) of the second material; performing a third etching operation (4-2d; ¶ [0056]), wherein the third etching operation removes a first portion (layer 61; ¶ [0056]) of the third material; performing a fourth etching operation (Third Etching (c), “overhanging portions” of metal film 5 after Second Etching (b) can be removed by the third etching; ¶ [0040]), wherein the fourth etching operation removes a second portion (“overhanging portions”) of the second material; and performing a fifth etching operation (Third Etching (c), {4-2c}; Fig 5; ¶ [0040-42, {0055}]), wherein the fifth etching operation removes a second portion (as shown in Fig 5 and described in ¶ [0040-42]) of the first material. Regarding claim 18, Masahiko discloses the product formed by the method of claim 17, further comprising: forming a fourth material (resist pattern 9; Fig 3; ¶ [0051-52]) on a surface of the first material, wherein a position of the fourth material is static for a duration of the first etching operation, the second etching operation, the third etching operation, the fourth etching operation, and the fifth etching operation (resist pattern 9 is not removed until after completion of 4-2a through 4-2d; ¶ [0057]). Regarding claim 19, Masahiko discloses the product formed by the method of claim 17, wherein removing the first portion of the first material (4; Fig 3) exposes a portion of a bottom surface of a fourth material (resist pattern 9; Fig 3; ¶ [0051-52]) comprising a photoresist layer, the portion of the bottom surface of the fourth material corresponding to an overhung region of the fourth material (as shown in Fig 3, and in a specific example, 0.2 µm side etching {beneath the overhung resist pattern 9}; ¶ [0031-32]). Regarding claim 20, Masahiko discloses the product formed by the method of claim 17, wherein removing the first portion of the second material (5; Fig 4) exposes a portion of a bottom surface of the first material (4; Fig 4), the portion of the bottom surface of the first material corresponding to an overhung region of the first material (as shown in Fig 4; and, film 4 is about 0.2 µm interior to an edge of film 9, while film 5 is about 0.9 µm from the same edge of film 9; ¶ [0031-32, 0037]). Claims 1, 12-13, and 16 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Assal; Jerome et al. (US 2006/0094247; hereinafter Assal). Regarding claim 1 (3rd interpretation), Assal discloses a method comprising: forming a stack of materials on a semiconductor substrate (layer sequence 2; Fig 1; ¶ [0017]), the stack of materials comprising a first material (Ag layer 21; Fig 1; ¶ [0017]), a second material (Ni layer 22; Fig 1; ¶ [0017]), and a third material (Ti layer 23; Fig 1; ¶ [0017]); performing a first etching operation (first patterning step; Figs 1-2; ¶ [0018]), wherein the first etching operation removes a first portion (the portion of layer 21 no longer remaining in residual layer 211; Fig 2; ¶ [0018]) of the first material; performing a second etching operation (second patterning step; Figs 2-3; ¶ [0019]), wherein the second etching operation removes a first portion (the portion of layer 22 no longer remaining in residual layer 221; Fig 3; ¶ [0019]) of the second material; performing a third etching operation (third patterning step; Figs 3-4; ¶ [0020]), wherein the third etching operation removes a first portion (the portion of layer 23 no longer remaining in residual layer 231; Fig 4; ¶ [0020]) of the third material; performing a fourth etching operation (third patterning step; Figs 3-4; ¶ [0020]), wherein the fourth etching operation removes a second portion (the Ni layer 22 is overetched; ¶ [0020]) of the second material; and performing a fifth etching operation (third patterning step; Figs 3-4; ¶ [0020]), wherein the fifth etching operation removes a second portion (the portion of 211 no longer remaining in final layer 212; Fig 4; ¶ [0020]) of the first material. Regarding claim 12, Assal discloses the method of claim 1 (3rd interpretation), wherein the first material comprises silver (Ag, per claim 1), the second material comprises nickel (Ni, per claim 1), and the third material comprises titanium (Ti, per claim 1). Regarding claim 13, Assal discloses an apparatus comprising: a first material (Ag layer 21, comprising 212; Figs 1,4; ¶ [0017]) of a stack of materials, the first material corresponding to a first step of a staircase structure (212; Fig 4; stepped profile; ¶ [0008, 0020]) formed using an isotropic etching operation (chemical solution; ¶ [0020]), wherein a surface of the first step (upper horizontal surface of 212; Fig 4) is parallel to an x-direction (horizontal; Fig 4) and a z-direction (into the page; Fig 4), and wherein a height of the first step is parallel to a y-direction (vertical; Fig 4); a second material (Ni layer 22, comprising 221; Figs 1,4; ¶ [0017]) of the stack of materials, the second material corresponding to a second step of the staircase structure, the second step of the staircase structure located below the first step of the staircase structure with respect to the y-direction (as shown in Fig 4), wherein an extent of the second step extends beyond an extent of the first step with respect to the x-direction (as shown in Fig 4; stepped profile; ¶ [0020]); and a third material of the stack of materials (Ti layer 23, comprising 231; Figs 1,4; ¶ [0017]), the third material corresponding to a third step of the staircase structure, the third step of the staircase structure located below the second step of the staircase structure with respect to the y-direction (as shown in Fig 4), wherein an extent of the third step extends beyond the extent of the second step with respect to the x-direction (as shown in Fig 4; stepped profile; ¶ [0020]). Regarding claim 16, Assal discloses the apparatus of claim 13, wherein the first material comprises silver (Ag, per claim 13), the second material comprises nickel (Ni, per claim 13), and the third material comprises titanium (Ti, per claim 13). Claims 13-15 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Guyader; Francois et al. (US 2022/0037157 A1; hereinafter Guyader). Regarding claim 13 (2nd interpretation), Guyader discloses an apparatus comprising: a first material (31; Fig 2; ¶ [0054]) of a stack of materials, the first material corresponding to a first step of a staircase structure (Fig 2; ¶ [0057]) formed using an isotropic etching operation (chemical etching method, including Buffered Oxide Etch of silicon oxide; ¶ [0064-79]), wherein a surface of the first step (45; Fig 2; ¶ [0055]) is parallel to an x-direction (horizontal; Fig 2) and a z-direction (into the page; Fig 2), and wherein a height of the first step is parallel to a y-direction (vertical; Fig 3); a second material (29, having a thickness of 37nm; Fig 2; ¶ [0053]) of the stack of materials, the second material corresponding to a second step of the staircase structure, the second step of the staircase structure located below the first step of the staircase structure with respect to the y-direction (as shown in Fig 2), wherein an extent of the second step extends beyond an extent of the first step with respect to the x-direction (as shown in Fig 2; lateral edges 40 and 42 separated by a distance; ¶ [0054]); and a third material of the stack of materials (27, having a thickness of 25nm; Fig 2; ¶ [0052]), the third material corresponding to a third step of the staircase structure, the third step of the staircase structure located below the second step of the staircase structure with respect to the y-direction (as shown in Fig 2), wherein an extent of the third step extends beyond the extent of the second step with respect to the x-direction (as shown in Fig 2; lateral edges 38 and 40 separated by a distance; ¶ [0053]). Regarding claim 14, Guyader discloses the apparatus of claim 13 (2nd interpretation), further comprising: a semiconductor substrate (23; Fig 2; ¶ [0050]) corresponding to a fourth step of the staircase structure, the semiconductor substrate located below the third step (layer 27, comprising a step 41, as shown in Fig 2) of the staircase structure, wherein an extent of the fourth step extends beyond the extent of the third step with respect to the x-direction (by the step 39, as shown in Fig 2; ¶ [0052]). Regarding claim 15, Guyader discloses the apparatus of claim 13 (2nd interpretation), wherein a height of the second step of the staircase structure (37 nm, as per claim 13) is greater than a height of the third step of the staircase structure (25 nm, as per claim 13). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Machida, Masahiko et al. (JP 2002/110631-A; hereinafter Masahiko). Regarding claim 10, Masahiko discloses the method of claim 1 (2nd interpretation), but does not disclose further comprising: performing a rinsing operation subsequent to the first etching operation, the second etching operation, the third etching operation, the fourth etching operation, and the fifth etching operation; however, this would have been obvious to a person having ordinary skill in the art. One would have been motivated to do this for the following reasons: (1) each of steps 4-2a,4-2b,4-2c, corresponding to the first, second, fourth and fifth etching operations are done by aqueous solution (¶ [0052, 0054-55]), and one would have wanted to perform a post rinse following each etching operation in order to remove the aqueous etching solution and stop the etching, which is well-known in the art. As for the rinsing subsequent to the third etching operation (step 4-2d, performed using a mixed gas; ¶ [0056]), it would have been obvious that the subsequent (step 4-3; ¶ [0057]) removal of resist pattern 9 may be done by a wet stripping operation, including a rinsing operation, which is well-known in the art. One would have had a reasonable expectation of success in performing each rinsing, because these are well-known materials and processes in the art. Claims 6-7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Machida, Masahiko et al. (JP 2002/110631-A; hereinafter Masahiko) in view of Li; Yiming et al. (US 2011/0248405; hereinafter Lee). Regarding claim 6, Masahiko discloses the method of claim 1 (2nd interpretation), but does not disclose wherein removing the first portion of the third material (61; 4-2d; ¶ [0056]) exposes a portion of a bottom surface of the second material (metal film 5; Fig 3), the portion of the bottom surface of the second material corresponding to an overhung region of the second material. However, Masahiko does not indicate any directional criticality for the removing the first portion of the third material, indicating only that layer 61 be removed in order to separate drain (22) and source (23) electrodes (Fig 1; ¶ [0056]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the etching process used, for example an isotropic etch, may expose may a portion of a bottom surface of the second material, the portion of the bottom surface of the second material corresponding to an overhung region of the second material by the nature of the etching process. One may have been motivated to come to this conclusion, and to have used an isotropic etch, for reasons of cost savings and improved throughput as compared to an anisotropic etching process, as is known in the art (see also, for example, Li; ¶ [0003]), since Masahiko has listed these as reasons for the disclosure (¶ [0004-5]). One would have had a reasonable expectation of success because the etching process characteristics are well known in the art, as is the transistor structure (Masahiko; TFT; ¶ [0023]). Regarding claim 7, Masahiko discloses the method of claim 6, wherein removing the second portion of the second material (Third Etching (c), “overhanging portions” of metal film 5 after Second Etching (b) can be removed by the third etching; ¶ [0040]) comprises removing at least the overhung region of the second material (“overhanging portions”; ¶ [0040]). Regarding claim 11, Masahiko discloses the method of claim 1 (2nd interpretation), wherein the second etching operation comprises an isotropic etching operation (¶ [0039]). Masahiko does not disclose wherein each of the first etching operation, the third etching operation, the fourth etching operation, and the fifth etching operation comprise an isotropic etching operation; however, this would have been obvious to a person having ordinary skill in the art. First, Masahiko discloses that the first, fourth, and fifth etching operations each comprise an aqueous solution (¶ [0052, 0054-55]), and a person of ordinary skill in the would expect etching operations by aqueous solution to comprise isotropic etching operations. Second, Masahiko discloses that the third etching operation is performed by plasma etching. A person having ordinary skill in the art would know that plasma etching may be either anisotropic or isotropic depending upon particular processing parameters. One may have been motivated to use an isotropic etching operation for the third etching operation, for example, in order to attain a higher throughput and cost savings, as is known in the art (see also Li; ¶ [0003]), since Masahiko has listed these as reasons for the disclosure (¶ [0004-5]). One would have had a reasonable expectation of success because the materials and processes involved are well-known in the art. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Choi; Ju-il et al. (US 2019/0259718; the prior art discloses a pad structure comprising stack of materials including a staircase structure). Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRAD KNUDSON whose telephone number is (703)756-4582. The examiner can normally be reached Telework 9:30 -18:30 ET; M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /B.A.K./Examiner, Art Unit 2817 /ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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Prosecution Timeline

Jun 27, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.2%)
3y 5m
Median Time to Grant
Low
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