DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant’s arguments, see remarks, filed 06/08/2026, with respect to the rejection(s) of claim(s) 1-19 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of an updated prior art search.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3, 5-10 and 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoyama et al. (US-20210238442-A1 – hereinafter Aoyama) in view of Hashizume et al. (US-20210014978-A1 – hereinafter Hashizume), and further in view of Yoshida et al. (US-20120222890-A1 – hereinafter Yoshida).
Regarding claim 1, Aoyama teaches a method of manufacturing a wiring substrate, the manufacturing method comprising:
providing a conductive paste (¶0031) including a resin (¶0031), metal nanoparticles (¶0031) having a median diameter in a range of 10 nm to 500 nm (¶0033), and metal particles (¶0031) having a median diameter in a range of 1 μm to 10 μm (¶0013), wherein a ratio of a mass of the metal nanoparticles to a total mass of the metal nanoparticles and the metal particles is in a range of 5 mass% to 95 mass% (¶0035);
disposing (see Fig.2; ¶0096) the conductive paste (Fig.2 35; ¶0096) on at least a first surface (top surface) of an insulating base body (Fig.2 34; ¶0096) having the first surface (top surface) and a second surface (bottom surface) opposite to the first surface (top surface); and
forming a wiring layer (¶0031) by heat curing.
Aoyama does not teach forming the wiring layer by heating and pressurizing the conductive paste by using a roll press or a hard SUS plate, wherein in the forming the wiring layer, the conductive paste is heated and pressurized such that part of the wiring layer in a thickness direction is embedded in at least the first surface of the insulating base body,
wherein in the forming the wiring layer, the conductive paste is heated at a temperature in a range of 190°C to 300°C and pressurized at a pressure in a range of 2 MPa to 20 MPa, wherein the metal nanoparticles are a nano-copper powder, and wherein the metal particles are a copper powder.
Hashizume teaches forming a wiring layer (Fig.1 3; ¶0036 of Hashizume) by sintering (¶0032 of Hashizume) wherein the wiring layer (3 of Hashizume) is embedded (¶0032 of Hashizume) in a substrate (Fig.1 2; ¶0036 of Hashizume) and comprising copper nanoparticles (¶0029 of Hashizume).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the wiring layer by sintering (which requires high heat and pressure) and to embed the resulting wiring layer in the substrate as taught by Hashizume to arrive at the claimed invention. A practitioner would have been motivated to form the wiring layer by sintering because it is a well-known process for fabricating semiconductor devices. A practitioner would have been motivated to embed the wiring layer in the substrate for the benefit of causing an anchor effect to improve adhesion of the conductive pattern to the substrate. Additionally, copper is a well-known metal for use in fabricating conductive traces.
Aoyama in view of Hashizume does not explicitly teach forming a wiring layer by heating and pressurizing the conductive paste by using a roll press or a hard SUS plate, and wherein in the forming the wiring layer, the conductive paste is heated at a temperature in a range of 190°C to 300°C and pressurized at a pressure in a range of 2 MPa to 20 MPa.
Yoshida teaches the definition of sintering before the effective filing date of the claimed invention (¶0095 and Fig.2 of Yoshida), including temperatures between 200 and 250 degrees Celsius (¶0012 of Yoshida) and the use of a roll press (¶0111 of Yoshida).
This reference serves as evidence that the remaining limitations not explicitly taught by Aoyama in view of Hashizume are well-known in the art and do not patentably distinguish claim 1 over the prior art of record.
Regarding claim 3, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein in the providing the conductive paste, one or more surfaces of the metal particles are not covered with an aliphatic carboxylic acid (Aoyama in view of Hashizume, and further in view of Yoshida makes no mention of carboxylic acid, so the claim is assumed to be met).
Regarding claim 5, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein in the disposing the conductive paste, the insulating base body comprises a glass epoxy (bisphenol F type epoxy resin is cited in ¶0012 of Aoyama), a bismaleimide triazine resin, or a liquid crystal polymer (and could potentially be used in substrate 11, as the substrate material list in ¶0024 of Aoyama is non-limiting).
Regarding claim 6, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein in the forming the wiring layer, at least one surface of the insulating base body is deformed at a temperature in a range of 190°C to 300°C (¶0012 of Yoshida).
Regarding claim 7, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein after the conductive paste is disposed and before the wiring layer is formed, the conductive paste is covered with a polyimide sheet (¶0054 of Aoyama) or the hard SUS plate.
Regarding claim 8, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein in the providing the conductive paste, the conductive paste contains a solvent having a boiling point of 300°C or less (¶0086 of Aoyama).
Regarding claim 9, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 8, wherein in the providing the conductive paste, the solvent includes at least one of an alcohol, an ether (¶0086 of Aoyama), an ester, or an acrylic solvent having a hydrocarbon group having a carbon number of at least three.
Regarding claim 10, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 8, wherein in the providing the conductive paste, the solvent has the boiling point in a range of 150°C to 300°C (¶0086 of Aoyama).
Regarding claim 14, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not explicitly teach wherein in the forming the wiring layer , the conductive paste is heated and pressurized such that the wiring layer is embedded in the insulating base body by an amount in a range of 5 μm to 25 μm.
However, it would have been obvious to form the embedded wiring layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 15, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not explicitly teach wherein in the forming the wiring layer, the conductive paste is heated and pressurized such that the wiring layer is embedded in the insulating base body by an amount in a range of 1/100 to 6/100 of a thickness of the insulating base body.
However, it would have been obvious to form the embedded wiring layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 16, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not explicitly teach wherein in the forming the wiring layer, an upper surface of the wiring layer formed has flatness, and a difference in thickness between the thinnest portion and the thickest portion of the wiring layer is 3 μm or less.
However, it would have been obvious to form the wiring layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 17, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not explicitly teach wherein in the forming the wiring layer, an arithmetic average roughness Ra of an upper surface of the wiring layer formed is in a range of 10 nm to 100 nm.
However, it would have been obvious to form the upper surface of the wiring layer within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 18, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1, wherein in the forming the wiring layer, a plurality of the wiring layers are formed (wiring layers in substrates are known to include a plurality of wires to connect to a plurality of connections on a component like an LED).
The aforementioned combination does not explicitly teach wherein a distance between adjacent ones of the wiring layers is in a range of 30 μm to 5 cm.
However, it would have been obvious to form the wiring layers within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 19, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches a method of manufacturing a light-emitting device, the manufacturing method comprising: manufacturing the wiring substrate using the method according to claim 1; and mounting a light-emitting component on the wiring substrate (the prior art teaches a method of making a printed wiring board, and it is obvious to attach LEDs to printed wiring boards).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Uchida et al. (US-20160251531-A1 – hereinafter Uchida).
Regarding claim 2, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not teach wherein in the providing the conductive paste, the metal particles have a flat shape, and the metal particles have a ratio of a thickness to a maximum length in a plane direction that is in a range of 5 to 20.
Uchida teaches a conductive pattern comprising flat metal particles having a thickness to length ratio within the claimed range (abstract and ¶0011 of Uchida).
Shape differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. Additionally, the Applicant has presented no discussion in the specification which convinces the Examiner that the particular shape of the metal particles is anything more than one of numerous shapes a person of ordinary skill in the art would find obvious for the purpose of forming a wiring layer (In re Dailey, 149 USPQ 47 (CCPA 1976)). It appears that these changes produce no functional differences and therefore would have been obvious.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Brun (US-20230307341-A1).
Regarding claim 11, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida from claim 1 teaches the method according to claim 1.
The aforementioned combination does not teach wherein in the disposing the conductive paste, the insulating base body includes a through-hole, and the conductive paste is further disposed on the second surface of the insulating base body and in the through-hole, and in the forming the wiring layer, the conductive paste is heated and pressurized such that part of the wiring layer in the thickness direction is further embedded in the second surface of the insulating base body.
Brun teaches an insulating base body (Fig.1A 102; ¶0075 of Brun) comprising through holes and conductive metal (Fig.1A 122; ¶0081 of Brun) therethrough, with metal wiring layers (Fig.1A 114; ¶0075 of Brun) disposed on both the top and bottom surfaces of the insulating base body (102 of Brun).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, so use the methods taught by Aoyama in view of Hashizume, and further in view of Yoshida (see claim 1 rejection) to fabricate the interposer taught by Brun (Fig.1A of Brun) to arrive at the claimed invention. This combination is obvious because fabricating the interposer of Brun is a matter of design choice.
Regarding claim 12, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Brun from claim 11 teaches the method according to claim 11, wherein in the forming the wiring layer, the conductive paste disposed in the through-hole is also heated and pressurized (it would be obvious to use the same methods taught in claim 1 for all other metal wiring taught by Brun).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Brun, and further in view of Chen et al. (US-20230245991-A1 – hereinafter Chen).
Regarding claim 13, the aforementioned combination of Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Brun from claim 11 teaches the method according to claim 11.
The aforementioned combination does not teach wherein in the forming the wiring layer, the conductive paste is heated and pressurized such that, in a plan view of a portion of the wiring layer where the through-hole is formed, a diameter of a central portion of the through-hole in the thickness direction is larger than a diameter of the through-hole at the first surface of the insulating base body and a diameter of the through-hole at the second surface of the insulating base body.
Chen teaches a through hole filled with metal that is wider at the center than the top and bottom (Fig.19; ¶0084 of Chen).
It would have been obvious to one of ordinary skill to include the bulged via shape with the method taught by Aoyama in view of Hashizume, and further in view of Yoshida, and further in view of Brun because it is a matter of design choice (¶0014 of Chen).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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