DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/27/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 8-10, and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gocho et. al.(US-2021/040024-A1, hereinafter Gocho) , and further in view of JP295 (JP-2005/268295, hereinafter JP295).
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Regarding Claim 1.
Gocho teaches in Fig.1-3 and in related text A photoelectric conversion apparatus comprising:
a first substrate (#10) including a photoelectric conversion element (#12); and
a second substrate (#20) including an amplification transistor (Fig.2 #AMP) and a selection transistor (Fig.2 #SEL) connected electrically to a source of the amplification transistor, the amplification transistor being configured to amplify electrons that are a signal charge output from the photoelectric conversion element,
wherein the photoelectric conversion element includes an n-type semiconductor region configured to store the electrons,
Gocho does not explicitly disclose
wherein the amplification transistor and the selection transistor are each a p-type metal oxide semiconductor (p-type MOS) transistor.
However, JP295 explicitly teaches forming the pixel amplification transistor as a p-type MOS (PMOS) transistor, and further explains the advantages of PMOS over NNOS, particularly reduction of 1/f noise in pixel readout circuits. (See JP295 [0019-0023])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Gocho with the teachings of JP295, as identified above, because substituting a PMOS transistor for an NMOS transistor in a source-follower and selection configuration would have been a routine design medication motivated by known noise-reduction benefits which has no incompatibility with Gocho’s architecture.
Regarding Claim 2.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho also teaches wherein the first substrate includes a transfer transistor (Fig.2 #TR transfer transistor) configured to transfer the electrons to the amplification transistor, and wherein the transfer transistor is an n-type metal oxide semiconductor (n-type MOS) transistor. (Fig.2 #TR transistor being nMOS is standard and implicit in its pixel structure)
Regarding Claim 5.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
JP295 teaches wherein a gate of the amplification transistor is formed of n-type polysilicon. (Fig.1 [0020])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Gocho and JP295 with the teachings of JP295, as identified above, as this is a well-known and conventional process choice in CMOS technology to control threshold voltage and device characteristics..
Regarding Claim 8.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho further teaches wherein the second substrate is layered on the first substrate. (Fig.1 first and second substrates are stacked)
Regarding Claim 9.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho further teaches wherein the first substrate includes a first semiconductor member including the photoelectric conversion element (Fig.7 #54) and includes a first insulation film (#53),
wherein the second substrate includes a second semiconductor member including a source region of the amplification transistor (#AMP in #21) and includes a second insulation film (#53) and
wherein the first semiconductor member, the first insulation film, the second semiconductor member, and the second insulation film are arranged in this order. (Fig.7 [0130-0131])
Regarding Claim 10.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho further teaches further comprising a third substrate (#30) including a logic circuit configured to process a pixel signal output from the amplification transistor. ([0156])
Regarding Claim 14.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 10,
Gocho further teaches wherein the third substrate is layered on the second substrate. (Fig.1 second and third substrates are stacked)
Regarding Claim 15.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho further teaches wherein the first substrate includes a floating diffusion portion, and a wiring structure penetrating through a depth position of the second substrate is electrically connected to the floating diffusion portion.(Fig.7 #FD and vertical wiring #47/#48 [0129-0131])
Regarding Claim 16.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 15,
Gocho further teaches wherein the wiring structure is electrically connected to a gate of the amplification transistor. (Fig.7 #FD and vertical wiring #47/#48 [0129-0131] amplifier gate coupling via vertical wiring)
Regarding Claim 17.
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Gocho modified by JP295 teaches An equipment comprising the photoelectric conversion apparatus according to claim 1,
Gocho further teaches in Fig.20 and in related text the equipment further comprising at least one of:
an optical apparatus configured to guide light to the photoelectric conversion apparatus;
a control apparatus (#36) configured to control the photoelectric conversion apparatus;
a processing apparatus (#34) configured to process a signal output from the photoelectric conversion apparatus;
a display apparatus configured to display information acquired by the photoelectric conversion apparatus;
a storage apparatus configured to store information acquired by the photoelectric conversion apparatus; and
a mechanical apparatus configured to operate based on information acquired by the photoelectric conversion apparatus. (See Gocho Fig.20 [0058-0061] contains at least one of the above apparatus)
Regarding Claim 18.
Gocho teaches in Fig.1-3 and in related text A layered structure comprising:
a first substrate (#10) including a photoelectric conversion element (#12); and
a second substrate (#20) including an amplification transistor (Fig.2 #AMP) and a selection transistor (Fig.2 #SEL) connected electrically to a source of the amplification transistor, the amplification transistor being configured to amplify electrons that are a signal charge output from the photoelectric conversion element,
wherein the photoelectric conversion element includes an n-type semiconductor region configured to store the electrons,
Gocho does not explicitly disclose
wherein the amplification transistor and the selection transistor are each a p-type MOS transistor.
However, JP295 explicitly teaches forming the pixel amplification transistor as a p-type MOS (PMOS) transistor, and further explains the advantages of PMOS over NNOS, particularly reduction of 1/f noise in pixel readout circuits. (See JP295 [0019-0023])
. It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify Gocho with the teachings of JP295, as identified above, because substituting a PMOS transistor for an NMOS transistor in a source-follower and selection configuration would have been a routine design medication motivated by known noise-reduction benefits which has no incompatibility with Gocho’s architecture.
Regarding Claim 19.
Gocho modified by JP295 teaches The layered structure according to claim 18,
Gocho further teaches in Fig.1 and Fig.20 further comprising a third substrate (#30) including a logic circuit configured to process a pixel signal output from the amplification transistor,
wherein the third substrate is layered on the second substrate. (Gocho Fig.1 & Fig.20 [0058-0062])
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Gocho et. al.(US-2021/040024-A1, hereinafter Gocho) , in view of JP295 (JP-2005/268295, hereinafter JP295), and further in view of Machida et. al. (US-2017/0280080-A1, hereinafter Machida).
Regarding Claim 6.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho also teaches in Fig.4 wherein the second substrate (#20/#24) includes a reset transistor (#RST) and a floating diffusion (FD) capacitance switching transistor (#FDG), and
Machina teaches wherein the reset transistor and the FD capacitance switching transistor are each an n-type MOS transistor. (See Machina [0064-0070])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Gocho and JP295 with the teaching of Machina, as identified above, because this is a conventional and well-understood implementation in MOS device and would have been an obvious design choice.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Gocho et. al.(US-2021/040024-A1, hereinafter Gocho) , in view of JP295 (JP-2005/268295, hereinafter JP295) and Machida et. al. (US-2017/0280080-A1, hereinafter Machida) and further in view of Asaba et. al. (US-2009/0189057-A1, hereinafter Asaba).
Regarding Claim 7.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho teaches wherein the second substrate includes a reset transistor and a FD capacitance switching transistor, and
Gocho modified by JP295 does not explicitly disclose
wherein the reset transistor and the FD capacitance switching transistor are metal oxide semiconductor (MOS) transistors of a different conductivity type from each other.
Machinda teaches the FD capacitance switching transistor is an n-type MOS transistor. (See [0064-0070])
Asaba teaches the reset transistor may be implemented as a p-type transistor. (See [0010])
It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Gocho and JP295 with the teaching of Machina, as identified above, in order to achieve known design tradeoffs to enhance noise characteristics, reset behavior and capacitance switching performance; and this is also a conventional and well-understood implementation in pixel circuit which yields predictable results.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gocho et. al.(US-2021-040024-A1, hereinafter Gocho) , in view of JP295 (JP-2005/268295, hereinafter JP295), and further in view of Zha et. al. (US-2023/0247325-A1, hereinafter Zha).
Regarding Claim 11.
Gocho modified by JP295 teaches The photoelectric conversion apparatus according to claim 1,
Gocho teaches wherein the second substrate includes a reset transistor, and a amplification transistor.
Gocho modified by JP295 does not explicitly disclose a first power supply voltage supplied to the reset transistor and a second power supply voltage supplied to the amplification transistor are different from each other.
However, Zha teaches a first power supply voltage (#Vrst) supplied to the reset transistor (#MRST) and a second power supply voltage (#Vdd) supplied to the amplification transistor (#MSF) are different from each other. (Zha clam 11)
. It would have been obvious to one of ordinary skill in the art at the effective filing date of the claimed invention to modify the combination of Gocho and JP295 with the teaching of Zha, as identified above, in order to control the reset level independently from the amplification operating points, and to improve the performance and pixel operation of the device.
Allowable Subject Matter
Claims 3-4 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the reset transistor and the FD capacitance switching transistor are each a p-type MOS transistor. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 4 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein a gate of the amplification transistor is formed of p-type polysilicon.These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claim 12 contains allowable subject matter, because the prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein the second substrate includes a reset transistor, and a first power supply voltage supplied to the reset transistor is greater than a reference voltage and smaller than a second power supply voltage supplied to the amplification transistor. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 13 contains allowable subject matter because they depend from claim 12 .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA W KAO whose telephone number is (703)756-4797. The examiner can normally be reached Monday-Friday 9am-5pm Pacific Time.
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/SOPHIA W KAO/Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817