DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
In particular, claims 17-20 are being interpreted under of 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim limitation “a means for selecting an interface component by performing a selection of a device interface component layout from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to an interface structure of a shared integrated circuit semiconductor device component;” as recited in claim 17 invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Paragraphs [0065]-[0078] appear to define the structures that are the means for performing the functions of claims 17-20. The above means do not appear to be specifically defined in these paragraphs. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because they are drawn to software per se.
As described above, these claims are being interpreted under 35 U.S.C. 112(f). All of the “means for” structures as found in paragraphs [0065]-[0078] that define what the means are for performing the functional limitations are “a software module of an EDA software”. See Paragraphs [0065], [0067]-[0068]. “a software module of an EDA software” is considered software per se and therefore does not fall into one of the four categories of patent eligible subject matter. See MPEP 2106.03.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 4, 6-12, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US PGPUB No. 2023/0153514 in view of Mohan US Patent No. 8,191,034.
In reference to claim 1, Zhang teaches a non-transitory computer readable medium, comprising instructions that when executed by a processor of a computing device cause the processor to (Paragraph [0075]):
select a device interface component layout for an integrated circuit (Paragraph [0086] generate an IC design layout, including bonding pads);
perform at least one compatibility verification process for a selected device interface component layout with regard to an environment of the component (Claim 6, verifying compatibility between the set of criteria and the design rule instruction macro, Paragraphs [0034-7] defining design rule macros, which would be performed on the bonding pads, Abstract set of criteria corresponding to an IC manufacturing process), wherein the device interface component comprises a number of contacts and is at a predetermined position in the integrated circuit semiconductor device (Paragraph [0086] IC design layout diagram is completed and therefore the bonding pad numbers and positions would be set); and
output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout (Claim 6, displaying the result of the verification).
Zhang does not teach wherein the device interface component layout for the integrated circuit semiconductor device is selected from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to a device interface component, wherein the device interface component is an interface structure of a shared integrated circuit semiconductor device component. Mohan teaches selecting a device interface component layout for an integrated circuit semiconductor device from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to a device interface component, wherein the device interface component is an interface structure of a shared integrated circuit semiconductor device component (Claim 1; a plurality of chip layout files, interconnect selected terminals of the first and second interfacing terminal layers, including a plurality of terminals for interconnection with another chip, and performing a structural integrity check, the structural integrity check including an interconnection survey between terminals of the first and second interfacing terminal layers; performing a functional integrity check, the functional integrity check including characterization of interconnections between terminals of the first and second interfacing terminal layers with respect to a predetermined signal and power map; and, identifying for a user, any terminals of the first and second interfacing terminal layers failing at least one of the structural and functional integrity checks.) Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to incorporate the teachings of Mohan for selecting a device interface component layout with the teachings of Zhang for verifying the selected device interface component layout with set of criteria corresponding to an IC manufacturing process because it would allow for a user to make the best informed selection of the device interface component layout.
In reference to claim 3, Zhang in view of Mohan teaches receiving the set of parameters as an input (Mohan, column 6, lines 11-22).
In reference to claim 4, Zhang in view of Mohan teaches receiving an input to select a single device interface component layout of the plurality of device interface component layouts. (Mohan, column 12, lines 32-46).
In reference to claim 6, Zhang in view of Mohan teaches wherein the environment of the device interface component comprises any one of at least one further device component and a safety requirement of the integrated circuit semiconductor device (Zhang, Paragraph [0020]).
In reference to claim 7, Zhang in view of Mohan teaches wherein the selection is performed based on a best fitting interface structure at the predetermined position (Mohan column 9, line 46 – column 10, line 5).
In reference to claim 8, Zhang in view of Mohan teaches wherein the output corresponds to instructions to form the shared integrated circuit semiconductor device component (Mohan column 9, line 46 – column 10, line 5).
In reference to claim 9, Zhang in view of Mohan teaches wherein each of the plurality of device interface component layouts is configured to connect an electrically functional portion of the integrated circuit semiconductor device with a package portion of the integrated circuit semiconductor device (Mohan column 9, line 46 – column 10, line 5).
In reference to claims 10-12, and 15 drawn to a system having all the same functional limitations as found in claims 1, 3, 4, and 6 respectively, the same rejections apply.
In reference to claim 14, Zhang in view of Mohan teaches wherein the device interface component layout is embedded in any one of a schematic view and a layout view of the integrated circuit semiconductor device (Mohan, Figure 10).
In reference to claim 16, Zhang in view of Mohan wherein the compatibility verification information provides coordinates relating to a position of the selected device interface component relative to the predetermined position in the integrated circuit semiconductor device (Mohan column 9, line 46 – column 10, line 5).
In reference to claims 17-20, drawn to means for performing all the same functional limitations as found in claims 1, 6, 7, 9, and 16, the same rejections apply.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang, US PGPUB No. 2023/0153514 in view of Mohan US Patent No. 8,191,034 and Allegrucci, US Patent No. 6,518,787.
In reference to claim 2, Zhang in view of Mohan teach claim 1 as described above. Mohan further teaches wherein the predetermined position corresponds to a cell in an electronic design automation program (column 10, line 60 – column 11, line 10). They do not teach wherein the cell is a programmable cell. Allegrucci teaches a programmable cell that comprises a bonding pad. Accordingly, it would have been obvious for one of ordinary skill in the art at the time of invention to use the programmable cell of Allegrucci as the cell with the predetermined position in an electronic design automation program as taught by Mohan in the generated IC design layout of Zhang because it would allow the I/O associated with the bonding pad to be programmable.
Allowable Subject Matter
Claims 5 and 13 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In reference to claims 5/13 in a medium/system comprising instructions that when executed by a processor of a computing device cause the processor to: select a device interface component layout for an integrated circuit semiconductor device from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to a device interface component, wherein the device interface component is an interface structure of a shared integrated circuit semiconductor device component; perform at least one compatibility verification process for the selected device interface component layout with regard to an environment of the device interface component, wherein the device interface component comprises a number of contacts and is at a predetermined position in the integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout, prior art of record does not teach or clearly suggest wherein the device interface component layout corresponds to any one of a size and shape of an estate of components of the device interface component, the number and position of electrical contacts of the device interface component, structural and electrical characteristics, and position of functional portions of the integrated circuit semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON BOWERS whose telephone number is (571)272-1888. The examiner can normally be reached Flex M-F 7am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/B.B/ Examiner, Art Unit 2851
/JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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