DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 10/21/2025, without traverse to prosecute the claims of Invention I, claims 1-22 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/28/2023 is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
[0087] (page 25 line 7) identifies 310 and 320 as “block masks” [0088] (page 25 line 12) and [0089] (page 25 line 19) call out 320 and 330 as “block masks”.
Appropriate correction is required.
For compact prosecution, the examiner interprets [0088] and [0089] to call out 310 and 320 when referencing “block masks”.
Claim Objections
Claim 15 objected to because of the following informalities:
Claim 15 starts with, “device of 11” replaced with --device of claim 11--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 11, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (TW 202303844 A) in view of Jaeger et al. (US 20210028067 A1).
Re Claim 1 Wu teaches a semiconductor device, comprising:
a plurality of first nanosheet fin structures (204, page 8 par 2) located in a dense array region (204a-204c) of a substrate (202, page 8 par 1); and
a plurality of first isolation trenches (203, page 8 par 3) between adjacent first nanosheet fin structures (204) of the plurality of first nanosheet fin structures (204), wherein the plurality of first isolation trenches (203, FIG. 5A) include:
a first trench isolation layer (208, page 8 par 3);
a protective liner formed (211a, page 9 par 3 “The isolation structure 211may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (such as SiON), silicon carbide (Such as SiOC), silicon carbon nitride (such as SiCN), fluorine-doped silicate glass (FSG),a dielectric material with a low dielectric constant, other suitable materials, or a combination of the foregoing materials. In some embodiments, isolation structure 211 has a similar or identical composition to that of isolation member 208 . Isolation structure 211may include a single layer structure or a multilayer structure as described herein, wherein isolation structure 211 includes sublayer 211b disposed over sublayer 211a.”) on top of the first trench isolation layer (208); and
a second trench isolation layer (211b) located above the protective liner (211a), wherein:
the protective liner (211a) separates the first trench isolation layer (208) from the second trench isolation layer (211b, FIG. 6A & 6C); and
Wu teaches the second trench isolation layer (211b) is formed from flowable chemical vapor deposition of silicon dioxide (page 9 last par, “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…Isolation structure 211 (or each sublayer thereof) may be deposited by any suitable method, such as chemical vapor deposition (CVD), flow chemical vapor deposition (FCVD)…”), but does not explicitly teach the first trench isolation layer is more dense than the second trench isolation layer.
Jaeger claim 14 states, “The method of claim 10, wherein the first dielectric includes a flowable chemical vapor deposited (FCVD) oxide, the second dielectric includes a nitride, and filling the cap opening with the third dielectric includes performing a high density plasma chemical vapor deposition (HDPCVD) of oxide.” Using HDPCVD to form the “third dielectric” (first trench isolation layer) and using FCVD to form the “first dielectric” (second trench isolation layer) will cause the first trench isolation layer is more dense than the second trench isolation layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jaeger into the structure of Wu since Jaeger teaches a finFETs semiconductor device.
The ordinary artisan would have been motivated to modify Jaeger in combination with Wu in the above manner for the motivation of using FCVD and HDPCVD for the two trench isolation layers to have different densities. Ideal density for the isolation layers is critical for the source and drain functionality in relation to the gate of the semiconductor device. [0003] states, “The gate cut isolation may also be in a location in which interconnects such as source/drain (S/D) contacts and/or lateral interconnects (wires) are desired.”
Re Claim 2 Wu in view of Jaeger teaches the semiconductor device of claim 1, wherein a first height of the first trench isolation layer (Wu, use height of 208) in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer (use height of 211) in the plurality of first isolation trenches (FIG. 6A).
Re Claim 3 Wu in view of Jaeger teaches the semiconductor device of claim 1, wherein the first trench isolation layer (Wu, 208, page 8 par 3, “The isolation member 208 may include silicon oxide (SiO and/or SiO .sub.2 )…” ) is formed from a first oxide and the second trench isolation layer (211b, page 9 par 3 , page 9 par 3 “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (such as SiON), silicon carbide (Such as SiOC), silicon carbon nitride (such as SiCN), fluorine-doped silicate glass (FSG),a dielectric material with a low dielectric constant, other suitable materials, or a combination of the foregoing materials. In some embodiments, isolation structure 211 has a similar or identical composition to that of isolation member 208 . Isolation structure 211may include a single layer structure or a multilayer structure as described herein, wherein isolation structure 211 includes sublayer 211b disposed over sublayer 211a.”) is formed from a second oxide.
Re Claim 4 Wu in view of Jaeger teaches the semiconductor device of claim 3, wherein the first oxide used to form the first trench isolation layer (Wu, 208) and the second oxide used to form the second trench isolation layer (Wu, 211b) are silicon dioxide (page 9 par 3, “The isolation structure 211may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…isolation structure 211 has a similar or identical composition to that of isolation member 208”).
Re Claim 5 Wu in view of Jaeger teaches the semiconductor device of claim 1, wherein the first trench isolation layer is formed from high density plasma chemical vapor deposition (Jaeger, 170, FIG.7, process can be repeated for multiple trenches) [0037] of silicon dioxide (use Wu, page 9 last par, “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 ), and the second trench isolation layer (Jaeger, 126, FIG. 2) [0030] is formed from flowable chemical vapor deposition of silicon dioxide (Jaeger [0030]).
Re Claim 6 Wu in view of Jaeger teaches the semiconductor device of claim 1, wherein the second trench isolation layer (Wu, 211) in the plurality of first isolation trenches is substantially coplanar with a bottom surface of a nanosheet portion of the plurality of first nanosheet fin structures (205/206, FIG. 7A, page 8 par 1 “In some examples, non-channel layer 205 and channel layer 206 may form nanosheets…”).
Re Claim 7 Wu in view of Jaeger teaches the semiconductor device of claim 1, wherein the protective liner (Wu, 11a) is further formed along respective sidewall portions the plurality of first isolation trenches (203) extending between a top surface of the first trench isolation layer (208) to a bottom surface of a nanosheet portion(205/206) of the plurality of first nanosheet fin structures (FIG. 6A).
Re Claim 11 Wu teaches a semiconductor device (200, page 5 par 4), comprising:
a plurality of first nanosheet fin structures (204a-c, FIG. 3A) located in a dense array region of a substrate (202, page 6 par 4); and
a plurality of first isolation trenches (203, page 8 par 3) between adjacent first nanosheet fin structures (204a/204b and 204b/204c) of the plurality of first nanosheet fin structures (204a-c), wherein the plurality of first isolation trenches (203) include:
a first trench isolation layer (208, page 8 par 3);
a protective liner (211a, page 9 par 3) formed on top of the first trench isolation layer (208); and
a second trench isolation layer (211b, page 9 par 3) located above the protective liner (211a), wherein:
the protective liner separates (211a) the first trench isolation layer (208) from the second trench isolation layer (211b, FIG. 6A).
Wu teaches the second trench isolation layer (211b) is formed from flowable chemical vapor deposition of silicon dioxide (page 9 last par, “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…Isolation structure 211 (or each sublayer thereof) may be deposited by any suitable method, such as chemical vapor deposition (CVD), flow chemical vapor deposition (FCVD)…”), but does not explicitly teach the first trench isolation layer is more dense than the second trench isolation layer.
Jaeger claim 14 states, “The method of claim 10, wherein the first dielectric includes a flowable chemical vapor deposited (FCVD) oxide, the second dielectric includes a nitride, and filling the cap opening with the third dielectric includes performing a high density plasma chemical vapor deposition (HDPCVD) of oxide.” Using HDPCVD to form the “third dielectric” (second trench isolation layer) and using FCVD to form the “first dielectric” (first trench isolation layer) will cause the second trench isolation layer is more dense than the first trench isolation layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jaeger into the structure of Wu since Jaeger teaches a finFETs semiconductor device.
The ordinary artisan would have been motivated to modify Jaeger in combination with Wu in the above manner for the motivation of using FCVD and HDPCVD for the two trench isolation layers to have different densities. Ideal density for the isolation layers is critical for the source and drain functionality in relation to the gate of the semiconductor device. [0003] states, “The gate cut isolation may also be in a location in which interconnects such as source/drain (S/D) contacts and/or lateral interconnects (wires) are desired.”
Re Claim 13 Wu in view of Jaeger teaches the semiconductor device of claim 11, wherein the first trench isolation layer (Wu, 208) is formed from a first oxide and the second trench isolation layer (211b) is formed from a second oxide (page 9 par 3, “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (such as SiON), silicon carbide ( Such as SiOC), silicon carbon nitride (such as SiCN), fluorine-doped silicate glass (FSG), a dielectric material with a low dielectric constant, other suitable materials, or a combination of the foregoing materials. In some embodiments, isolation structure 211 has a similar or identical composition to that of isolation member 208 . Isolation structure 211 may include a single layer structure or a multilayer structure as described herein, wherein isolation structure 211 includes sublayer 211b disposed over sublayer 211a.”).
Re Claim 14 Wu in view of Jaeger teaches the semiconductor device of claim 13, wherein the first oxide used to form the first trench isolation layer (Wu, 208) and the second oxide used to form the second trench isolation layer (Wu, 211b) are silicon dioxide (Page 9 par 3, “The isolation structure 211 may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (such as SiON), silicon carbide ( Such as SiOC), silicon carbon nitride (such as SiCN), fluorine-doped silicate glass (FSG), a dielectric material with a low dielectric constant, other suitable materials, or a combination of the foregoing materials. In some embodiments, isolation structure 211 has a similar or identical composition to that of isolation member 208 . Isolation structure 211 may include a single layer structure or a multilayer structure as described herein, wherein isolation structure 211 includes sublayer 211b disposed over sublayer 211a.”).
Re Claim 15 Wu in view of Jaeger teaches the semiconductor device of claim 11, wherein the first trench isolation layer (Wu, 208) in the plurality of first isolation trenches (203) is below with a bottom surface of a nanosheet portion (205) of the plurality of first nanosheet fin structures (204a-c, FIG. 6A).
Claims 8, 12, and 17-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (TW 202303844 A) in view of Jaeger et al. (US 20210028067 A1) and further in view of Zhan et al. (CN 114864493 A).
Re Claim 8 Wu in view of Jaeger teaches the semiconductor device of claim 1, but does not teach:
a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from at least one second nanosheet fin structure in an isolated region of the substrate, wherein:
the plurality of first isolation trenches are narrower than the second isolation trench; and
the second isolation trench includes the first trench isolation layer.
Zhan teaches a second isolation trench (361, page 7) separating the plurality of first nanosheet fin structures (322, 323, 324, page 6) in the dense array region (around 322, 323, 324) of the substrate from at least one second nanosheet fin structure (321) in an isolated region of the substrate (110, page 6), wherein:
the plurality of first isolation trenches (trenches 362 and 363) are narrower than the second isolation trench (361, FIG. 3); and
the second isolation trench (361) includes the first trench isolation layer (use 360, all trenches are filled with same material. Page 16, “In FIG. 4, the isolation regions 361-364 which may be shallow trench isolation (STI)regions are formed adjacent to the fins 321-325 and located between the fins 321-325. The isolation regions 361-364 may be formed by depositing an insulating material layer 360 between the substrate 110, the fins 321-325, and the nanostructures 22, 24, and depositing the insulating material layer 360 between the adjacent fins 321-325 and the nano structures 22, 24. insulating material layer 360 can be oxide, the oxide such as silicon oxide,”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Wu in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Wu in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 12 Wu in view of Jaeger teaches the semiconductor device of claim 11, but does not teach a first height of the first trench isolation layer in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer in the plurality of first isolation trenches.
Zhan teaches a first height of the first trench isolation layer (361, page 7) in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer (90, page 5, use height of layer on top surface of 361) in the plurality of first isolation trenches (FIG. 6A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Wu in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Wu in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 17 Wu in view of Jaeger teaches the semiconductor device of claim 11, but does not teach:
a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from at least one second nanosheet fin structure in an isolated region of the substrate, wherein:
the plurality of first isolation trenches are narrower than the second isolation trench; and
the second isolation trench includes the first trench isolation layer and the second trench isolation layer.
Zhan teaches a second isolation trench (361, page 7) separating the plurality of first nanosheet fin structures (322, 323, 324, page 6) in the dense array region of the substrate (110) from at least one second nanosheet fin structure (321) in an isolated region of the substrate (110), wherein:
the plurality of first isolation trenches (362 and 363) are narrower than the second isolation trench (361); and
the second isolation trench includes (361) the first trench isolation layer (use 361, page 16, “The isolation regions 361-364 may be formed by depositing an insulating material layer 360”) and the second trench isolation layer (90, page 17 par 3, FIG. 6A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Wu in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Wu in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 18 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 17, wherein the first trench isolation layer (Zhan, 362/363) in the plurality of first isolation trenches and the first trench isolation layer (361) in the second isolation trench have a same first height, and the second trench isolation layer (90) in the plurality of first isolation trenches (90 over 362/363) and the second trench isolation layer (90) in the second isolation trench (90 over 361) have a same second height (FIG. 6A).
Re Claim 19 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 17, wherein the first trench isolation layer (Zhan, 361) in the second isolation trench is below with a bottom surface of a nanosheet portion of the at least one second nanosheet (22C1, page 4) fin structure (FIG. 6D).
Re Claim 20 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 19, the second trench isolation layer in the second isolation trench (Zhan, 90 above 361) is substantially coplanar with the bottom surface of the nanosheet portion of the plurality of the at least one second nanosheet (22C1, page 4) fin structure (FIG. 6D).
Re Claim 21 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 17, wherein the protective liner (Zhan, 90) is further formed along respective sidewall portions the plurality of first isolation trenches (90 on sidewalls of 322, 323, and 324) and the second isolation trench (90 on 321 and 322 sidewalls) extending between a top surface of the first trench isolation layer (361, 362, and 263) to a bottom surface of a nanosheet portion (22C1) of the plurality of first nanosheet fin structures (322, 323, and 324) and the second nanosheet fin structure (321, FIG. 6D).
Claims 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (TW 202303844 A) in view of Jaeger et al. (US 20210028067 A1) and Zhan et al. (CN 114864493 A) and further in view of Lee et al. (US 20150200297 A1).
Re Claim 9 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 8, but does not teach a third height of the first trench isolation layer in the second isolation trench is equal to a first height of the first trench isolation layer in the plurality of first isolation trenches plus a second height of the second trench isolation layer in the plurality of first isolation trenches.
Lee teaches a third height of the first trench isolation layer in the second isolation trench (use 20 on right in 200 region) [0018] is equal to a first height of the first trench isolation layer in the plurality of first isolation trenches (use 20 on left in 100 region, process can be repeated for multiple trenches) plus a second height of the second trench isolation layer (use 16 on left in 100 region) in the plurality of first isolation trenches (FIG. 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Wu in view of Jaeger and Zhan since Lee teaches a semiconductor device with fin structures.
The ordinary artisan would have been motivated to modify Lee in combination with Wu in view of Jaeger and Zhan in the above manner for the motivation of optimally integrating isolation trenches to the ideal height in comparison to the 2 isolation layers to reach the smallest chip size possible and still achieve peak device performance. [0001] states, “Reductions in the size and inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades.”
Re Claim 22 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 17, but does not teach the protective liner completely surrounds the first trench isolation layer formed in the plurality of first isolation trenches and the second isolation trench.
Lee the protective liner (24A [0024] and 16 [0014]) completely surrounds the first trench isolation layer (use 20 in 100 region, [0018]) formed in the plurality of first isolation trenches and the second isolation trench (FIG. 8, process can be repeated for multiple trenches).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Wu in view of Jaeger and Zhan since Lee teaches a semiconductor device with fin structures.
The ordinary artisan would have been motivated to modify Lee in combination with Wu in view of Jaeger and Zhan in the above manner for the motivation of forming a liner completely surrounding the first isolation layer to help one control the stress applied to the isolation layer and device. [0016] states, “By adjusting formation process conditions, the material, and the treatment conditions of dielectric liner 16, dielectric liner 16 may apply a compressive stress, a tensile stress, or a neutral stress.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (TW 202303844 A) in view of Jaeger et al. (US 20210028067 A1) and Zhan et al. (CN 114864493 A) and further in view of Long et al. (CN 114975276 A).
Re Claim 10 Wu in view of Jaeger and Zhan teaches the semiconductor device of claim 8, but does not teach the first trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a nanosheet portion of the at least one second nanosheet fin structure.
Long teaches the first trench isolation layer (97, page 17 par 2) in the second isolation trench (86C, page 15 par 2) is substantially coplanar with a bottom surface of a nanosheet portion (52A, page 10 par 1) of the at least one second nanosheet fin structure (use fin stack to right of 86C, FIG. 13B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Long into the structure of Wu in view of Jaeger and Zhan since Long teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Long in combination with Wu in view of Jaeger and Zhan in the above manner for the motivation of having the first isolation layer in a trench be coplanar with a channel layer to optimally arrange the dielectric between the fins to optimize device performance and still not require the device to be larger than necessary. Page 2 par 4 states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistor, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area.”
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (TW 202303844 A) in view of Jaeger et al. (US 20210028067 A1) and further in view of Long et al. (CN 114975276 A).
Re Claim 16 Wu in view of Jaeger teaches the semiconductor device of claim 15, but does not teach the second trench isolation layer in the plurality of first isolation trenches is substantially coplanar with the bottom surface of the nanosheet portion of the plurality of first nanosheet fin structures.
Long teaches the second trench isolation layer (97’, page 5) in the plurality of first isolation trenches (86A and 86B, page 5) is substantially coplanar with the bottom surface of the nanosheet portion (54a, page 4) of the plurality of first nanosheet fin structures (FIG. 13B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Long into the structure of Wu in view of Jaeger since Long teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Long in combination with Wu in view of Jaeger in the above manner for the motivation of having the second trench isolation layer in a trench be coplanar with a channel layer to optimally arrange the dielectric between the fins to optimize device performance and still not require the device to be larger than necessary. Page 2 par 4 states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistor, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area.”
Conclusion
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 1/21/26