DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-14 and 16-18 and 20-21 and 23-34 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7, 11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1).
Re Claim 1 Su teaches a semiconductor device (FIG. 1G), comprising:
a plurality of first nanosheet fin structures (104) [0037] located in a dense array region (1041-4) of a substrate (102), the plurality of first nanosheet fin structures (104) each including a nanosheet portion (106 and 108) [0041] and a fin portion (102 portions directly under 104) located below the nanosheet portion (106 and 108); and
a plurality of first isolation trenches (FIG. 1A, open areas between 106 and 108 portions) between adjacent first nanosheet fin structures (104) of the plurality of first nanosheet fin structures (104), wherein the plurality of first isolation trenches (open areas between 106 and 108 portions) include:
a first trench isolation layer (129) [0071] located entirely below the nanosheet portions (106 and 08);
a protective liner (130) [0059] located on top of the first trench isolation layer (129) and entirely below the nanosheet portions (106 and 108); and
a second trench isolation layer (132) [0061] located on top of the protective liner (130) and entirely below the nanosheet portions (106 and 108), wherein:
the protective liner (130) separates the first trench isolation layer (129) from the second trench isolation layer (132, FIG. 1G).
Su does not teach the first trench isolation layer is more dense than the second trench isolation layer.
Jaeger claim 14 states, “The method of claim 10, wherein the first dielectric includes a flowable chemical vapor deposited (FCVD) oxide, the second dielectric includes a nitride, and filling the cap opening with the third dielectric includes performing a high density plasma chemical vapor deposition (HDPCVD) of oxide.” Using HDPCVD to form the “third dielectric” (first trench isolation layer) and using FCVD to form the “first dielectric” (second trench isolation layer) will cause the first trench isolation layer to be more dense than the second trench isolation layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jaeger into the structure of Wu since Jaeger teaches a finFETs semiconductor device.
The ordinary artisan would have been motivated to modify Jaeger in combination with Wu in the above manner for the motivation of using FCVD and HDPCVD for the two trench isolation layers to have different densities. Ideal density for the isolation layers is critical for the source and drain functionality in relation to the gate of the semiconductor device. [0003] states, “The gate cut isolation may also be in a location in which interconnects such as source/drain (S/D) contacts and/or lateral interconnects (wires) are desired.”
Re Claim 2 Su in view of Jaeger teaches the semiconductor device of claim 1, wherein a first height of the first trench isolation layer (Su, 129 parts in direct contact with walls of 102) in the plurality of first isolation trenches (regions between 106 and 108 regions) is greater than a second height of the second trench isolation layer (132) in the plurality of first isolation trenches (FIG. 1G).
Re Claim 3 Su in view of Jaeger teaches the semiconductor device of claim 1, wherein the first trench isolation layer (Su, 129, 128 is oxide as taught in [0058] from FIG. 1E becomes 129 in FIG. 1G) is composed of a first oxide (silicon oxide) and the second trench isolation layer (132) is composed of a second oxide (silicon oxide) [0061].
Re Claim 7 Su in view of Jaeger teaches the semiconductor device of claim 1, wherein the protective liner (Su, 130) is further located along sidewalls of the second trench isolation layer (132m FIG. 1G).
Re Claim 11 Su teaches a semiconductor device (FIG. 1G), comprising:
a plurality of first nanosheet fin structures (104) [0037] located in a dense array region (1042-4) of a substrate (102), the plurality of first nanosheet fin structures (104) each including a nanosheet region (106 and 108) [0041] and a fin region (102 portions directly under 104) located below the nanosheet region (106 and 108); and
a plurality of first isolation trenches (FIG. 1A, open areas between 1042-4) between adjacent first nanosheet fin structures (104) of the plurality of first nanosheet fin structures (104), wherein the plurality of first isolation trenches (open areas between 1042-4) include:
a first trench isolation layer (129) [0071] located entirely below the nanosheet portions (106 and 108);
a protective liner (130) [0059] located on top of the first trench isolation layer (129) and entirely below the nanosheet portions (106 and 108); and
a second trench isolation layer (132) [0061] located on top of the protective liner (130) and entirely below the nanosheet portions (106 and 108), wherein:
the protective liner (130) separates the first trench isolation layer (129) from the second trench isolation layer (132, FIG. 1G).
Su does not teach the second trench isolation layer is more dense than the first trench isolation layer.
Jaeger claim 14 states, “The method of claim 10, wherein the first dielectric includes a flowable chemical vapor deposited (FCVD) oxide, the second dielectric includes a nitride, and filling the cap opening with the third dielectric includes performing a high density plasma chemical vapor deposition (HDPCVD) of oxide.” Using HDPCVD to form the “third dielectric” (second trench isolation layer) and using FCVD to form the “first dielectric” (first trench isolation layer) will cause the second trench isolation layer to be more dense than the first trench isolation layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jaeger into the structure of Su since Jaeger teaches a finFETs semiconductor device.
The ordinary artisan would have been motivated to modify Jaeger in combination with Su in the above manner for the motivation of using FCVD and HDPCVD for the two trench isolation layers to have different densities. Ideal density for the isolation layers is critical for the source and drain functionality in relation to the gate of the semiconductor device. [0003] states, “The gate cut isolation may also be in a location in which interconnects such as source/drain (S/D) contacts and/or lateral interconnects (wires) are desired.”
Re Claim 13 Su in view of Jaeger teaches the semiconductor device of claim 11, wherein the first trench isolation layer (Su, 129, 128 is oxide as taught in [0058] from FIG. 1E becomes 129 in FIG. 1G) is composed of a first oxide (silicon oxide) and the second trench isolation layer (132) is composed of a second oxide (silicon oxide) [0061].
Claims 4-5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) as applied to claims 1 and 3 above, and further in view of Wu et al. (TW 202303844 A)
Re Claim 4 Su in view of Jaeger teaches the semiconductor device of claim 3, wherein the second oxide (Su, 132) is silicon dioxide [0061].
Su in view of Jaeger does not teach the first oxide is silicon dioxide.
Wu teaches the first oxide (208 in FIG. 15A, page 8 last par) is silicon dioxide (page 9 par 3, “The isolation structure 211may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…isolation structure 211 has a similar or identical composition to that of isolation member 208”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Su in view of Jaeger since Wu teaches a nanosheet device.
The ordinary artisan would have been motivated to modify Wu in combination with Su in view of Jaeger in the above manner for the motivation of forming the first trench isolation layer out of silicon dioxide to optimize the space available in the device size continues to scale down. Page 2 last par states, “Technological developments in the materials and design of integrated circuits (ICs) have created generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation.”
Re Claim 5 Su in view of Jaeger teaches the semiconductor device of claim 1, wherein the first trench isolation layer is formed from high density plasma chemical vapor deposition (Jaeger [0037], 170, FIG.7, process can be repeated for multiple trenches),
and the second trench isolation layer (Jaeger, [0030], 126, FIG. 2) is formed from flowable chemical vapor deposition of silicon dioxide [0030].
Su in view of Jaeger does not teach the first trench isolation layer is formed of silicon dioxide.
Wu teaches the first trench isolation layer (208) is formed of silicon dioxide (208 in FIG. 15A, page 9 par 3, “The isolation structure 211may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…isolation structure 211 has a similar or identical composition to that of isolation member 208”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Su in view of Jaeger since Wu teaches a nanosheet device.
The ordinary artisan would have been motivated to modify Wu in combination with Su in view of Jaeger in the above manner for the motivation of forming the first trench isolation layer out of silicon dioxide to optimize the space available in the device size continues to scale down. Page 2 last par states, “Technological developments in the materials and design of integrated circuits (ICs) have created generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation.”
Re Claim 14 Su in view of Jaeger teaches the semiconductor device of claim 13, wherein the second oxide (Su, 132) is silicon dioxide [0061].
Su in view of Jaeger does not teach the first oxide is silicon dioxide.
Wu teaches the first oxide (208 in FIG. 15A, page 8 last par) is silicon dioxide (page 9 par 3, “The isolation structure 211may include any suitable material, such as silicon oxide (SiO and/or SiO .sub.2 )…isolation structure 211 has a similar or identical composition to that of isolation member 208”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Su in view of Jaeger since Wu teaches a nanosheet device.
The ordinary artisan would have been motivated to modify Wu in combination with Su in view of Jaeger in the above manner for the motivation of forming the first trench isolation layer out of silicon dioxide to optimize the space available in the device size continues to scale down. Page 2 last par states, “Technological developments in the materials and design of integrated circuits (ICs) have created generations of integrated circuits, each generation having smaller and more complex circuits than the previous generation.”
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) as applied to claims 1 above, and further in view of Xie (US 10998234 B2).
Re Claim 6 Su in view of Jaeger teaches the semiconductor device of claim 1, but does not teach the second trench isolation layer in the plurality of first isolation trenches is substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the plurality of first nanosheet fin structures.
Xie teaches the trench isolation layer (218, col 6 line 53) in the plurality of first isolation trenches (left and right 218 in FIG. 3B) is substantially coplanar with a bottom surface of a sacrificial isolation layer (212, col 5 line 1) located between the nanosheet portion (206, col 4 line 63) and the fin portion of the plurality of first nanosheet fin structures (elevated part of substrate 204 in FIG. 3B).
Integrating Xie into Su in view of Jaeger would lead one to form the second trench isolation layer in the plurality of first isolation trenches to be substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the plurality of first nanosheet fin structures.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xie into the structure of Su in view of Jaeger since Xie teaches a gate all around nanosheet device.
The ordinary artisan would have been motivated to modify Xie in combination with Su in view of Jaeger in the above manner for the motivation of optimally integrating a sacrificial isolation layer located between the nanosheet portion and the fin portion around the isolation structure to build a semiconductor device that functions at a peak level. Col 1 line 30 states, “The wrap-around gate structures and source/drain contacts used in nanosheet devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.”
Re Claim 16 Su in view of Jaeger teaches the semiconductor device of claim 11, but does not teach the second trench isolation layer in the plurality of first isolation trenches is substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the plurality of first nanosheet fin structures.
Xie teaches the trench isolation layer (218, col 6 line 53) in the plurality of first isolation trenches (left and right 218 in FIG. 3B) is substantially coplanar with a bottom surface of a sacrificial isolation layer (212, col 5 line 1) located between the nanosheet portion (206, col 4 line 63) and the fin portion of the plurality of first nanosheet fin structures (elevated part of substrate 204 in FIG. 3B).
Integrating Xie into Su in view of Jaeger would lead one to form the second trench isolation layer in the plurality of first isolation trenches to be substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the plurality of first nanosheet fin structures.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xie into the structure of Su in view of Jaeger since Xie teaches a gate all around nanosheet device.
The ordinary artisan would have been motivated to modify Xie in combination with Su in view of Jaeger in the above manner for the motivation of optimally integrating a sacrificial isolation layer located between the nanosheet portion and the fin portion around the isolation structure to build a semiconductor device that functions at a peak level. Col 1 line 30 states, “The wrap-around gate structures and source/drain contacts used in nanosheet devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.”
Claims 8, 12, 17-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) as applied to claims 1, 11 above, and further in view of Zhan et al. (CN 114864493 A).
Re Claim 8 Su in view of Jaeger teaches the semiconductor device of claim 1, but does not teach:
a second isolation trench separating the plurality of first nanosheet fin structures in the dense array region of the substrate from at least one second nanosheet fin structure in an isolated region of the substrate, wherein:
the plurality of first isolation trenches are narrower than the second isolation trench; and
the second isolation trench includes the first trench isolation layer.
Zhan teaches a second isolation trench (361, page 7) separating the plurality of first nanosheet fin structures (322, 323, 324, page 6) in the dense array region (around 322, 323, 324) of the substrate from at least one second nanosheet fin structure (321) in an isolated region of the substrate (110, page 6), wherein:
the plurality of first isolation trenches (trenches 362 and 363) are narrower than the second isolation trench (361, FIG. 3); and
the second isolation trench (361) includes the first trench isolation layer (use 360, all trenches are filled with same material. Page 16, “In FIG. 4, the isolation regions 361-364 which may be shallow trench isolation (STI)regions are formed adjacent to the fins 321-325 and located between the fins 321-325. The isolation regions 361-364 may be formed by depositing an insulating material layer 360 between the substrate 110, the fins 321-325, and the nanostructures 22, 24, and depositing the insulating material layer 360 between the adjacent fins 321-325 and the nano structures 22, 24. insulating material layer 360 can be oxide, the oxide such as silicon oxide,”).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Su in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Su in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 12 Su in view of Jaeger teaches the semiconductor device of claim 11, but does not teach a first height of the first trench isolation layer in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer in the plurality of first isolation trenches.
Zhan teaches a first height of the first trench isolation layer (361, page 7) in the plurality of first isolation trenches is greater than a second height of the second trench isolation layer (90, page 5, use height of layer on top surface of 361) in the plurality of first isolation trenches (FIG. 6A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Su in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Su in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 17 Su in view of Jaeger teaches the semiconductor device of claim 11, further comprising:
a second isolation trench (open area between 1041-2) separating the plurality of first nanosheet fin structures (1042-4) in the dense array region of the substrate (102) from at least one second nanosheet fin structure (1041) in an isolated region of the substrate (102), but does not teach:
the plurality of first isolation trenches are narrower than the second isolation trench; and
the second isolation trench includes the first trench isolation layer, the second trench isolation layer, and the protective liner separating the first trench isolation layer from the second trench isolation layer.
Zhan the plurality of first isolation trenches (362 and 363) are narrower than the second isolation trench (361); and
the second isolation trench (361) includes the first trench isolation layer (362 and 363, 361-364 are insulating material layer 360, page 16 par 1), the second trench isolation layer (43, page 9 par 3), and the protective liner (90) separating the first trench isolation layer (360 in 361) from the second trench isolation layer (43, FIG. 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Zhan into the structure of Su in view of Jaeger since Zhan teaches a device with nanosheet fin structures.
The ordinary artisan would have been motivated to modify Zhan in combination with Su in view of Jaeger in the above manner for the motivation of Optimally integrating isolation trenches between nanosheet fin stacks is critical for micro scaling semiconductor designs and still allowing the device to function at a peak level. Page 2 par 3 states, “The process of microscaling (scaling down) typically provides benefits by increasing the production efficiency and reducing the cost of correlation.”
Re Claim 18 Su in view of Jaeger and Zhan teaches the semiconductor device of claim 17, wherein the first trench isolation layer (Zhan, 360) in the plurality of first isolation trenches (362 and 363) and the first trench isolation layer (360) in the second isolation trench (361) have a same first height, and the second trench isolation layer (43) in the plurality of first isolation trenches (362/363) and the second trench isolation layer (43) in the second isolation trench (361) have a same second height (FIG. 7).
Re Claim 21 Su in view of Jaeger and Zhan teaches the semiconductor device of claim 17, further comprising a second protective liner (Su, 150) [0079] located along sidewalls of the fin regions of the plurality of first nanosheet fin structures (1042-4) in the dense array region of the substrate (102) and the at least one second nanosheet fin structure (1041) in the isolated region of the substrate (FIG. 1I).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) and Zhan (CN 114864493 A) as applied to claims 1 and 8 above, and further in view of Lee et al. (US 20150200297 A1).
Re Claim 9 Su in view of Jaeger and Zhan teaches the semiconductor device of claim 8, but does not teach a third height of the first trench isolation layer in the second isolation trench is equal to a first height of the first trench isolation layer in the plurality of first isolation trenches plus a second height of the second trench isolation layer in the plurality of first isolation trenches.
Lee teaches a third height of the first trench isolation layer in the second isolation trench (use 20 on right in 200 region) [0018] is equal to a first height of the first trench isolation layer in the plurality of first isolation trenches (use 20 on left in 100 region, process can be repeated for multiple trenches) plus a second height of the second trench isolation layer (use 16 on left in 100 region) in the plurality of first isolation trenches (FIG. 5).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Su in view of Jaeger and Zhan since Lee teaches a semiconductor device with fin structures.
The ordinary artisan would have been motivated to modify Lee in combination with Su in view of Jaeger and Zhan in the above manner for the motivation of optimally integrating isolation trenches to the ideal height in comparison to the 2 isolation layers to reach the smallest chip size possible and still achieve peak device performance. [0001] states, “Reductions in the size and inherent features of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) and Zhan (CN 114864493 A) Lee et al. (US 20150200297 A1) as applied to claims 1 and 8 and 9 above, and further in view of Xie (US 10998234 B2).
Re Claim 10 Su in view of Jaeger and Zhan and Lee teaches the semiconductor device of claim 8, but does not teach the first trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the at least one second nanosheet fin structure.
Xie teaches the first trench isolation layer (218, col 6 line 53) in the second isolation trench (process can be repeated, left and right 218 in FIG. 3B) is substantially coplanar with a bottom surface of a sacrificial isolation layer (212, col 5 line 1) located between the nanosheet portion (206, col 4 line 63) and the fin portion of the at least one second nanosheet fin structure (elevated part of substrate 204 in FIG. 3B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xie into the structure of Su in view of Jaeger and Zhan and Lee since Xie teaches a gate all around nanosheet device.
The ordinary artisan would have been motivated to modify Xie in combination with Su in view of Jaeger and Zhan and Lee in the above manner for the motivation of optimally integrating a sacrificial isolation layer located between the nanosheet portion and the fin portion around the isolation structure to build a semiconductor device that functions at a peak level. Col 1 line 30 states, “The wrap-around gate structures and source/drain contacts used in nanosheet devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 20230034360 A1) in view of Jaeger et al. (US 20210028067 A1) and Zhan et al. (CN 114864493 A) as applied to claims 17 above, and further in view of Xie (US 10998234 B2).
Re Claim 20 Su in view of Jaeger and Zhan teaches the semiconductor device of claim 17, but does not teach the second trench isolation layer in the second isolation trench is substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the at least one second nanosheet fin structure.
Xie teaches the trench isolation layer (218, col 6 line 53) in the plurality of second isolation trenches (process can be repeated, left and right 218 in FIG. 3B) is substantially coplanar with a bottom surface of a sacrificial isolation layer (212, col 5 line 1) located between the nanosheet portion (206, col 4 line 63) and the fin portion of the plurality of first nanosheet fin structures (elevated part of substrate 204 in FIG. 3B).
Integrating Xie into Su in view of Jaeger and Zhan would lead one to form the second trench isolation layer in the plurality of second isolation trenches to be substantially coplanar with a bottom surface of a sacrificial isolation layer located between the nanosheet portion and the fin portion of the plurality of first nanosheet fin structures.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Xie into the structure of Su in view of Jaeger and Zhan since Xie teaches a gate all around nanosheet device.
The ordinary artisan would have been motivated to modify Xie in combination with Su in view of Jaeger and Zhan in the above manner for the motivation of optimally integrating a sacrificial isolation layer located between the nanosheet portion and the fin portion around the isolation structure to build a semiconductor device that functions at a peak level. Col 1 line 30 states, “The wrap-around gate structures and source/drain contacts used in nanosheet devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.”
Response to Arguments
Applicant’s arguments with respect to claims 1-14,16-18 and 20-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 7/1/26
Prosecution Insights