Prosecution Insights
Last updated: October 02, 2026
Application No. 18/342,873

SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Jun 28, 2023
Priority
Aug 26, 2022 — JP 2022-134907
Examiner
RAMOS-DIAZ, FERNANDO JOSE
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+14.4% vs TC avg
Minimal +2% lift
Without
With
+1.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
23 currently pending
Career history
60
Total Applications
across all art units

Statute-Specific Performance

§103
44.5%
+4.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
17.6%
-22.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§103 §112
DETAILED ACTION/EXAMINER’S COMMENT This Office action responds to the amendments filed on 06/01/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status Applicant’s response filed on 06/01/2026 in reply to the final rejection mailed on 04/01/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claim 6 is cancelled. Accordingly, pending in this Office action are claims 1-3, 5, & 7-20. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 16 & 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The limitation of Claim 16 “a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer” and the limitation of Claim 19 “a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer” are repeat limitations to the newly amended claim 1. The amended limitation “a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer” in lines 17-18 of Claim 1 is repeated in both Claim 16 and Claim 19. The repeated language of the limitations render Claims 16 & 19 unclear as to whether another part of the case is meant to be described. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5, 7, & 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kaji (US 20220223546) in view of Kotani (US 20110031584) & Nogawa (US 20210305144) as evidenced by MatWeb (matweb.com). Regarding Claim 1, Kaji (see, e.g., fig. 1) shows a semiconductor device comprising: a resin insulated substrate (41, 21, & 31) including a first resin insulating layer 41 (see, e.g., para.0021) including a first resin (acrylic resin), a conductor base 21 (see, e.g., para.0024) provided on a first main surface of the first resin insulating layer (bottom surface of 41), and a conductor foil 31 (see, e.g., para.0019) provided in direct contact with a second main surface of the first resin insulating layer (top surface of 41) opposite the first main surface, the first resin insulating layer extended along an entire surface of the conductor foil and interposed between the conductor base and the conductor foil (see, e.g., fig. 1); a power semiconductor element 71 (see, e.g., para.0018) bonded to the conductor foil; a case 61 (see, e.g., para.0028) surrounding an outer circumference of the resin insulated substrate (see, e.g., fig. 2); a sealing resin 77 (see, e.g., para.0030) provided inside the case to seal the power semiconductor element: and a second resin insulating layer 51 (see, e.g., para.0022) including a second resin (polyimide resin), and provided between the first resin insulating layer and the sealing resin (see, e.g., fig. 1), wherein a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer (see, e.g., para.0028), and the second resin insulating layer is not interposed between the conductor foil and the first resin insulating layer (see, e.g., fig. 1). Kaji, however, fails to show the second resin insulating layer having a water-absorption rate that is less than a water absorption rate of the sealing resin and is less than a water-absorption rate of the first resin insulating layer the second resin insulating layer is provided to cover entire side surfaces of the adhesive layer along an inside of the case, Kotani (see, e.g., para.0006-0007, para.0048), in a similar device to Kaji, teaches that the second resin insulating layer 10 (polyimide resin) having a water-absorption rate that is less than a water absorption rate of the sealing resin 12 would prevent short circuiting caused by electromigration between wiring lines. It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the second resin insulating layer 10 having a water-absorption rate that is less than a water absorption rate of the sealing resin 12 (epoxy resin) of Kotani in the device of Kaji to prevent short circuiting caused by electromigration between wiring lines. Kaji, in view of Kotani, however, fails to show the second resin insulating layer having a water-absorption rate that is less than a water-absorption rate of the first resin insulating layer the second resin insulating layer is provided to cover entire side surfaces of the adhesive layer along an inside of the case, The water absorption rates of various polyimide resins for the second resin insulating layer 51, made of polyimide resin (0.04%, see, e.g., matweb.com, Overview of Materials for Polyimide), and the first resin insulating layer 41, made of acrylic resin (0.3%, see, e.g., matweb.com, Overview of Materials for Acrylic, General Purpose, Molded), are known as evidenced by MatWeb. Regarding the priority date of the reference MatWeb, see MPEP 2112 (II) for inherent features of the materials used in the application. Kaji (see, e.g., para.0028), in view of Kotani as evidenced by MatWeb, states there is an adhesive layer to bond the case to the semiconductor device but fails to explicitly show the configuration the second resin insulating layer is provided to cover entire side surfaces of the adhesive layer along an inside of the case, Nogawa (see, e.g., fig. 3, para.0033-0034), in a similar device to Kaji, in view of Kotani as evidenced by MatWeb, shows a configuration for an adhesive layer 16 bonding a case 40 in a semiconductor device 50. The adhesive of layer of Nogawa is incorporated into the device of Kaji, in view of Kotani as evidenced by MatWeb, as shown in annotated figure 1. Nogawa (see, e.g., para.0056) states the case 40 would improve the strength and reduce deterioration of the reliability of the semiconductor device 50. By incorporating the adhesive layer 16 of Nogawa into the device of Kaji, in view of Kotani as evidenced by MatWeb, the adhesive layer would be positioned such that the second resin insulating layer 51 is provided to cover entire side surfaces of the adhesive layer 16 inside the case 61. The second resin insulating layer 51 covers entire vertical side surfaces of the adhesive layer 16 since 16 is positioned in the corners of the device between the case 61, first resin insulating layer 41, and second resin insulating layer 51 (see, e.g., annotated figure 1). PNG media_image1.png 567 995 media_image1.png Greyscale It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the adhesive layer of Nogawa into the device of Kaji, in view of Kotani as evidenced by MatWeb, because the combination would improve the strength and reduce deterioration of the reliability of the semiconductor device. Regarding Claim 2, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 (see, e.g., para.0022) includes at least one kind of resin selected from liquid crystal polymer, silicone, polyamide imide, polyimide, and para-xylene polymer. Regarding Claim 3, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the first resin insulating layer 41 further includes filler (see, e.g., para.0021). Regarding Claim 5, Kaji (see, e.g., fig. 1, annotated figure 2), in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 has a thickness that is smaller than a thickness of the conductor foil 31 (see, e.g., annotated figure 2). Since Applicant has not established a direction for thickness, the thicknesses of the second resin insulating layer and conductor foil are interpreted as shown in annotated figure 2. PNG media_image2.png 534 859 media_image2.png Greyscale Regarding Claim 7, Kaji (see, e.g., fig. 1), in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 is selectively provided at a position in contact with a side surface of the conductor foil 31 (between 31a & 31b, see, e.g., fig. 1). Regarding Claim 10, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein: the power semiconductor element 71 is bonded to the conductor foil 31 with a bonding material 81 (see, e.g., para.0018) interposed: and the second resin insulating layer 51 has a greater thickness than a total of a thickness of the conductor foil 31 and a thickness of the bonding material 81 (see, e.g., annotated figure 3). Since Applicant has not established a direction for thickness, the thicknesses of the second resin insulating layer and conductor foil are interpreted as shown in annotated figure 3. PNG media_image3.png 740 897 media_image3.png Greyscale Regarding Claim 11, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, however, fails to show wherein the second resin insulating layer 51 further includes a plurality of resin insulating layers. Although Kaji, in view of Kotani & Nogawa as evidenced by MatWeb fail to show the plurality of resin insulating layers, the duplication of parts is an obvious modification of the device absent reason to believe a new and unexpected result is produced. See MPEP 2144.04 (VI)(B), In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.) Therefore, the prior record of art renders claim 11 obvious. Regarding Claim 12, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the first resin and the second resin are a same resin (polyimide resin, see, e.g., para.0021-0022). Although Examiner has elected the first resin to be acrylic and the second resin to be polyimide resin, Kaji (see, e.g., para.0021-0022) states both these resins are “thermoplastic resin.” Therefore the limitation is rendered obvious because they are both thermoplastic resins. Regarding Claim 13, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 further includes filler (see, e.g., para.0022). Regarding Claim 14, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 13, a filled percentage of the first resin insulating layer is greater than a filled percentage of the second resin insulating layer. MatWeb (see, e.g., matweb.com, Overview of Materials for Polyimide) states the polyimide resin can have a filler percentage between 0-40%. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to arrive at the limitation a filled percentage of the first resin insulating layer (Polyimide) is greater than a filled percentage of the second resin insulating layer (Polyimide) through routine experimentation of the various filler percentages of polyimide resins and ratios of the first and second resin insulating layers. Regarding Claim 15, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer has a thickness that is greater than a thickness of the conductor foil (see, e.g., fig. 5). Kaji (see, e.g., fig. 5, para.0038), in view of Kotani & Nogawa as evidenced by MatWeb, discloses an alternate embodiment wherein the second insulating layer 53 (corresponding to 51 of fig. 1) has a greater thickness than the conductor foil 32 (corresponding to 31 of fig. 1) in the vertical direction. This embodiment satisfies the limitations as required by Claim 1 on which Claim 15 depends, and renders Claim 15 obvious. Regarding Claim 16, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein: a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer (limitation already shown in claim 1 rejection); and the second resin insulating layer has a thickness that is greater than a thickness of the adhesive layer (see, e.g., annotated figure 4). Since Applicant has not established a direction for thickness, the thicknesses of the second resin insulating layer and adhesive layer are interpreted as shown in annotated figure 4. PNG media_image4.png 927 1136 media_image4.png Greyscale Regarding Claim 17, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 is provided on an exposed part of a top surface of the first resin insulating layer 41 that is not covered by the conductor foil 31 (between 31a & 31b, see, e.g., fig. 1). Regarding Claim 18, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein the second resin insulating layer 51 surrounds a circumference of the conductor foil 31 (see, e.g., fig. 2). Regarding Claim 19, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, wherein: a part of the case is bonded to a top surface of an end part of the first resin insulating layer via an adhesive layer (limitation already shown in claim 1 rejection); and the water-absorption rate of the second resin insulating layer (polyimide resin) is less than a water absorption rate of the adhesive layer (silicone). MatWeb (see, e.g., matweb.com, Overview of Materials for Polyimide, Overview of Materials for Silicone, RTV, Encapsulation Grade) states the polyimide resin can have a water absorption rate between 0.04-2% and silicone has a water absorption rate between 0.05-.5% Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to arrive at the limitation the water-absorption rate of the second resin insulating layer (Polyimide) is less than a water absorption rate of the adhesive layer (Silicone, RTV, Encapsulation Grade) through routine experimentation of the various water absorption rates of polyimide and silicone. Regarding Claim 20, Kaji (see, e.g., para.0021), in view of Kotani (see, e.g., para.0048) & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 12, wherein: the first resin insulating layer further includes filler (see, e.g., para.0021), and the second resin insulating layer does not include filler (corresponding to 10 of Kotani, see, e.g., para.0048). Kotani (see, e.g., para.0048) also teaches a second resin insulating layer 10 made of polyimide resin without filler. The material satisfies the rejection of Claims 1 & 12 on which Claim 20 depends, and therefore a simple substitution of a second resin insulating layer without filler 10 (of Kotani) in place of the second resin insulating layer 51 (of Kaji) is used for the rejection of Claim 20. Claim 8 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kaji (US 20220223546) in view of Kotani (US 20110031584) & Nogawa (US 20210305144) as evidenced by MatWeb (matweb.com) and further in view of Otsubo (US 20170034911). Regarding Claim 8, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, however, fails to show wherein the conductor foil 31 has a side surface having a regular tapered shape with a width that gradually increases in a direction of the first resin insulating layer. Kaji (see, e.g., fig. 1), in view of Kotani & Nogawa as evidenced by MatWeb shows instead the conductor foil has a side surface with a constant width in a direction of the first resin insulating layer. However, it is noted that the specification fails to provide teachings about the criticality of having a side surface having a regular tapered shape with a width that gradually increases in a direction of the first resin insulating layer, as claimed in the instant application. Additionally, the limitation “regular” is broad and does not further limit the claimed shape. Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the conductor foil side surface disclosed by Kaji, in view of Kotani & Nogawa as evidenced by MatWeb as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular shape of the conductor foil side surface claimed by applicant is nothing more than one of numerous shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976). Furthermore, the claimed limitation is known in the art: PNG media_image5.png 477 746 media_image5.png Greyscale Otsubo (see, e.g., fig. 12, para.0070), in the same field of endeavor teaches that the shape of the conductor foil 16 side surface can be a regular tapered shape with a width that gradually increases in a direction of the first resin insulating layer 2 (bottom layer). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of Otsubo in the device of Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, because the shape is known in the semiconductor art to have a width that gradually increases in a direction of the first resin insulating layer as an obvious configuration as suggested by Otsubo, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Regarding Claim 9, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, shows the semiconductor device of claim 1, Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, however, fails to show wherein the conductor foil has a side surface having an inverse tapered shape with a width gradually decreasing as being closer to the first resin insulating layer. Kaji (see, e.g., fig. 1), in view of Kotani & Nogawa as evidenced by MatWeb shows instead the conductor foil has a side surface with a constant width in a direction of the first resin insulating layer. However, it is noted that the specification fails to provide teachings about the criticality of having a side surface having an inverse tapered shape with a width gradually decreasing as being closer to the first resin insulating layer, as claimed in the instant application. Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the shape of the conductor foil side surface disclosed by Kaji, in view of Kotani & Nogawa as evidenced by MatWeb as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular shape of the conductor foil side surface claimed by applicant is nothing more than one of numerous shapes that a person having ordinary skill in the art will find obvious to provide using routine experimentation as a matter of choice or based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976). Furthermore, the claimed limitation is known in the art: PNG media_image6.png 453 575 media_image6.png Greyscale Otsubo (see, e.g., fig. 3, para.00039), in the same field of endeavor teaches that the shape of the conductor foil 6 side surface can be an inverse tapered shape with a width gradually decreasing as being closer to the first resin insulating layer 2 (bottom layer). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the shape of Otsubo in the device of Kaji, in view of Kotani & Nogawa as evidenced by MatWeb, because the shape is known in the semiconductor art to be gradually decreasing as being closer to the first resin insulating layer as an obvious configuration as suggested by Otsubo, and implementing a known structure shape for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Response to Arguments Applicant's arguments, see page 5 filed 06/01/2026, with respect to the claim objections of claim 18 have been fully considered and are persuasive. The claim objections of claim 18 have been withdrawn. Applicant’s arguments, see pages 5-6, with respect to the rejection(s) of claim(s) 1-3, & 5-20 under 35 U.S.C. 103 have been fully considered and are persuasive over the prior art of record. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kaji, Kotani, Nogawa, Otsubo, & MatWeb. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO JOSE RAMOS-DIAZ/ Examiner, Art Unit 2818 /STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Jun 28, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection mailed — §103, §112
Jan 13, 2026
Response Filed
Apr 01, 2026
Final Rejection mailed — §103, §112
Jun 01, 2026
Response after Non-Final Action
Jun 22, 2026
Request for Continued Examination
Jun 24, 2026
Response after Non-Final Action
Aug 17, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
84%
With Interview (+1.5%)
3y 3m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 17 resolved cases by this examiner. Grant probability derived from career allowance rate.

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