Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: the claim states “….a first control terminal a first sense terminal for the first switching device, and a second control terminal for the second switching device, and a second sense terminal for the second switching device…..” In the view of the Examiner, the claim should read “….a first control terminal, a first sense terminal for the first switching device, Appropriate correction is required.
Claim 1 is objected to because of the following informalities: the claim states “….the casing being configured…”. The word being is not needed here and in other places in this claim. Appropriate correction is required.
Claim 5 is objected to because of the following informalities: the claim states “….the third direction being intersecting…”. The word being is not needed here. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 8 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 8, the claim states, “…which has a control electrode that is provided on a side thereof facing the fourth edge of the casing.” However, in the view of the Examiner, the control electrodes in Fig. 11 (which corresponds to this claim) face the third edge of the casing. This can be seen in Fig. 4, where the control electrodes of the power semiconductor devices (Q1-Q6) all face the third edge 2C (see Para. [0041 of spec). Examiner can find nowhere in the specification where the control electrodes face the fourth edge.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 10-12 are rejected under 35 U.S.C. 102a1 as being anticipated by US20150023081A1 (Obiraki).
Regarding Claim 1, Obiraki discloses a semiconductor module (Fig. 3, el. 100, Para. [0035]), comprising: a first switching device (see annotated Fig. 3 below, el. 6, Para. [0035]); a second switching device (see annotated Fig. 3 below, el. 6, Para. [0035]) coupled in series with the first switching device (see Fig. 2); a casing (Fig. 3, el. 21, Para. [0033]) having a first edge, a second edge, a third edge, and a fourth edge (see annotated Fig. 3 below), the first and second edges facing each other in a first direction in a plan view of the semiconductor module (see annotated Fig. 3 below), the third and fourth edges facing each other in a second direction intersecting the first direction in the plan view (see annotated Fig. 3 below), the casing being configured to house the first and second switching devices (Para. [0033]); a positive terminal (see annotated Fig. 3 below, el. 11a, Para. [0037]) and a negative terminal (see annotated Fig. 3 below, el. 12a, Para. [0037]) that are provided on a first edge side of the casing (see annotated Fig. 3 below); an output terminal (see annotated Fig. 3, els. 10a, Para. [0037]) provided on a second edge side of the casing (see annotated Fig. 3 below); a first control terminal (see annotated Fig. 3 below, el. 13ga, Para. [0047]) a first sense terminal for the first switching device (see annotated Fig. 3 below, 13sa, Para. [0047]), and a second control terminal (see annotated Fig. 3 below, el. 14ga, Para. [0047]) for the second switching device (see annotated Fig. 3 below), and a second sense terminal (see annotated Fig. 3 below, el. 14sa, Para. [0047]) for the second switching device (see annotated Fig. 3 below), the first and second control terminals and the first and second sense terminals being provided on a third edge side of the casing (see annotated Fig. 3 below); a first conductive pattern coupled to the positive terminal (see annotated Fig. 3 below), the first switching device being arranged on the first conductive pattern (see annotated Fig. 3 below); a second conductive pattern (see annotated Fig. 3 below, el. 4, Para. [0037]) coupled to the output terminal (Para. [0037]), the second switching device being arranged on the second conductive pattern (see annotated Fig. 3 below); and a third conductive pattern (see annotated Fig. 3 below) coupled to the negative terminal and the second switching device (see annotated Fig. 3 below), the third conductive pattern being provided on one side of the semiconductor module corresponding to a fourth edge side of the casing (see annotated Fig. 3 below).
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Regarding Claim 2, Obiraki discloses the semiconductor module according to Claim 1, wherein in the plan view, an area of the output terminal is larger than an area of each of the positive terminal and the negative terminal (see annotated Fig. 3 above, where the output terminal consists of two terminals 10a, each of which is the same size as the positive terminal and the negative terminal. Thus, the area of the output terminal is twice each of the positive and negative terminals).
Regarding Claim 3, Obiraki discloses the semiconductor module according to Claim 1, further comprising: a first control conductive pattern (see annotated Fig. 3 above) configured to couple the first control terminal and the first switching device (see annotated Fig. 3 above); and a second control conductive pattern configured to couple the second control terminal and the second switching device (see annotated Fig. 3 above), wherein the first control conductive pattern is arranged closer to the third edge of the casing than the first conductive pattern is (see annotated Fig. 3 above), and the second control conductive pattern is arranged closer to the third edge of the casing than the second conductive pattern is (see annotated Fig. 3 above).
Regarding Claim 10, Obiraki discloses the semiconductor module of Claim 1, further comprising: a conductive first substrate (Fig. 3, el. 1, Para. [0035]); and a second substrate and a third substrate that are on the first substrate (see annotated 5 below, el. 5 Para. [0040]), wherein the second conductive pattern includes a first section and a second section coupled to each other (see annotated Fig. 3 below), the third conductive pattern includes a third section and a fourth section coupled to each other (see annotated Fig. 3 below), the second substrate has the first conductive pattern, the first section, the fourth section, and the first switching device formed thereon, and the third substrate has the second section, the third section, and the second switching device formed thereon (see annotated Fig. 3 below).
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Regarding Claim 11, Obiraki discloses the semiconductor module according to Claim 10, further comprising: a first control conductive pattern configured to couple the first control terminal and the first switching device (see annotated Fig. 3 above page 4); and a second control conductive pattern configured to couple the second control terminal and the second switching device (see annotated Fig. 3 above pate 4), wherein the first control conductive pattern, the first conductive pattern, the first section, and the fourth section are arranged on the second substrate in this order in the second direction (see annotated Fig. 3 above page 4 and 6), and the second control conductive pattern, the second section, and the third section are arranged on the third substrate in this order in the second direction (see annotated Fig. 3 above pate 4 and 6).
Regarding Claim 12, Obiraki discloses the semiconductor module according to Claim 11, wherein the positive terminal is coupled to the first conductive pattern (see annotated Fig. 3 above page 6), the output terminal is coupled to the second section (see annotated Fig. 3 above page 6), and the negative terminal is coupled to the fourth section (see annotated Fig. 3 above page 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Obiraki.
Regarding Claim 4, Obiraki discloses the semiconductor module according to Claim 3, wherein each of the first and second switching devices has a plurality of semiconductor chips (see annotated Fig. 3 above Page 4, where the first and second switching devices have three power semiconductor chips respectively) that includes a first semiconductor chip that is closest to the first edge of the casing (see annotated Fig. 3 above), and a second semiconductor chip that is closest to the second edge of the casing (see annotated Fig. 3 above), each of the plurality of semiconductor chips having a control electrode (see Fig. 3 and Para. [0039]);
Obiraki does not disclose that length of the first control conductive pattern in a longitudinal direction thereof is longer than a distance between a geometric center of the control electrode of the first semiconductor chip of the first switching device, and a geometric center of the control electrode of the second semiconductor chip of the first switching device; and a length of the second control conductive pattern in a longitudinal direction thereof is longer than a distance between a geometric center of the control electrode of the first semiconductor chip of the second switching device, and a geometric center of the control electrode of the second semiconductor chip of the second switching device.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify the lengths of the control conductive patterns so that they are longer than the distance between the geometric center of the control electrode of the first semiconductor chip and the geometric center of the control electrode of the second semiconductor chip. This would be involve a simple change in length of the control conductive patterns of Obiraki (see MPEP 2144.04(IV)(A)).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Obiraki in view of US20130056755A1 (Hatai).
Regarding Claim 5, Obiraki discloses the semiconductor module according to claim 3, further comprising: a substrate (Fig. 3, el. 5, Para. [0035]) wherein the first to third conductive patterns are formed on the substrate.
Obiraki does not disclose a control substrate that is arranged at a position away, in a third direction, from the substrate, the third direction being intersecting each of the first direction and the second direction, wherein the first and second control conductive patterns are formed on the control substrate.
Hatai discloses a semiconductor module (Fig. 10, el. PM9, Para. [0124]) with a control substrate (Fig. 10, el. 101, Para. [0124]) that is placed in a third direction (the vertical direction) with respect to a main substrate (Fig. 10, el. 11, Para. [0124]) wherein control wires (Fig. 10, el. 102, Para. [0125]) are attached to the control substrate and connect the control substrate to power transistors (Fig. 10, el. 15, 16, Para. [0125]), and the control substrate overlaps the main substrate and the transistors (Fig. 10, Para. 0124]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to place the first and second control conductive patterns in Obiraki on the control subtrate of Hatai, elevating the control substrate (as in Hatai) such that it is apart from the substrate in Obiraki in a third direction. This would provide a reduction in size in the x and y directions (one of the motivations provided in Hatai – see Para. [0134]).
Regarding Claim 6, Obiraki in view of Hatai discloses the semiconductor module according to claim 5, wherein the control substrate and the substrate overlap each other in the plan view to form an overlap region (see analysis of claim 5).
Regarding Claim 7, Obiraki in view of Hatai discloses the semiconductor module according to claim 6, wherein at least a part of the first switching device and at least a part of the second switching device are in the overlap region in the plan view (see analysis of claim 5).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Obiraki in view of Hatai.
Regarding Claim 8, Obiraki in view of Hatai discloses the semiconductor module according to claim 7, wherein each of the first and second switching devices includes a semiconductor chip which has a control electrode that is provided on a side thereof facing the third edge of the casing (Obiraki, see annotated Fig. 3 above).
Obiraki in view of Hatai does not disclose that the control electrode faces the fourth edge of the casing.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Obirkai in view of Hatai such that the control electrode faces the fourth edge of the casing. Such a configuration could be obtained by simply rotating the semiconductor chip 180 degrees, and would be a simple rearrangement of parts (see MPEP 2144.04(VI)(C)).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Obiraki in view of US20210143136A1 (Usui).
Regarding Claim 9, Obiraki discloses the semiconductor module according to Claim 1.
Obiraki does not disclose a first filter provided between the first control terminal and the first sense terminal; and a second filter provided between the second control terminal and the second sense terminal.
Usui discloses a semiconductor module (Fig. 11, el. 4, Para. [0095]) with first (Fig. 12, el. RFC1, Para. [0103]; although these are described as choke coils, they can also be filters – see Para. [0114]) and second filters (Fig. 12, el. RFC2, Para. [Para. [0103]), where the filters are connected between the control terminal (see Fig. 12, where the filter is connected to el. GC1) and the sense terminal (see Fig. 12, where the filter is connected to el. SC1).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to add first and second filters to Obiraki as disclosed by Usui for the purpose of minimizing common-mode noise (Usui, Para. [0097]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899