DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Group I (claims 1-11) in the reply filed on 06/28/2023 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ZHANG et al. (U.S 2022/0302149 A1).
As to claim 1, Zhang et al. disclose in Figs. 3E-3M a semiconductor structure, comprising: an alternating stack (330, Fig. 3E) of insulating layers (“stack dielectric layers” 310) (Fig. 3E, para. [0068]) and electrically conductive layers (“stack conductive layers” 328) located on a planar semiconductor layer (“filling layer” 306) comprising a first semiconductor material (see para. [0066], layer 306 can be polysilicon) and laterally extending along a horizontal direction (Fig. 3E, para. [0066], [0075]);
a memory opening (see “channel holes” in stack 330, Fig. 3I, para. [0070]) vertically extending through the alternating stack (330);
a memory opening fill structure (314) located in the memory opening (see “channel holes” in stack 330, Fig. 3I, para. [0070]) and comprising a memory film (316, Fig. 3I) and a vertical semiconductor channel (318) that includes a second semiconductor material (para. [0071]); and
a backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) comprising a third semiconductor material (see para. [0088]) and contacting (shown in Figs. 3K-3L) the vertical semiconductor channel (318) and the planar semiconductor layer (“filling layer” 306) (see Figs. 3K-3L, para. [0088]).
As to claim 2, as applied to claim 1 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein: a horizontal interface is present between the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) and the planar semiconductor layer (“filling layer” 306) (Fig. 3K); the vertical semiconductor channel (318) has a doping of a first conductivity type (para. [0080]); and the first semiconductor material of the planar semiconductor layer (“filling layer” 306) comprises a doped polycrystalline semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type (para. [0038], [0088]).
As to claim 3, as applied to claim 1 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) comprises: a planar portion in contact with the planar semiconductor layer (“filling layer” 306) and having a backside surface that is spaced from the first horizontal plane by a uniform vertical spacing; and a cap portion (315, Fig. 3I) in contact with the vertical semiconductor channel (318) and having an area overlap with the memory opening fill structure (314) and vertically protruding farther from the alternating stack (330) than a distal surface of the planar portion (Fig. 3E-3M).
As to claim 4, as applied to claims 1 and 3 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the cap portion (315, Fig. 3I) protrudes farther outward from a horizontal plane including an interface between the planar semiconductor layer (306) and the alternating stack (330) than the planar portion (Fig. 3I).
As to claim 5, as applied to claims 1 and 3 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) contacts an entirety of a non-vertical end surface of the memory film (316, Fig. 3K) (Fig. 3K).
As to claim 6, as applied to claims 1 and 3 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) is in contact with a non-vertical end surface of the vertical semiconductor channel (318) (Fig. 3K).
As to claim 7, as applied to claims 1 and 3 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) is in contact with an end portion of an outer sidewall of the vertical semiconductor channel (318) (Fig. 3K).
As to claim 8, as applied to claims 1 and 3 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein: the memory opening fill structure (314) further comprises a dielectric core (see a dielectric core inside 314) that is laterally surrounded by the vertical semiconductor channel (318) (Fig. 3K); the dielectric core (see a dielectric core inside 314) comprises an end portion that protrudes farther away from the alternating stack (330) than a first horizontal plane including the horizontal interface between the planar semiconductor layer (“filling layer” 306) and the backside semiconductor source structure; and the backside semiconductor source structure is in contact with the dielectric core (see a dielectric core inside 314).
As to claim 9, as applied to claims 1, 3 and 8 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) is in contact with an end portion of an inner sidewall of the memory film (316, Fig. 3K).
As to claim 10, as applied to claims 1, 3 and 8 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) is in contact with an end portion of an outer sidewall of the memory film (316, Fig. 3K).
As to claim 11, as applied to claims 1, 3 and 8 above, Zhang et al. disclose in Figs. 3E-3M all claimed limitations including the limitation: wherein the backside semiconductor source structure (“doped semiconductor layer” 360, Fig. 3K) comprises: a first vertical sidewall in contact with the vertical semiconductor channel (318); and a second vertical sidewall in contact with the planar semiconductor layer (“filling layer” 306) and laterally offset outward from the first vertical sidewall (Fig. 3K).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 February 21, 2026