Attorney’s Docket Number: YOR920151366US06 (1188-5)
Filing Date: 06/28/2023
Claimed Priority Date: 09/19/2019 (DIV of 16/576,201 now PAT 11,735,524)
04/05/2017 (DIV of 15/479,983 now PAT 10,541,206)
03/22/2016 (DIV of 15/076,878 now PAT 9,837,355)
Applicants: Briggs et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 11/21/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 11/21/2025, responding to the Office action mailed on 10/01/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-18.
Response to Amendment
Applicant’s amendments to the Claims have overcome the claim objections previously set forth in the Non-Final Office action mailed on 10/01/2025. Accordingly, all previous claim objections are hereby withdrawn.
Applicant’s amendments to the Claims have overcome the respective claim rejections under non-statutory Double Patenting, 35 U.S.C. 102, and 35 U.S.C. 103, as previously set forth in the same Office action. Accordingly, all previous claim rejections are hereby also withdrawn. However, new grounds of rejection are presented below, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 6, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Verheijden et al. (US2009/0267166) in view of Ahn et al. (US2015/0287682).
Regarding Claim 1, Verheijden (see, e.g., Fig. 7j and Par. [0085]-[0101]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., interconnect lines comprising barrier layer 111 and bulk copper 112) on a substrate (e.g., substrate 105)
- a plurality of air gaps (e.g., cavities/air-gaps 50) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., permeable porous layer 114 of carbon-doped oxide/ Black-Diamond™) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines
- a plurality of interconnects (e.g., portions of interconnects 121,122 in via openings 118) in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present between said electrically conductive lines (see, e.g., Fig. 7j: each space laterally between consecutive conductive lines and proximate to an interconnect via landing is substantially occupied by cavities/air-gaps 50, thus does not define an exclusion zone for said via landing).
However, Verheijden (see, e.g., Fig. 7j) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, wherein the exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines.
Ahn (see, e.g., Figs. 1 and 24, and Par. [0071]), on the other hand and in the same field on endeavor, teaches an electrical device comprising a plurality of conductive patterns 10 in a first interconnect layer L1 on a substrate 1 that are positioned in an array having parallel lengths, and connected to a plurality of conductive patterns 20 in second interconnect layer L2, wherein the number of depicted conductive patterns or connections therebetween is non-limiting (see, e.g., Par. [0053]: any suitable number of conductive patterns and connections therebetween may be chosen by one skilled in the art according to the needs of the circuit design). Furthermore, Ahn teaches that the conductive patterns 10 have air-gaps AG1 arranged therebetween such that an exclusion zone for conductive patterns 20 is not present in said array of conductive patterns 10, therefore increasing the area of the air gap regions and improving the signal transfer speed through the interconnections.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have the plurality of electrically conductive lines positioned in an array having parallel lengths and an exclusion zone for said plurality of interconnects not being present in said array of electrically conductive lines in the structure of Verheijden, because it is known in the semiconductor layout art that electrically conductive lines can be positioned in an array having parallel lengths wherein said array is devoid of exclusion zones for interconnects, as taught by Ahn, thereby forming air gap regions with increased areas for improved signal transfer speed through interconnections, and implementing a known arrangement of electrically conductive lines for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 2, Verheijden (see, e.g., Fig. 7j) shows that that the plurality of interconnects (e.g., via portions of 121,122) do not enter the plurality of air gaps (e.g., 50).
Regarding Claim 3, Verheijden (see, e.g., Fig. 7j and Par. [0091]) discloses that the material of permeable porous layer 114 is, e.g., a carbon-doped oxide. Additionally, Ahn (see, e.g., Par. [0069]) teaches that porous SiOCH (also a carbon-doped oxide) is a suitable material for forming a permeation layer 13. Therefore, Verheijden in view of Ahn teaches that the permeable cap dielectric is selected from the group consisting of crosslinked polyphenylenes, porous SiCOH, SiCOH, methyl silsesquioxane (MSSQ), and combinations thereof.
Regarding Claim 6, Verheijden (see, e.g., Fig. 7j and Par. [0089]) shows that each of the plurality of electrically conductive lines is comprised of a metal (e.g., bulk copper 112).
Regarding Claim 8, Verheijden (see, e.g., Fig. 7j and Par. [0085]-[0101]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., interconnect lines comprising barrier layer 111 and bulk copper 112) on a substrate (e.g., substrate 105)
- a plurality of air gaps (e.g., cavities/air-gaps 50) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., permeable porous layer 114 of carbon-doped oxide/ Black-Diamond™) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines
- a plurality of interconnects (e.g., portions of interconnects 121,122 in via openings 118) in electrical communication and self-aligned (e.g., by a Dual Damascene process) with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present between said electrically conductive lines (see, e.g., Fig. 7j: each space laterally between consecutive conductive lines and proximate to an interconnect via landing is substantially occupied by cavities/air-gaps 50, thus does not define an exclusion zone for said via landing).
However, Verheijden (see, e.g., Fig. 7j) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, wherein the exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. Also, see comments stated above in Par. 10-11 with regards to Claim 1, which are considered repeated here.
Regarding Claim 9, see comments stated above in Par. 12 with regards to Claim 2, which are considered repeated here.
Claims 4 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Verheijden et al. (US2009/0267166) in view of Ahn et al. (US2015/0287682), and in further view of Liu et al. (US7871922).
Regarding Claim 4, Ahn (see, e.g., Fig. 2 and Par. [0007]) discloses a pitch D1 separating adjacent electrically conductive lines 10 in a highly integrated semiconductor device. However, Verheijden in view of Ahn he is silent about the value of the pitch. Liu (see, e.g., Figs. 2B, 2K, and Col. 3, L. 44-53), on the other hand and in the same field of endeavor, teaches that a pitch b between conductive lines 230 in sub-22nm technology is 30nm or more.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pitch separating adjacent ones of the plurality of electrically conductive lines ranging from 30nm to 80nm in the electrical device of Verheijden in view of Ahn, because a pitch of at least 30nm is known in the semiconductor art as a pitch for sub-22nm technology conductive lines, as suggested by Liu, and implementing a known pitch between conductive lines of a highly integrated semiconductor device for their conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 10, see comments stated above in Par. 19-20 with regards to Claim 4, which are considered repeated here.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Verheijden et al. (US2009/0267166) in view of Ahn et al. (US2015/0287682), and in further view of Siew et al. (US2016/0372415).
Regarding Claim 5, Verheijden (see, e.g., Fig. 7j and Par. [0089]) discloses that the plurality of electrically conductive lines is comprised of a metal (e.g., bulk copper 112). However, Verheijden in view of Ahn is silent about each of the plurality of electrically conductive lines being comprised of doped semiconductor material. Siew (see, e.g., Figs. 56-57, and Par. [0251]), on the other hand and in the same field of endeavor, teaches that metal and doped polysilicon are known to be equivalent materials for their use as material for implementing conductive layers.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have either a metal or a doped semiconductor material such as doped polysilicon as the material of the plurality of electrically conductive lines in the structure of Verheijden in view of Ahn, because these materials are known in the semiconductor art as being equivalent materials for implementing conductive layers, as suggested by Siew, and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 11, see comments stated above in Par. 23-24 with regards to Claim 5, which are considered repeated here.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kloster et al. (US2004/0102031) in view of Ahn et al. (US2015/0287682).
Regarding Claim 1, Kloster (see, e.g., Fig. 3M and Par. [0037]-[0055]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., line portion 318 of conductive layers 110 and 112) on a substrate (e.g., substrate layer 104)
- a plurality of air gaps (e.g., void spaces/air gaps 326) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., permeable layer 324) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines
- a plurality of interconnects (e.g., via portion 316 of conductive layers 313 and 315) in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present between said electrically conductive lines (see, e.g., Fig. 3M: each space laterally between consecutive conductive lines and proximate to an interconnect via landing is substantially occupied by void spaces/air gaps 326, thus does not define an exclusion zone for said via landing).
However, Kloster (see, e.g., Fig. 3M) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, wherein the exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines.
Ahn (see, e.g., Figs. 1 and 24, and Par. [0071]), on the other hand and in the same field on endeavor, teaches an electrical device comprising a plurality of conductive patterns 10 in a first interconnect layer L1 on a substrate 1 that are positioned in an array having parallel lengths, and connected to a plurality of conductive patterns 20 in second interconnect layer L2, wherein the number of depicted conductive patterns or connections therebetween is non-limiting (see, e.g., Par. [0053]: any suitable number of conductive patterns and connections therebetween may be chosen by one skilled in the art according to the needs of the circuit design). Furthermore, Ahn teaches that the conductive patterns 10 have air-gaps AG1 arranged therebetween such that an exclusion zone for conductive patterns 20 is not present in said array of conductive patterns 10, therefore increasing the area of the air gap regions and improving the signal transfer speed through the interconnections.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have the plurality of electrically conductive lines positioned in an array having parallel lengths and an exclusion zone for said plurality of interconnects not being present in said array of electrically conductive lines in the structure of Kloster, because it is known in the semiconductor layout art that electrically conductive lines can be positioned in an array having parallel lengths wherein said array is devoid of exclusion zones for interconnects, as taught by Ahn, thereby forming air gap regions with increased areas for improved signal transfer speed through interconnections, and implementing a known arrangement of electrically conductive lines for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 2, Kloster (see, e.g., Fig. 3M) shows that that the plurality of interconnects (e.g., via portion 316 of 313,315) do not enter the plurality of air gaps (e.g., 326).
Regarding Claim 3, Kloster (see, e.g., Fig. 3M and Par. [0048]) discloses that the material of permeable layer 324 is a porous carbon doped oxide having the molecular structure SixOyRz, in which "R" is an alkyl or aryl group. Additionally, Ahn (see, e.g., Par. [0069]) teaches that porous SiOCH (also a carbon-doped oxide with (CH) as alkyl group) is a suitable material for forming a permeation layer 13. Therefore, Kloster in view of Ahn teaches that the permeable cap dielectric is selected from the group consisting of crosslinked polyphenylenes, porous SiCOH, SiCOH, methyl silsesquioxane (MSSQ), and combinations thereof.
Regarding Claim 4, Kloster (see, e.g., Fig. 3M and Par. [0009]) discloses that the spacing between conductive layers 110 and 112 may vary with feature size of the microelectronic structure as would be apparent to one skilled in the art, and is preferably between about 10 nm and about 1000 nm.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a pitch separating adjacent ones of the plurality of electrically conductive lines in the plurality of electrically conductive lines ranging from 30 nm to 80 nm in the structure of Kloster in view of Ahn, as it has been held by the court that a prima facie case of obviousness exists in the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art”. See In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997).
Regarding Claim 5, Kloster (see, e.g., Fig. 3M and Par. [0027],[0054]) discloses that the material of the conductive layers can be, e.g., doped polysilicon. Therefore, Kloster slows that each of the plurality of electrically conductive lines is comprised of a doped semiconductor material.
Regarding Claim 6, Kloster (see, e.g., Fig. 3M and Par. [0027],[0054]) discloses that the material of the conductive layers can be, e.g., metal (Cu). Therefore, Kloster slows that each of the plurality of electrically conductive lines is comprised of a metal.
Regarding Claim 7, Kloster (see, e.g., Fig. 3M and Par. [0033],[0040]) discloses that dielectric layer 340 can include a spin-on low-k silicon dioxide. Therefore, Kloster shows that the metal of the plurality of electrically conductive lines is present in trenches in a low-k dielectric material (e.g., Cu present in trenches in low-k dielectric 340).
Regarding Claim 8, Kloster (see, e.g., Fig. 3M and Par. [0037]-[0055]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., line portion 318 of conductive layers 110 and 112) on a substrate (e.g., substrate layer 104)
- a plurality of air gaps (e.g., void spaces/air gaps 326) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., permeable layer 324) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines
- a plurality of interconnects (e.g., via portion 316 of conductive layers 313 and 315) in electrical communication and self- aligned (e.g., by dual damascene interconnect formation process) with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present between said electrically conductive lines (see, e.g., Fig. 3M: each space laterally between consecutive conductive lines and proximate to an interconnect via landing is substantially occupied by void spaces/air gaps 326, thus does not define an exclusion zone for said via landing).
However, Kloster (see, e.g., Fig. 3M) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, and wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. Also, see comments stated above in Par. 29-30 with regards to Claim 1, which are considered repeated here.
Regarding Claim 9, see comments stated above in Par. 31 with regards to Claim 2, which are considered repeated here.
Regarding Claim 10, see comments stated above in Par. 33-34 with regards to Claim 4, which are considered repeated here.
Regarding Claim 11, see comments stated above in Par. 35 with regards to Claim 5, which are considered repeated here.
Regarding Claim 12, Kloster (see, e.g., Fig. 3M and Par. [0027],[0054]) discloses that the material of the conductive layers can be, e.g., metal (Cu). Furthermore, Kloster (see, e.g., Fig. 3M and Par. [0033],[0040]) discloses that dielectric layer 340 can include a spin-on low-k silicon dioxide. Therefore, Kloster shows that each of the plurality of electrically conductive lines are comprised of a metal (e.g., Cu) present in trenches in a low-k dielectric material (e.g., 340).
Claims 1-2, 6, 8-9, and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2001/0016412) in view of Ahn et al. (US2015/0287682).
Regarding Claim 1, Lee (see, e.g., Figs. 8A-C and Par. [0041]-[0046]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., wiring lines 54) on a substrate (e.g., comprising underlying layers 50 and 52)
- a plurality of air gaps (e.g., air gaps 100) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., capping layer 60 of porous dielectric) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines (see, e.g., Fig. 8C: bottom surface of 60 and plurality of 54s share at least a same horizontal plane, thus are co-planar)
- an interconnect (e.g., Par. [0046]: conductive plug (not shown) formed to fill opening 66) in electrical communication with one of said plurality of electrically conductive lines, wherein an exclusion zone for said interconnect is not present between said electrically conductive lines (see, e.g., Fig. 8C: each space laterally between consecutive wiring lines and proximate to a conductive plug landing is substantially occupied by air gaps 100, thus does not define an exclusion zone for said plug landing).
However, Lee (see, e.g., Fig. 8C) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, and a plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines.
Ahn (see, e.g., Figs. 1 and 24, and Par. [0071]), on the other hand and in the same field on endeavor, teaches an electrical device comprising a plurality of conductive patterns 10 in a first interconnect layer L1 on a substrate 1 that are positioned in an array having parallel lengths, and connected to a plurality of conductive patterns 20 in second interconnect layer L2, wherein the number of depicted conductive patterns or connections therebetween is non-limiting (see, e.g., Par. [0053]: any suitable number of conductive patterns and connections therebetween may be chosen by one skilled in the art according to the needs of the circuit design). Furthermore, Ahn teaches that the conductive patterns 10 have air-gaps AG1 arranged therebetween such that an exclusion zone for conductive patterns 20 is not present in said array of conductive patterns 10, therefore increasing the area of the air gap regions and improving the signal transfer speed through the interconnections.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have the plurality of electrically conductive lines being positioned in an array having parallel lengths, and a plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines in the structure of Lee, because it is known in the semiconductor layout art that electrically conductive lines can be positioned in an array having parallel lengths wherein said array is devoid of exclusion zones for a plurality of interconnects in electrical communication with said conductive lines, as taught by Ahn, thereby forming air gap regions with increased areas for improved signal transfer speed through interconnections, and implementing a known arrangement of electrically conductive lines for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 2, Lee (see, e.g., Fig. 8C) shows that that the interconnect (e.g., plug) do not enter the plurality of air gaps (e.g., 100). Additionally, Ahn (see, e.g., Figs. 1 and 24) teaches that a plurality of conductive patterns 20 can be in electrical communication with an array of conductive patterns 10. Therefore, Lee in view of Ahn teaches that the plurality of interconnects do not enter the plurality of air gaps.
Regarding Claim 6, Lee (see, e.g., Fig. 8C and Par. [0029) slows that each of the plurality of electrically conductive lines (e.g., 54) is comprised of a metal (e.g., copper, tungsten, or aluminum).
Regarding Claim 8, Lee (see, e.g., Figs. 8A-C and Par. [0041]-[0046]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., wiring lines 54) on a substrate (e.g., comprising underlying layers 50 and 52)
- a plurality of air gaps (e.g., air gaps 100) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines
- a permeable cap dielectric (e.g., capping layer 60 of porous dielectric) present over the plurality of air gaps and the plurality of electrically conductive lines, the permeable cap dielectric having a bottom surface that is co-planar with the plurality of electrically conductive lines (see, e.g., Fig. 8C: bottom surface of 60 and plurality of 54s share at least a same horizontal plane, thus are co-planar)
- an interconnect (e.g., Par. [0046]: conductive plug (not shown) formed to fill opening 66) in electrical communication and self aligned (e.g., by damascene-type via opening fill) with one of said plurality of electrically conductive lines, wherein an exclusion zone for said interconnect is not present between said electrically conductive lines (see, e.g., Fig. 8C: each space laterally between consecutive wiring lines and proximate to a conductive plug landing is substantially occupied by air gaps 100, thus does not define an exclusion zone for said plug landing).
However, Lee (see, e.g., Fig. 8C) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, and a plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. Also, see comments stated above in Par. 47-48 with regards to Claim 1, which are considered repeated here.
Regarding Claim 9, see comments stated above in Par. 49 with regards to Claim 2, which are considered repeated here.
Regarding Claim 13, Lee (see, e.g., Figs. 8A-C and Par. [0041]-[0046]) shows most aspects of the instant invention, including an electrical device comprising:
- a plurality of electrically conductive lines (e.g., wiring lines 54) on a substrate (e.g., comprising underlying layers 50 and 52)
- a plurality of air gaps (e.g., air gaps 100) between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines, air gap sidewalls including portions of the substrate (e.g., portion of 100 is recessed into 52)
- an interconnect (e.g., Par. [0046]: conductive plug (not shown) formed to fill opening 66) in electrical communication and misaligned with one of said plurality of electrically conductive lines, wherein an exclusion zone for said interconnect is not present between said electrically conductive lines (see, e.g., Fig. 8C: each space laterally between consecutive wiring lines and proximate to a conductive plug landing is substantially occupied by air gaps 100, thus does not define an exclusion zone for said plug landing).
However, Lee (see, e.g., Fig. 8C) depicts his inventions in vertical cross-section views. Thus, he is silent about the plurality of electrically conductive lines being positioned in an array having parallel lengths, and a plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. Also, see comments stated above in Par. 47-48 with regards to Claim 1, which are considered repeated here.
Regarding Claim 14, see comments stated above in Par. 49 with regards to Claim 2, which are considered repeated here.
Regarding Claim 15, Lee (see, e.g., Fig. 8C) shows a permeable cap dielectric (e.g., capping layer 60 of porous dielectric) present over the plurality of air gaps.
Claims 4, 10, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2001/0016412) in view of Ahn et al. (US2015/0287682), and in further view of Liu et al. (US7871922).
Regarding Claim 4, Ahn (see, e.g., Fig. 2 and Par. [0007]) discloses a pitch D1 separating adjacent electrically conductive lines 10 in a highly integrated semiconductor device. However, Lee in view of Ahn he is silent about the value of the pitch. Liu (see, e.g., Figs. 2B, 2K, and Col. 3, L. 44-53), on the other hand and in the same field of endeavor, teaches that a pitch b between conductive lines 230 in sub-22nm technology is 30nm or more.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the pitch separating adjacent ones of the plurality of electrically conductive lines ranging from 30nm to 80nm in the electrical device of Lee in view of Ahn, because a pitch of at least 30nm is known in the semiconductor art as a pitch for sub-22nm technology conductive lines, as suggested by Liu, and implementing a known pitch between conductive lines of a highly integrated semiconductor device for their conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 10, see comments stated above in Par. 59-60 with regards to Claim 4, which are considered repeated here.
Regarding Claim 16, see comments stated above in Par. 59-60 with regards to Claim 4, which are considered repeated here.
Claims 5, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2001/0016412) in view of Ahn et al. (US2015/0287682), and in further view of Siew et al. (US2016/0372415).
Regarding Claim 5, Lee (see, e.g., Fig. 8C and Par. [0029) slows that each of the plurality of electrically conductive lines (e.g., 54) is comprised of a metal (e.g., copper, tungsten, or aluminum). However, Lee in view of Ahn is silent about each of the plurality of electrically conductive lines being comprised of a doped semiconductor material. Siew (see, e.g., Figs. 56-57, and Par. [0251]), on the other hand and in the same field of endeavor, teaches that metal and doped polysilicon are known to be equivalent materials for their use as material for implementing conductive layers.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have either a metal or a doped semiconductor material such as doped polysilicon as the material of the plurality of electrically conductive lines in the structure of Lee in view of Ahn, because these materials are known in the semiconductor art as being equivalent materials for implementing conductive layers, as suggested by Siew, and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 11, see comments stated above in Par. 64-65 with regards to Claim 5, which are considered repeated here.
Regarding Claim 17, see comments stated above in Par. 64-65 with regards to Claim 5, which are considered repeated here.
Allowable Subject Matter
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 11/21/2025 have been considered but are moot in view of the new grounds of rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814