DETAILED ACTION
This action is responsive to the election received on 12/19/2025. This action further includes consideration by the examiner of IDS documents submitted up to 01/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-13) in the reply filed on 12/19/2025 is acknowledged. Claim(s) 14-20 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Applicant’s election without traverse of Species A (Figure 34C) in the reply filed on 12/19/2025 is acknowledged. Claim(s) 11-13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/28/2023, 06/30/2023, 05/20/2024, and 01/26/2026 has/have been considered by the examiner and made of record in the application file.
Claim Objections
Claim(s) 10 is/are objected to because of the following informalities where proposed corrections are bolded and underlined:
Claim 10, lines 1-2, “the backside semiconductor source structure is not in contact with the dielectric core”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,824,966 B1; Kanakamedala et al.; 11/2017; (“Kanakamedala”).
Regarding Claim 1. Kanakamedala discloses A semiconductor structure (Figures 14A-14B wherein Figures 1-13 are the method of making), comprising:
an alternating stack of insulating layers (#32, Figure 14A, insulating material layers) and electrically conductive layers (#46, Figure 14A, electrically conductive layers alternatingly stacked with #32s) located on a single crystalline semiconductor layer (#10, Figure 14A, substrate which may be single crystalline according to column 4, lines 53-54);
a memory opening (#49, Figure 3, memory opening in which #55 is formed in Figure 14A) vertically extending through the alternating stack (Figure 14A, the openings in which #55 is formed extend fully through the alternating stack of #32s and #46s) and through the single crystalline semiconductor layer (Figure 14A, the openings in which #55 is formed extend at least partially through #10);
a memory opening fill structure (#55, Figure 14A, memory stack structure) located in the memory opening (Figure 14A, #55 is located in the openings, formed in Figures 3-4) and comprising a memory film (#50, Figure 14A, memory film) and a vertical semiconductor channel (#60, Figure 14A, vertical semiconductor channel); and
a backside semiconductor source structure (#48 and #61, Figure 14A, source contact layer and annular source region) comprising a doped semiconductor material (column 14, lines 29-32, “source contact layer 48 includes a doped semiconductor material having the same conductivity type (e.g., the second conductivity type) as the annular source regions 61”, i.e. #48 and #61 are a doped semiconductor material),
wherein the backside semiconductor source structure comprises an epitaxial doped semiconductor portion (#48, Figure 14A, source contact layer, doped as described above, and epitaxially grown according to column 14, lines 66-67) in contact with and in epitaxial alignment with a single crystalline structure of the single crystalline semiconductor layer (Figure 14A, column 14, line 66 through column 15, line 2, “The source contact layer 48 can include a doped epitaxial semiconductor material that is epitaxially aligned to the single crystalline material of the doped semiconductor well 10D, which is a portion of the substrate 10”, i.e. #48 is epitaxially aligned with and in direct contact with #10), and a polycrystalline doped semiconductor portion (#61, Figure 14A, annular source region which is a polycrystalline doped region according to column 20, lines 62-64) in contact with the vertical semiconductor channel (Figure 14A, #61 directly contacts #60).
Regarding Claim 2. Kanakamedala discloses The semiconductor structure of Claim 1, wherein the epitaxial doped semiconductor portion (#48) and the polycrystalline doped semiconductor portion (#61) have a same material composition throughout (column 11, lines 21-23, “the in-process semiconductor channel 60L includes amorphous silicon or polysilicon”; column 14, lines 29-32, “source contact layer 48 includes a doped semiconductor material having the same conductivity type (e.g., the second conductivity type) as the annular source regions 61. For example, the source contact layer 48 can include doped silicon”, i.e. both #48 and #61 are formed to have the same composition of silicon doped with the second conductivity type impurities).
Regarding Claim 3. Kanakamedala discloses The semiconductor structure of Claim 1, wherein:
the vertical semiconductor channel has a doping of a first conductivity type (column 13, lines 42-43, “in-process semiconductor channel 60L includes a doped semiconductor material of a first conductivity type”, i.e. #60 which is formed from a portion of #60L (see Figures 6 through 8) has doping of a first conductivity type); and
an entirety of the backside semiconductor source structure has a doping of a second conductivity type that is an opposite of the first conductivity type (column 14, lines 29-32, “source contact layer 48 includes a doped semiconductor material having the same conductivity type (e.g., the second conductivity type) as the annular source regions 61”, i.e. #48 and #61 are doped with the second conductivity type).
Regarding Claim 4. Kanakamedala discloses The semiconductor structure of Claim 1, wherein a boundary between the epitaxial doped semiconductor portion and the polycrystalline doped semiconductor portion comprises a continuously extending grain boundary that extends from the memory film to a backside surface of the backside semiconductor source structure (Figure 14A, the boundary between the single crystalline #48 and polycrystalline #61, which is necessarily a grain boundary separating poly- and single-crystalline materials, extends in a vertical direction continuously from a bottom surface of #50 to a bottom, or backside surface, of the combination of #48 and #61).
Regarding Claim 5. Kanakamedala discloses The semiconductor structure of Claim 1, wherein the epitaxial doped semiconductor portion (#48) contacts a cylindrical sidewall of the single crystalline semiconductor layer (#10) at a sidewall of the memory opening (Figures 14A and 14B, a cylindrical interior sidewall of #10 in the memory opening extending into #10, see cylindrical memory structures formed in the openings in Figure 5B, is contacted by #48 as best observed in Figure 13).
Regarding Claim 6. Kanakamedala discloses The semiconductor structure of Claim 1, wherein the polycrystalline doped semiconductor portion (#61) contacts an end segment of an outer sidewall of the vertical semiconductor channel (Figure 14A, #61 contacts a bottom, or end, segment of a bottom outer sidewall of #60).
Regarding Claim 7. Kanakamedala discloses The semiconductor structure of Claim 1, wherein the epitaxial doped semiconductor portion (#48) comprises a portion located on a distal horizontal surface of the single crystalline semiconductor layer (Figure 14A, #48 includes a horizontally extending portion, between #55 and #76, which is located on a distal horizontal upper surface of #10).
Regarding Claim 8. Kanakamedala discloses The semiconductor structure of Claim 7, wherein an interface between the epitaxial doped semiconductor portion and the polycrystalline doped semiconductor portion (Figure 14A, the vertically extending boundary between the single crystalline #48 and polycrystalline #61) is located in a horizontal plane including the distal horizonal surface of the single crystalline semiconductor layer (Figure 14A and better viewed in Figure 13, the interface of #61 and #48 extends in a vertical direction into the horizontal plane including the upper surface of #10 which #48 is located on).
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2021/0035999 A1; Nishikawa et al.; 02/2021; (“Nishikawa”).
Regarding Claim 1. Nishikawa discloses A semiconductor structure (Figures 13A-13B), comprising:
an alternating stack of insulating layers (#32, Figure 13A, insulating layers) and electrically conductive layers (#46B, Figure 13A metallic fill material layer alternatingly stacked with #32s) located on a single crystalline semiconductor layer (#10, Figure 13A, semiconductor material layer, [0068], “single crystalline semiconductor material (e.g., single crystal silicon) of the semiconductor material layer 10”);
a memory opening (Figure 13A, openings through the stack in which #55s are located) vertically extending through the alternating stack (Figure 13A, the openings in which #55 is formed extend fully through the alternating stack of #32s and #46Bs) and through the single crystalline semiconductor layer (Figure 13A, the openings in which #55 is formed extend at least partially through #10)
a memory opening fill structure (#55, Figure 13A, memory stack structure) located in the memory opening (Figure 13A, openings through the stack in which #55s are located) and comprising a memory film (#50, Figure 13A, memory film) and a vertical semiconductor channel (#60C, Figure 13A, polycrystalline cylindrical portion and polycrystalline neck portion of semiconductor channel #60); and
a backside semiconductor source structure (#11 and #60B, Figure 13B, epitaxial pedestal structure and polycrystalline base portion) comprising a doped semiconductor material ([0068], “epitaxial pedestal structure 11 can have a doping of the first conductivity type”),
wherein the backside semiconductor source structure comprises an epitaxial doped semiconductor portion in contact with and in epitaxial alignment with a single crystalline structure of the single crystalline semiconductor layer (#11, Figure 13B, epitaxial pedestal structure which is doped, see [0068], and is in epitaxial alignment with #10, [0068], “epitaxial pedestal structure 11 comprises a single crystalline semiconductor material (e.g., single crystal silicon) in epitaxial alignment with the single crystalline semiconductor material (e.g., single crystal silicon) of the semiconductor material layer 10”), and a polycrystalline doped semiconductor portion (#60B, Figure 13B, polycrystalline base portion formed from #211, see Figures 6E-6F, which is doped according to [0103]) in contact with the vertical semiconductor channel (Figure 13B, #60B is in direct contact with #60N).
Regarding Claim 9. Nishikawa discloses The semiconductor structure of Claim 1, wherein:
a horizontal interface between the single crystalline semiconductor layer (#10) and the epitaxial doped semiconductor portion (#11) is located in a first horizontal plane (Figure 13B, let the interface of the bottom of #11 and the top surface of #10 be the first horizontal plane);
the memory opening fill structure comprises a dielectric core (#62, Figure 13B, dielectric core) that is laterally surrounded by the vertical semiconductor channel (Figure 13B, #62 is at least partially laterally surrounded by #60C and #60N); and
an end surface of the dielectric core (Figure 13B, bottommost surface of #62) is more distal from a second horizontal plane including an interface between the single crystalline semiconductor layer and the alternating stack (Figure 13B, let the interface of the bottom of the lowest #32 and the top surface of #10 be the first horizontal plane) than the first horizontal plane is from the second horizontal plane (Figure 13B, the bottommost surface of #62 is more distal from the interface of #32 and #10 than the interface of #11 and #10 is from the interface of #32 and #10).
Allowable Subject Matter
Claim(s) 10 is/are objected for the informality described above and are further objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: None of the cited prior art, either alone or in combination, teaches “the backside semiconductor source structure is not in contact with the dielectric core, and is spaced from the dielectric core by the vertical semiconductor channel”, as recited in claim 10, in combination with all other required limitations of the claim.
Regarding Claim 10. Nishikawa discloses The semiconductor structure of Claim 9.
Nishikawa does not disclose that the backside semiconductor source structure is not in contact with the dielectric core, and is spaced from the dielectric core by the vertical semiconductor channel. As observed in Figure 13B of Nishikawa, the polycrystalline semiconductor portion (#60B) of the backside semiconductor source structure is in direct contact with the dielectric core (#62). It is interpreted by the examiner that it would not be obvious to separate the polycrystalline semiconductor portion (#60B) of the backside semiconductor source structure from the dielectric core (#62) by providing the vertical semiconductor channel therebetween as #60B is instead interpreted by Nishikawa as being part of the overall semiconductor channel structure (#60). Similarly, the other reference relied upon above, Kanakamedala, also discloses in Figure 14A that the polycrystalline semiconductor portion (#61) of the backside semiconductor source structure is in direct contact with the dielectric core (#62). Therefore, claim 10 is interpreted as including allowable subject matter and would be allowable, pending resolving the informality in claim 10, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0422523 A1; Kim et al.; 12/2023 – Figures 5A-5D disclose a semiconductor structure comprising a memory structure (#VS1, vertical channel structure) passing through an alternating stack (#EL/#ILD) and a single crystalline semiconductor layer (#100, [0093], “second substrate 100 may include a monocrystalline semiconductor material”) and a backside semiconductor source structure comprising an epitaxial doped portion (#SCP2, [0135], “SCP2 may . . . cover the upper surface of the second substrate 100. . . SCP2 may include a . . . selective epitaxial growth method”) and a polycrystalline doped portion ([0118], “SCP1 may be a polycrystalline silicon layer”). However, the polycrystalline portion is separated from the vertical semiconductor channel (#VSP) bye the memory film (#DSP).
US 9,805,805 B1; Zhang et al.; 10/2017 – Figure 8 discloses a semiconductor structure comprising a memory structure (#55, memory stack structures) passing through an alternating stack (#32/#42) and a single crystalline semiconductor layer (#10, [0093], “second substrate 100 may include a monocrystalline semiconductor material”) and a backside semiconductor source structure comprising an epitaxial doped portion (#SCP2, [0135], “SCP2 may . . . cover the upper surface of the second substrate 100. . . SCP2 may include a . . . selective epitaxial growth method”) and a polycrystalline doped portion ([0118], “SCP1 may be a polycrystalline silicon layer”). However, the polycrystalline portion is separated from the vertical semiconductor channel (#VSP) bye the memory film (#DSP).
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/TYLER J WIEGAND/Examiner, Art Unit 2812