DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 11/5/25 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 3 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 6 of copending Application No. 18/459,174 (reference application) US Pub 2025/0079282. Although the claims at issue are not identical, they are not patentably distinct from each other because they overlap in scope.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Pertaining to claim 1: Claim 1 entirely overlaps in scope with claim 1 of the reference application. The only difference is the inclusion of additional limitations found in the reference application.
Pertaining to claim 3: Claim 3 is the same as claim 6 of the reference application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al US 2017/0148699 and further in view of Vincent et al US 2015/0380386.
Pertaining to claim 1, Seo teaches a semiconductor package, comprising:
a semiconductor die 120 having a device side including circuitry formed therein see Figure 10 marked up below;
a substrate facing and coupled to the device side see Figure 10 below, the substrate including:
first and second metal layers, the first metal layer positioned closer to the device side than the second metal layer and coupled to the second metal layer by way of a via see Figure 10 marked up below; and
a dielectric 130 contacting at least part of the first and second metal layers and the via; and
a mold compound 110 covering the semiconductor die 120 and the substrate (all elements 130 together see figure 10 marked up below),
wherein the package includes a lateral surface approximately perpendicular to the first and second metal layers of the substrate See Figure 10, and wherein the mold compound and the dielectric are exposed to the lateral surface, a segment (portion of dielectric immediately adjacent to metal elements) of the dielectric 130 positioned between the first metal layer and the lateral surface, the segment of the dielectric 130 contacting the mold compound at the lateral surface See Figure 10 marked up below.
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Seo does not teach wherein the second metal layer is exposed to the lateral surface. Vincent teaches a device with an encapsulated chip mounted on a substrate with metal layers, the metal layers exposed to a lateral surface. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teaching of Vincent into the invention of Seo for the purpose of providing lateral side contacts to external devices as taught by Vincent Figure 1 element 28 (provided below) note that what is being relied upon by Vincent is only the exposed metal layer in the substrate with external connection and nothing else. Providing lateral side contacts would be a design choice made by the ordinary artisan. When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
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Pertaining to claim 3, Seo in view of Vincent teaches the semiconductor package of claim 1, wherein the dielectric includes AJINOMOTO® Build-up Film (ABF). [0082] of Seo
Pertaining to claim 4, Seo in view of Vincent teaches the semiconductor package of claim 1, wherein a second segment of the dielectric is positioned between the via and the lateral surface. See Seo Figure 10 marked up below
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Pertaining to claim 6, Seo in view of Vincent teaches the semiconductor package of claim 1, wherein a distance between the first metal layer and the lateral surface is smaller than a distance between the via and the lateral surface. See Figure 10 of Seo marked up above in the rejection of Claim 1
Pertaining to claim 7, Seo in view of Vincent teaches the semiconductor package of claim 1, wherein an entire boundary between the mold compound and the dielectric lacks delamination. There is no delamination mentioned by Seo or Vincent in their structures.
Allowable Subject Matter
Claims 2, 5, 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-17 are allowed
The following is a statement of reasons for the indication of allowable subject matter:
Pertaining to claim 5, the prior art does not teach nor suggest the combination of claims 1, 4 and 5, wherein a distance between the via and the lateral surface is at least 125 microns. The applicant’s specification teaches that this dimension is a critical dimension for inhibiting delamination Pertaining to claim 8, the prior art does not teach nor suggest the combination of claims 1 and 8, wherein a conductive component between the second metal layer and a bottom surface of the substrate is exposed to the lateral surface. The prior art cited teaches only one exposed metal layer (Vincent) and would not suggest an additional exposed metal layer in the relationship as claimed.
Pertaining to claim 9, the prior art does not teach nor suggest a first metal layer of the stack closer to the device side than a second metal layer of the stack, the second metal layer closer to the device side than a third metal layer of the stack; and a dielectric contacting at least part of the at least three metal layers and the via; and a mold compound covering the semiconductor die and the substrate, wherein the package includes a lateral surface approximately perpendicular to the first metal layer, wherein the first and second metal layers are offset from the lateral surface by at least 100 microns, and wherein the dielectric contacts the mold compound at the lateral surface
Note: Prior art US Pub 2019/0221446 is an example of the state of the art for inhibiting delamination in edges of a separated semiconductor package.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817