Attorney Docket Number: 10921.1205USW1
Filing Date: 06/28/2023
Claimed Priority Dates: 12/06/2021 (CON of PCT/JP2021/044725)
01/04/2021 (JP 2021-000237)
Inventors: Kikuchi et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 04/21/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 04/21/2026 in reply to the previous Office action mailed on 01/28/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-19, with claims 4, 13, and 17 remaining withdrawn from consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2018/0218969) in view of Matsubara (US 2016/0307854).
Regarding claim 1, Nakamura (see, e.g., fig. 7) shows most aspects of the instant invention, including a semiconductor device comprising:
a semiconductor control element CPC;
a first drive element CPH located on a first side on a first direction X perpendicular to a thickness direction of the semiconductor control element with respect to the semiconductor control element, the first drive element receiving a signal transmitted from the semiconductor control element (see, e.g., pars.0060/ll.6-12 and 0061/ll.5-9);
a second drive element CPL located on a second side opposite the first side in the first direction with respect to the semiconductor control element, the second drive element receiving a signal transmitted from the semiconductor control element (see, e.g., pars.0060/ll.6-12 and 0061/ll.5-9); and
a sealing resin MR covering the semiconductor control element
Nakamura teaches most aspects of the instant invention. Nakamura further teaches that modulating potential for Nakamura’s elements can affect and adjust the performance and usage applications of these elements, that Nakamura’s semiconductor control and drive elements operate at varying high and low voltages, and that Nakamura’s device is intended to function as an inverter (see, e.g., pars.0003, 0061, 0063, and 0064/ll.17-20). Nakamura, however, fails to explicitly specify that an electric potential of the semiconductor control element is lower than an electric potential of each of the first drive element and the second drive element. Matsubara, in the same field of endeavor and in a similar device to Nakamura, teaches that potential differences may be present in semiconductor devices having semiconductor control and drive elements and that such potentials may be configured according to desired design specifications, wherein Matsubara further specifically teaches that a semiconductor control element having a lower potential than a drive element may be required for certain intended inverter applications, such as with electric and hybrid vehicles (see, e.g., Matsubara: pars.0005/ll.1-3 and 0036/ll.3-10).
Here, Nakamura’s express teachings that modulating potential for Nakamura’s elements can affect and adjust the performance and usage applications of these elements taken together with Matsubara’s disclosure that the potentials of semiconductor control and drive elements may be configured according to desired design specifications and intended external applications would have suggested to one of ordinary skill in the art that the potentials of semiconductor control and drive elements may be adjusted as a matter of routine optimization of a result-effective variable. Adjusting potentials to achieve predictable results, such as modified electrical/mechanical performance, as well as Nakamura’s and Matsubara’s express teachings of performance alterations and expanded external usage applicability, would have been well within the ordinary skill in the art. No evidence of criticality or unexpected results, that is, results different in kind and not merely degree, for the claimed dimensional relationship is apparent. Accordingly, the claimed limitation represents an obvious optimization of a result-effective variable.
Moreover, Matsubara is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would find particular incentive to have an electrical potential of the semiconductor control element be lower than an electric potential of each of the first drive element and the second drive element, as suggested by Matsubara, so as to expand the external applications of Nakamura’s inverter semiconductor device, for example, in electric and hybrid vehicles.
Nakamura, however, fails to explicitly specify a first insulating element located between the semiconductor control element and the first drive element in the first direction, the first insulating element relaying a signal transmitted from the semiconductor control element to the first drive element and providing electrical insulation between the semiconductor control element and the first drive element. Nakamura additionally fails to explicitly specify a second insulating element located between the semiconductor control element and the second drive element in the first direction, the second insulating element relaying a signal transmitted from the semiconductor control element to the second drive element and providing electrical insulation between the semiconductor control element and the second drive element.
Matsubara, in the same field of endeavor and in a similar device to Nakamura, teaches the use of an insulating element 12 between a semiconductor control element 111 and a drive element 112, wherein the insulating element is located between the semiconductor control element and the drive element in a first direction Y (see, e.g., Matsubara: fig. 2). Matsubara further denotes that such an insulating element relays a signal transmitted from the semiconductor control element to the drive element and provides electrical insulation between the semiconductor control element and the drive element (see, e.g., Matsubara: pars.0005/ll.4-6 and 0036/ll.1-6). Matsubara teaches that the use of such an insulating element and configuration to transmit electrical signals between the control and drive elements improves the insulation and dielectric strength of the device and is further necessary to account and adjust for voltage differences between the semiconductor control element and the drive element, all which ensure the performance of the semiconductor device (see, e.g., Matsubara: pars.0005/ll.1-6, 0036/ll.1-6, and 0037/ll.1-3).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include in Nakamura’s device a first insulating element located between the semiconductor control element and the first drive element in the first direction, the first insulating element relaying a signal transmitted from the semiconductor control element to the first drive element and providing electrical insulation between the semiconductor control element and the first drive element, and a second insulating element located between the semiconductor control element and the second drive element in the first direction, the second insulating element relaying a signal transmitted from the semiconductor control element to the second drive element and providing electrical insulation between the semiconductor control element and the second drive element, as Matsubara teaches the benefits of including an insulating element between a semiconductor control element and a drive element, so as to employ a protective insulative configuration that transmits electrical signals between Nakamura’s control and individual drive elements (wherein the individual drive elements are each disposed on opposite sides of Nakamura’s control element) in a manner that improves the insulation and dielectric strength of Nakamura’s device, thereby ensuring the performance of Nakamura’s device, while further accounting and adjusting for voltage differences between Nakamura’s semiconductor control and individual drive elements, thereby protecting each of the control and drive elements from voltage variances.
Regarding claim 2, Nakamura (see, e.g., fig. 7) shows that Nakamura’s semiconductor device further comprises an electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) including a first die pad DPC on which the semiconductor control element CPC is mounted, a second die pad DPH on which the first drive element CPH is mounted, and a third die pad DPL on which the second drive element CPL is mounted.
Regarding claim 5, Nakamura (see, e.g., fig. 7) shows that the electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) includes a plurality of input terminals LD5a, LD8 (see, e.g., pars.0067/ll.1-2 and 0113) arranged side by side in the first direction X, and at least one of the plurality of input terminals LD5a is electrically connected to the semiconductor control element CPC (see, e.g., pars.0098 and 0113/ll.1-6).
Regarding claim 8, Nakamura (see, e.g., fig. 7) shows that the plurality of input terminals LD5a, LD8 includes an input support terminal LD8 (see, e.g., par.0131/ll.1-4) connected to the first die pad DPC. Additionally, also regarding claim 8, Matsubara (see, e.g., Matsubara: fig. 2) also shows that the plurality of input terminals 3, 5 includes an input support terminal 51 connected to the first die pad 21.
Regarding claim 9, Nakamura (see, e.g., fig. 7) shows that the electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) further includes:
a plurality of first output terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2, 0084/ll.21-26, and 0117) arranged side by side in the first direction X, at least one LD2 of the plurality of first output terminals being electrically connected to the first drive element CPH (see, e.g., par.0135/ll.1-5); and
a plurality of second output terminals LD5b, LD3, LB3a (see, e.g., pars.0064/ll.3, 0084/ll.21-26, and 0126) arranged side by side in the first direction on the second side with respect to the plurality of first output terminal, at least one LD3 of the plurality of second output terminals being electrically connected to the second drive element CPL (see, e.g., par.0135/ll.7-10)
Regarding claim 10, Nakamura (see, e.g., fig. 7) shows that:
the plurality of first output terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2, 0084/ll.21-26, and 0117) include a single first output support terminal LD6 connected to the second die pad DPH (see, e.g., par.0132/ll.3-4); and
the plurality of second output terminals LD5b, LD3, LB3a (see, e.g., pars.0064/ll.3, 0084/ll.21-26, and 0126) include a single second output support terminal LB3a connected to the third die pad DPL (see, e.g., pars.0126 and 0132/ll.9-11)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura/Matsubara in view of Shirai (US 2020/0312750).
Regarding claim 3, Matsubara (see, e.g., Matsubara: fig. 2) shows that the first insulating element 12 is mounted on the first die pad 21. Furthermore, although Matsubara fails to illustrate that Matsubara’s device further comprises a second insulating element, it is clear to one of ordinary skill in the art that to achieve the necessary voltage accountancy and adjustment between a drive element and semiconductor control element taught by Matsubara that Nakamura’s device would need to encompass two insulating elements: an insulating element on the first side between Nakamura’s first drive element and semiconductor control element and an insulating element on the second side between Nakamura’s second drive element and semiconductor control element (see the comments stated above in paragraphs 5-11, which are considered to be repeated here). Since Matsubara teaches the affirmed functionality of including insulating elements on the first die pad (see, e.g., Matsubara: fig. 2 and par.0039/ll.1-7, wherein Matsubara cites the larger structure of the first die pad), it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Nakamura’s necessary second insulating element also on the first die pad.
Furthermore, Shirai, in the same field of endeavor and in a similar device to Nakamura/Matsubara, shows a semiconductor device A1 comprising a semiconductor control element 3, a first insulating element 24B, and a second insulating element 24A, wherein all three elements are mounted on a first die pad 46 (see, e.g., Shirai: fig. 2).
Shirai is evidence showing that one of ordinary skill in the art would appreciate that a first and second insulating element mounted on a first die pad would be equivalent to a first and second insulating element mounted in another configuration, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Nakamura/Matsubara. That is, insulating element configurations suggested by both Shirai and Nakamura/Matsubara would yield the predictable result of providing an insulative structure shielding and protecting adjacent conductive semiconductor elements.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first and second insulating element mounted on a first die pad, as taught by Shirai, or a first and second insulating element mounted in another configuration, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an insulative structure shielding and protecting adjacent conductive semiconductor elements. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 6-7, 11-12, and 14-16 and 18-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Response to Arguments
With regards to the claims, Applicant argues:
The combination of Nakamura and Matsubara cannot arrive at the claimed invention, which requires the use of (at least) two insulating elements with one control element.
The Examiner responds:
As discussed above in paragraphs 5-11, Matsubara teaches the benefits and protective value of including an insulating element between a semiconductor control element and a drive element. Furthermore, Nakamura teaches that Nakamura’s individual drive elements are disposed on opposite sides of Nakamura’s semiconductor control element (see, e.g., fig. 7). Accordingly, as taught by Matsubara and discussed above in paragraphs 5-11, one of ordinary skill in the art would be motivated to include an insulating element between Nakamura’s semiconductor control element and individual drive elements, that is, to include a first insulating element between Nakamura’s semiconductor control element and first drive element and a second insulating element between Nakamura’s semiconductor control element and second drive element, so as to ensure that an insulating element is beneficially and sufficiently included between each of Nakamura’s drive elements and Nakamura’s semiconductor control element.
Applicant’s amendments to the claims, filed on 04/21/2026, have overcome the 35 U.S.C. 112(b) rejections put forth in the previous Office action mailed on 01/28/2026. Accordingly, the 35 U.S.C. 112(b) rejections put forth in the previous Office action are hereby withdrawn.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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