Attorney Docket Number: 10921.1205USW1
Filing Date: 06/28/2023
Claimed Priority Dates: 12/06/2021 (CON of PCT/JP2021/044725)
01/04/2021 (JP 2021-000237)
Inventors: Kikuchi et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 11/11/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election without traverse of Species I, reading on figure 1, in the reply filed on 11/11/2025, is acknowledged. The applicant indicated that claims 1-3, 5-12, 14-16, and 18-19 read on the elected species. The examiner agrees. Accordingly, claims 4, 13, and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5-12 and 14 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5, 6, and 8 recite the limitation of a/the “plurality of input-side terminals”. It is unclear what “input-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “input side” or comprise “inputs”. Accordingly, there is insufficient antecedent basis for this limitation in the claim, as it is indistinct where or on what an “input-side” should be.
Claim 6 recites the limitations “an input-side first terminal that is located farthest on the first side” and “an input-side first terminal that is located farthest on the second side”. These limitations in the claims are indefinite, as it is not defined from what respectively and/or relatively to what the “input-side first terminals” must be farthest.
Claim 6 recites the limitations “an input-side first terminal” and “an input-side second terminal”. It is unclear what “input-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “input side” or comprise “inputs”. Accordingly, there is insufficient antecedent basis for this limitation in the claim, as it is indistinct where or on what an “input-side” should be.
Claim 8 recites the limitation an “input-side support terminal”. It is unclear what “input-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “input side” or comprise “inputs”. Accordingly, there is insufficient antecedent basis for this limitation in the claim, as it is indistinct where or on what an “input-side” should be.
Claims 9-12 and 14 recite the limitations “a plurality of first output-side terminals” and “a plurality of second output-side terminals”. It is unclear what “output-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “output side” or comprise “outputs”. Accordingly, there is insufficient antecedent basis for these limitations in the claim, as it is indistinct where or on what an “output-side” should be.
Claim 10 recites the limitations “a single first output-side support terminal” and “a single second output-side support terminal”. It is unclear what “output-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “output side” or comprise “output”. Accordingly, there is insufficient antecedent basis for this limitation in the claim, as it is indistinct where or on what an “output-side” should be.
Claims 11 and 12 recites the limitations “a first output-side innermost terminal” and “a second output-side innermost terminal”. It is unclear what “output-side” constitutes, as no side of any element of the semiconductor device has been previously sufficiently recited to be an “output side” or comprise “outputs”. Accordingly, there is insufficient antecedent basis for this limitation in the claim, as it is indistinct where or on what an “output-side” should be. Additionally, the limitations of “innermost” in the claims are indefinite, as it is unclear with respect to what such an “output-side terminal” must be innermost.
Claim 11 recites the limitations “a first output-side innermost terminal that is located farthest on the second side” and “a second output-side innermost terminal that is located farthest on the first side”. The limitations of “farthest” in the claim are indefinite, as it is not defined from what respectively and/or relatively to what the “output-side innermost terminal(s)” must be farthest.
Claim 7 depends from claims 5-6 and thus inherits the deficiencies identified supra.
All claims dependent upon the claims identified above additionally inherit the deficiencies of the claims identified supra.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2018/0218969) in view of Matsubara (US 2016/0307854).
Regarding claim 1, Nakamura (see, e.g., fig. 7) shows most aspects of the instant invention, including a semiconductor device comprising:
a semiconductor control element CPC;
a first drive element CPH located on a first side on a first direction X perpendicular to a thickness direction of the semiconductor control element with respect to the semiconductor control element, the first drive element receiving a signal transmitted from the semiconductor control element (see, e.g., pars.0060/ll.6-12 and 0061/ll.5-9);
a second drive element CPL located on a second side opposite the first side in the first direction with respect to the semiconductor control element, the second drive element receiving a signal transmitted from the semiconductor control element (see, e.g., pars.0060/ll.6-12 and 0061/ll.5-9); and
a sealing resin MR covering the semiconductor control element
Nakamura teaches most aspects of the instant invention. Nakamura further teaches that Nakamura’s semiconductor control and drive elements operate at varying high and low voltages (see, e.g., pars.0061 and 0064/ll.17-20). Nakamura, however, fails to explicitly specify a first insulating element located between the semiconductor control element and the first drive element in the first direction, the first insulating element relaying a signal transmitted from the semiconductor control element to the first drive element and providing electrical insulation between the semiconductor control element and the first drive element. Nakamura additionally fails to explicitly specify a second insulating element located between the semiconductor control element and the second drive element in the first direction, the second insulating element relaying a signal transmitted from the semiconductor control element to the second drive element and providing electrical insulation between the semiconductor control element and the second drive element.
Matsubara, in the same field of endeavor and in a similar device to Nakamura, teaches the use of an insulating element 12 between a semiconductor control element 111 and a drive element 112, wherein the insulating element is located between the semiconductor control element and the drive element in a first direction Y (see, e.g., Matsubara: fig. 2). Matsubara further denotes that such an insulating element relays a signal transmitted from the semiconductor control element to the drive element and provides electrical insulation between the semiconductor control element and the drive element (see, e.g., Matsubara: pars.0005/ll.4-6 and 0036/ll.1-6). Matsubara teaches that the use of such an insulating element and configuration to transmit electrical signals between the control and drive elements is necessary to account and adjust for voltage differences between the semiconductor control element and the drive element, ensuring the performance of the semiconductor device (see, e.g., Matsubara: pars.0005/ll.1-6, 0036/ll.1-6, and 0037/ll.1-3).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include in Nakamura’s device a first insulating element located between the semiconductor control element and the first drive element in the first direction, the first insulating element relaying a signal transmitted from the semiconductor control element to the first drive element and providing electrical insulation between the semiconductor control element and the first drive element, and a second insulating element located between the semiconductor control element and the second drive element in the first direction, the second insulating element relaying a signal transmitted from the semiconductor control element to the second drive element and providing electrical insulation between the semiconductor control element and the second drive element, as taught by Matsubara, so as to employ a protective insulative configuration that transmits electrical signals between Nakamura’s control and individual drive elements in a manner accounting and adjusting for voltage differences between Nakamura’s semiconductor control and individual drive elements, protecting each of the control and drive elements from voltage variances and ensuring the performance of Nakamura’s device.
Regarding claim 2, Nakamura (see, e.g., fig. 7) shows that Nakamura’s semiconductor device further comprises an electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) including a first die pad DPC on which the semiconductor control element CPC is mounted, a second die pad DPH on which the first drive element CPH is mounted, and a third die pad DPL on which the second drive element CPL is mounted.
Regarding claim 5, Nakamura (see, e.g., fig. 7) shows that the electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) includes a plurality of terminals LD5a, LD8 (see, e.g., pars.0067/ll.1-2) arranged side by side in the first direction X, and at least one of the plurality of terminals LD5a is electrically connected to the semiconductor control element CPC (see, e.g., pars.0098 and 0113/ll.1-6).
Regarding claim 8, Nakamura (see, e.g., fig. 7) shows that the plurality of terminals LD5a, LD8 includes a support terminal LD8 (see, e.g., par.0131/ll.1-4) connected to the first die pad DPC. Additionally, also regarding claim 8, Matsubara (see, e.g., Matsubara: fig. 2) also shows that the plurality of terminals 3, 5 includes a support terminal 51 connected to the first die pad 21.
Regarding claim 9, Nakamura (see, e.g., fig. 7) shows that the electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) further includes:
a plurality of first terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2 and 0084/ll.21-26) arranged side by side in the first direction X, at least one LD2 of the plurality of first terminals being electrically connected to the first drive element CPH (see, e.g., par.0135/ll.1-5); and
a plurality of second terminals LD4, LD7 (see, e.g., pars.0063/ll.6-8 and 0084/ll.21-26) arranged side by side in the first direction on the second side with respect to the plurality of first terminal, at least one LD4 of the plurality of second terminals being electrically connected to the second drive element CPL (see, e.g., par.0135/ll.7-10)
Regarding claim 10, Nakamura (see, e.g., fig. 7) shows that:
the plurality of first terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2 and 0084/ll.21-26) include a single first support terminal LD6 connected to the second die pad DPH (see, e.g., par.0132/ll.3-4); and
the plurality of second terminals LD4, LD7 (see, e.g., pars.0063/ll.6-8 and 0084/ll.21-26) include a single second support terminal LD7 connected to the third die pad DPL (see, e.g., par.0132/ll.9-11)
Regarding claim 9, Nakamura (see, e.g., fig. 7) shows that the electroconductive support member DPC/DPH/DPL/LD (see, e.g., par.0087) further includes:
a plurality of first terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2 and 0084/ll.21-26) arranged side by side in the first direction X, at least one LD2 of the plurality of first terminals being electrically connected to the first drive element CPH (see, e.g., par.0135/ll.1-5); and
a plurality of second terminals LD5b, LD3, LB3a (see, e.g., pars.0064/ll.3, 0084/ll.21-26, and 0126) arranged side by side in the first direction on the second side with respect to the plurality of first terminal, at least one LD3 of the plurality of second terminals being electrically connected to the second drive element CPL (see, e.g., par.0135/ll.7-10)
Regarding claim 10, Nakamura (see, e.g., fig. 7) shows that:
the plurality of first terminals LD2, LD6 (see, e.g., pars.0064/ll.1-2 and 0084/ll.21-26) include a single first support terminal LD6 connected to the second die pad DPH (see, e.g., par.0132/ll.3-4); and
the plurality of second terminals LD5b, LD3, LB3a (see, e.g., pars.0064/ll.3, 0084/ll.21-26, and 0126) include a single second support terminal LB3a connected to the third die pad DPL (see, e.g., pars.0126 and 0132/ll.9-11)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura/Matsubara in view of Shirai (US 2020/0312750).
Regarding claim 3, Matsubara (see, e.g., Matsubara: fig. 2) shows that the first insulating element 12 is mounted on the first die pad 21. Furthermore, although Matsubara fails to illustrate that Matsubara’s device further comprises a second insulating element, it is clear to one of ordinary skill in the art that to achieve the necessary voltage accountancy and adjustment between a drive element and semiconductor control element taught by Matsubara that Nakamura’s device would need to encompass two insulating elements: an insulating element on the first side between Nakamura’s first drive element and semiconductor control element and an insulating element on the second side between Nakamura’s second drive element and semiconductor control element (see the comments stated above in paragraphs 17-20, which are considered to be repeated here). Since Matsubara teaches the affirmed functionality of including insulating elements on the first die pad (see, e.g., Matsubara: fig. 2 and par.0039/ll.1-7, wherein Matsubara cites the larger structure of the first die pad), it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Nakamura’s necessary second insulating element also on the first die pad.
Furthermore, Shirai, in the same field of endeavor and in a similar device to Nakamura/Matsubara, shows a semiconductor device A1 comprising a semiconductor control element 3, a first insulating element 24B, and a second insulating element 24A, wherein all three elements are mounted on a first die pad 46 (see, e.g., Shirai: fig. 2).
Shirai is evidence showing that one of ordinary skill in the art would appreciate that a first and second insulating element mounted on a first die pad would be equivalent to a first and second insulating element mounted in another configuration, and that such differences would result in no unexpected changes in the performance of the integrated circuit structure of Nakamura/Matsubara. That is, insulating element configurations suggested by both Shirai and Nakamura/Matsubara would yield the predictable result of providing an insulative structure shielding and protecting adjacent conductive semiconductor elements.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a first and second insulating element mounted on a first die pad, as taught by Shirai, or a first and second insulating element mounted in another configuration, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing an insulative structure shielding and protecting adjacent conductive semiconductor elements. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 6-7, 11-12, and 14 are objected to but would be allowable if rewritten (1) to overcome the 112(b) rejections put forth in this Office action and (2) in independent form including all the limitations of the base claim and any intervening claims.
Claims 15-16 and 18-19 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814