DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C.
119 (a)-(d).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/28/2023, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species A, Figure 1-12, and Claims 1-6 in the reply filed on 11/06/2025 is acknowledged. Claims 7 – 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/06/2025.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0013] on page 5 recites “when flip-flop mounting in performed”; this should be written as “when flip-chip mounting is performed.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is indefinite due to the following reasons:
The limitation "a semiconductor chip mounted on the multi-layer substrate by flip-chip mounting and having an internal circuit” does not clearly state whether the internal circuit is part of the semiconductor chip or the multi-layer substrate. The examiner interprets this limitation as a semiconductor chip having an internal circuit is mounted on the multi-layer substrate.
The limitation “the plural pads include an electrode pad connected with the internal circuit and plural inspection pads formed in at least three parts in four corners” is unclear whether the electrode pad is a single “electrode pad” within the set of pads or whether the electrode pad is part of the plural inspection pads or separate from them. It is also unclear which of the plural pads are not connected with the internal circuit. The examiner interprets this limitation as including one electrode pad connected to the internal circuit, and the inspection pads formed in at least three of the four corners that are not connected to the internal circuit.
The limitation “plural inspection pads formed in at least three parts in four corners” is unclear whether three or four inspection pads are used and how the inspection pads are distributed among the four corners. The examiner interprets this limitation as inspection pads being formed in at least three of the four corners.
The limitation “a line connects the adjacent inspection pads with each other” is unclear as to whether “a line” connect all of the inspection pads or whether there are plurality of “lines” connecting adjacent inspection pad pairs. The examiner interprets this limitation as a single line connecting all the inspection pads in the three corners.
Claim 2 is indefinite because the phrase “the plural inspection pads include first to fourth inspection pads formed in four corners” is unclear whether one inspection pad is formed in each of the four corners or four inspection pads are formed in each of the four corners. The examiner interprets the limitation as one inspection pad being formed in each corner.
Claim 3 is indefinite because the limitation “a fifth inspection pad” which lacks proper antecedent basis, since claim 1 does not introduce first through fourth inspection pads.
Claim 4 recites “a resistance is connected between the adjacent inspection pads”; the word “resistance” should be replaced with “resistor” or “resistive component” or “resistive element”.
Claims 5 and 6 are rejected because they are dependent on Claims 2 and 1 respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Nose et al. (US20030042618A1; hereinafter Nose) in view of Hanada (JPH09116245A; hereinafter Hanada).
Regarding Claim 1, Nose discloses a semiconductor device (semiconductor device 19, FIG. 2 reproduced below, [0053]) comprising:
a multi-layer substrate (wiring substrate 2 has a multi-layer interconnection constituted by a stack of plural insulating substrates, FIG. 2, [0061]); and
a semiconductor chip mounted on the multi-layer substrate (semiconductor chip 1 mounted on substrate 2, FIG. 2, [0054]) by flip-chip mounting (face down mounting, [0009]) and having an internal circuit (system circuit as an integrated circuit, with both a memory circuit and a logical operation circuit, [0056]),
wherein plural pads (plural electrode pads 10 and eight inspection electrode pads 11a to 11h) are formed on a front surface (main surface 1X) of the semiconductor chip (1), FIG. 2, [0056].
plural pillars (solder bumps or conductive bumps 3) are respectively formed on the plural pads (plural electrode pads 10 and eight inspection electrode pads 11a to 11h), FIG. 2, [0068].
plural upper-surface electrodes (20) are formed on an upper surface of the multi-layer substrate (main surface 2X of the wiring substrate 2), FIG. 2, [0068],
plural lower-surface electrodes (26) are formed on a lower surface of the multi-layer substrate (rear surface 2Y of wiring substrate 2) and are respectively connected with the plural upper-surface electrodes (20), (the plural electrode pads 26 are electrically connected respectively to the plural electrode pads 20, FIG. 2, [0073]),
the plural pillars (3) are joined to the plural upper-surface electrodes (20) by solder (solder bumps 3 are melted and thereafter cured to connect the electrode pads on the semiconductor chip 1 and the electrode pads 20), FIG. 2, [0078],
the plural pads include an electrode pad (10) connected with the internal circuit (the plural electrode pads 10 are electrically connected an integrated circuit), [0060],
and plural inspection pads (11a to 11h) formed in at least three parts in four corners (first corner 1a, second corner 1b, third corner 1c, fourth corner 1d) on the front surface (1X) of the semiconductor chip (1) and not connected with the internal circuit (electrically isolated from the integrated circuit incorporated in the semiconductor chip 1), FIG. 6, [0059], [0060], and
a line connects the adjacent inspection pads with each other (wiring line 13a connects 11a and 11b, wiring line 13b connects 11c and 11d, wiring line 13c connects 11e and 11f, wiring line 13d connects 11g and 11h), FIG. 6, [0058].
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Nose: FIG. 2
Nose does not disclose “plural lower-surface electrodes connected with the plural upper-surface electrodes via through holes.”
In a similar art, Hanada discloses electronic component manufacturing method and the method comprising the external connection terminal and the inspection, [0015].
Hanada discloses a: plural lower-surface electrodes (pattern of wirings 26e-26h on the other side of the substrate) connected with the plural upper-surface electrodes (pads 181-184 on the main side of the substrate) via through holes (through holes 191-194 and wiring lines 181a – 184a), FIGS. 1, 2, [0020].
Hanada discloses that a semiconductor device as taught can enable easy performance of function check of the semiconductor chip [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose’s device in order to easily check the functionality of the semiconductor chip as disclosed by Hanada [0005].
Regarding Claim 2, The combination of Nose and Hanada disclose the semiconductor device according to claim 1.
Nose discloses: wherein the plural inspection pads (11a to 11h) include first to fourth inspection pads formed in four corners (11a, 11b formed in the first corner 1a; 11c, 11d formed in the second corner 1b; 11e, 11f formed in the third corner 1c; 11g, 11h formed in the fourth corner 1d) on the front surface (1X) of the semiconductor chip (1), FIG. 6, [0059].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Seo (US20220013419A1; hereinafter Seo).
Regarding Claim 3, The combination of Nose and Hanada disclose the semiconductor device according to claim 1.
The combination of Nose and Hanada does not disclose “wherein the plural inspection pads include a fifth inspection pad formed in a central portion of the front surface of the semiconductor chip.”
In a similar art, Seo discloses a semiconductor package including a semiconductor chip 100, [0002], [0026].
Seo discloses measurement connection electrode 130 with first and second center measurement connection electrodes 130C1 and 130C2 that are disposed in the center region CR, FIG. 1A, [0033].
The combination of Nose and Seo disclose: wherein the plural inspection pads (Nose:11a to 11h) include a fifth inspection pad (Seo: 130C1, 130C2) formed in a central portion of the front surface of the semiconductor chip (Nose: 1).
Seo discloses that a semiconductor device as taught enables easy and accurate detection of a connection failure between a semiconductor chip and a substrate [0098]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device in order to detect connection failures easily and accurately as disclosed by Seo [0098].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Chang et al. (US20150109013A1; hereinafter Chang).
Regarding Claim 4, The combination of Nose and Hanada disclose the semiconductor device according to claim 1.
The combination of Nose and Hanada does not disclose “wherein a resistance is connected between the adjacent inspection pads.”
In a similar art, Chang discloses a semiconductor device and a method of testing the same [0002].
Chang discloses the first resistance pattern RPb1 may be connected to the first and second probe test pads PPb1 and PPb2, the second resistance pattern RPb2 may be connected to the third and fourth probe test pads PPb3 and PPb4, and the i-th resistance pattern RPbi may be connected to the n−1th and n-th probe test pads PPn-1 and PPn, FIG. 6, [0067].
The combination of Nose and Chang disclose: wherein a resistance (Chang: RPb1, RPb2, RPb3, RPb4) is connected between the adjacent inspection pads (11a-11h), FIG. 6, [0067].
Chang discloses that a semiconductor device as taught provides an efficient method of testing the reliability of the semiconductor device [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device, in order to provide an efficient method of testing the reliability as disclosed by Chang [0003].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Liao et al. (US20080277777A1; hereinafter Liao).
Regarding Claim 6, The combination of Nose and Hanada disclose the semiconductor device according to claim 1.
The combination of Nose and Hanada does not disclose “comprising a heat sink die-bonded to a back surface of the semiconductor chip, and a mold resin sealing the multi-layer substrate, the semiconductor chip, and the heat sink, wherein an upper surface of the heat sink is exposed from the mold resin.”
In a similar art, Liao discloses a semiconductor package that integrates with a heat dissipation member [0002].
The combination of Nose and Liao discloses a semiconductor device comprising a heat sink (Liao: heat dissipation member 43) die-bonded to a back surface of the semiconductor chip (Liao: semiconductor chip 41) and a mold resin sealing (Liao: encapsulant 44) the multi-layer substrate (Nose: wiring substrate 2, FIG. 2, [0061]), the semiconductor chip (Liao: 41), and the heat sink (Liao: 43), wherein an upper surface of the heat sink (Liao: 43) is exposed from the mold resin (Liao: 44, FIG. 4E, [0032]).
Liao discloses that a semiconductor package as taught improves heat dissipation of the package [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device, in order to improve heat dissipation as disclosed by Liao [0004].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Suwa et al. (WO9612296A1; hereinafter Suwa), still further in view of Kazuyuki (US20050212147A1; hereinafter Kazuyuki).
Regarding Claim 5, The combination of Nose and Hanada disclose the semiconductor device according to claim 2.
The combination of Nose and Hanada does not disclose “further comprising a printed substrate on which the multi-layer substrate is mounted.”
In a similar art, Suwa discloses a semiconductor device with a face-down semiconductor chip, [0020].
Suwa discloses: further comprising a printed substrate (wiring board 22, [0074]) on which the multi-layer substrate (tape 4, [0046]) is mounted, FIGS. 16A, B, [0091].
The combination of Hanada and Suwa disclose: and the lower-surface electrode (Hanada: pattern of wiring 26h) connected to any one of the plural inspection pads (Hanada: pad 184) is connected to a GND terminal (Hanada: ground external connection terminal 161, FIGS. 1, 2, [0020], [0028]) of the printed substrate (Suwa: wiring board 22, [0074]).
Suwa discloses that a semiconductor device as taught improves signal transmission characteristics and improves manufacturing yield [0023], [0096]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device, in order to improve signal transmission characteristics and improve manufacturing yield as disclosed by Suwa [0023], [0096].
The combination of Nose, Hanada, and Suwa does not disclose “wherein the line is formed along an outer circumference of the front surface of the semiconductor chip.”
In a similar art, Kazuyuki discloses a semiconductor wafer, semiconductor chip, and method of inspection of a semiconductor chip [0002].
Kazuyuki discloses: wherein the line (inspection wire 4) is formed along an outer circumference of the front surface of the semiconductor chip (4 extends over the entire periphery of the chip areas 2), FIG. 1A, [0042].
Kazuyuki discloses that a semiconductor device as taught improves the reliability of the device [0063]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose, Hanada, and Suwa’s device, in order to improve the reliability as disclosed by Kazuyuki [0063].
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna Palaniswamy whose telephone number is
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supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-273-8300.
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899