DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claims 1 – 5 and newly added claims 15 - 19 have been fully considered. Based on the cited prior arts Nose, Hanada, Seo, Chang, Suwa, and Liao and new grounds of rejection from Uno (JP4949733B2) the claims 1 – 6 and 15 - 19 are rejected.
Response to Amendment
Applicant’s amendments to the specification has been fully considered and resolve the rejections. The specification rejections has been withdrawn.
Applicant’s amendments to claims 1- 5 has been fully considered and resolve the indefiniteness. The 35 U.S.C. 112(b) rejections to claims 1-6 has been withdrawn.
Applicant’s newly added claims 15-19 have been considered and examined.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 16 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16 on page 6 recites “wherein the resistive component is connected between two of the plural lines.” A review of the specification finds no support for this limitation. The closest support is found in paragraph [0024] which recites “A resistance R1 is connected between the adjacent inspection pads 61a and 61b. A resistance R2 is connected between the adjacent inspection pads 61b and 61c. A resistance R3 is connected between the adjacent inspection pads 61c and 61d. A resistance R4 is connected between the adjacent inspection pads 61a and 61e”, but does not disclose the resistive component is connected between two of the plural lines.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Nose et al. (US20030042618A1; hereinafter Nose) in view of Hanada (JPH09116245A; hereinafter Hanada), further in view of Uno (JP2007305763A; hereinafter Uno).
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Regarding Claim 1, (Currently Amended) Nose discloses a semiconductor device (semiconductor device 19, FIG. 2 reproduced above, [0053]) comprising:
a multi-layer substrate (wiring substrate 2 has a multi-layer interconnection constituted by a stack of plural insulating substrates, FIG. 2, [0061]); and
a semiconductor chip mounted on the multi-layer substrate (semiconductor chip 1 mounted on substrate 2, FIG. 2, [0054]) by flip-chip mounting (face down mounting, [0009]), the semiconductor chip having an internal circuit (system circuit as an integrated circuit, with both a memory circuit and a logical operation circuit, [0056]),
wherein plural pads (plural electrode pads 10 and eight inspection electrode pads 11a to 11h) are formed on a front surface (main surface 1X) of the semiconductor chip (1), FIG. 2, [0056].
plural pillars (solder bumps or conductive bumps 3) are respectively formed on the plural pads (plural electrode pads 10 and eight inspection electrode pads 11a to 11h), FIG. 2, [0068].
plural upper-surface electrodes (20) are formed on an upper surface of the multi-layer substrate (main surface 2X of the wiring substrate 2), FIG. 2, [0068],
plural lower-surface electrodes (26) are formed on a lower surface of the multi-layer substrate (rear surface 2Y of wiring substrate 2) and are respectively connected with the plural upper-surface electrodes (20), (the plural electrode pads 26 are electrically connected respectively to the plural electrode pads 20, FIG. 2, [0073]),
the plural pillars (3) are joined to the plural upper-surface electrodes (20) by solder (solder bumps 3 are melted and thereafter cured to connect the electrode pads on the semiconductor chip 1 and the electrode pads 20), FIG. 2, [0078],
the plural pads include an electrode pad (10) connected with the internal circuit (the plural electrode pads 10 are electrically connected an integrated circuit), [0060],
plural inspection pads (11a to 11h) formed on the front surface (1X) of the semiconductor chip (1) such that at least three of four corners on the front surface of the semiconductor chip include one of the inspection pads (the electrode pads 11a and 11b for inspection are disposed at a first corner 1a of the semiconductor chip 1, the electrode pads 11c and 11d for inspection are disposed at a second corner 1b of the chip, the electrode pads 11e and 11f for inspection are disposed at a third corner 1c of the chip, and the electrode pads 11g and 11h for inspection are disposed at a fourth corner 1d, FIG. 6, [0059]),
the inspection pads (11a to 11h) not being connected with the internal circuit (electrically isolated from the integrated circuit incorporated in the semiconductor chip 1, [0060]).
the semiconductor chip (1) comprises plural lines (wiring lines 13a, 13b, 13c, 13d), each one of the plural lines connecting adjacent inspection pads among the plural inspection pads with each other (wiring line 13a connects 11a and 11b, wiring line 13b connects 11c and 11d, wiring line 13c connects 11e and 11f, wiring line 13d connects 11g and 11h), FIG. 6, [0058].
Nose does not disclose “plural lower-surface electrodes connected with the plural upper-surface electrodes via through holes.”
In a similar art, Hanada discloses electronic component manufacturing method and the method comprising the external connection terminal and the inspection, [0015].
Hanada discloses a: plural lower-surface electrodes (pattern of wirings 26e-26h on the other side of the substrate) connected with the plural upper-surface electrodes (pads 181-184 on the main side of the substrate) via through holes (through holes 191-194 and wiring lines 181a – 184a), FIGS. 1, 2, [0020].
Hanada discloses that a semiconductor device as taught can enable easy and proper function check of the semiconductor chip [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose’s device in order to enable easy and proper function check of the semiconductor chip as disclosed by Hanada [0005].
The combination of Nose and Hanada does not disclose “each of the plural lines electrically connect to the adjacent inspection pads that are located at adjacent corners of the semiconductor chip.”
In a similar art, Uno discloses a semiconductor device including a semiconductor chip 10 on a substrate 11, [0006].
each of the plural lines (wiring portion 15) electrically connect to the adjacent inspection pads (probing pads 14) that are located at adjacent corners of the semiconductor chip (10), FIG. 12 reproduced above, [0007].
Uno [0007] discloses a semiconductor chip 10 having four corner probing pads 14 and four elongated wiring portions 15. As shown in FIG. 12 each wiring portion 15 electrically connects adjacent probing pads 14 located at adjacent corners of the semiconductor chip.
Uno discloses that a semiconductor device as taught enables defect detection in the periphery of the chip [0006], [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device in order to detect defects in the periphery of the semiconductor chip as disclosed by Uno [0006], [0007].
Regarding Claim 2, (Currently Amended) The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 1.
Nose discloses: wherein the plural inspection pads include a first inspection pad (11a, 11b) formed in a first corner (1a) on the front surface of the semiconductor chip (1X), a second inspection pad (11c, 11d) formed in a second corner (1b) on the front surface (1X) of the semiconductor chip, a third inspection pad (11e, 11f) formed in a third corner (1c) on the front surface (1X) of the semiconductor chip, and a fourth inspection pad (11g, 11h) formed in a fourth corner (1d) on the front surface (1X) of the semiconductor chip (1), FIG. 6, [0059].
Uno discloses: wherein the plural inspection pads include a first inspection pad (probing pad 14) formed in a first corner on the front surface (surface of the substrate 11) of the semiconductor chip (10), a second inspection pad (probing pad 14) formed in a second corner on the front surface (surface of the substrate 11) of the semiconductor chip (10), a third inspection pad (probing pad 14) formed in a third corner on the front surface (surface of the substrate 11) of the semiconductor chip (10), and a fourth inspection pad (probing pad 14) formed in a fourth corner on the front surface (surface of the substrate 11) of the semiconductor chip (10), FIG. 12, [0007].
Uno discloses that a semiconductor device as taught enables defect detection in the periphery of the chip [0006], [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device in order to detect defects in the periphery of the semiconductor chip as disclosed by Uno [0006], [0007].
Regarding Claim 17, (New) The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 1.
The combination of Nose and Hanada does not disclose “wherein each of the at least three of four corners on the front surface of the semiconductor chip includes only a single one of the plural inspection pads.”
Uno discloses: wherein each of the at least three of four corners on the front surface of the semiconductor chip (10) includes only a single one of the plural inspection pads (probing pads 14), FIG. 12, [0007].
Uno [0007] discloses a semiconductor chip 10 having four corner probing pads 14 and four elongated wiring portions 15. As shown in FIG. 12 each wiring portion 15 electrically connects adjacent probing pads 14 located at adjacent corners of the semiconductor chip. Thereby only a single inspection pad (probing pad 14) is at each of the at least three of the four corners of the chip 10.
Uno discloses that a semiconductor device as taught enables defect detection in the periphery of the chip [0006], [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose and Hanada’s device in order to detect defects in the periphery of the semiconductor chip as disclosed by Uno [0006], [0007].
Claim 3, 15, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Uno, still further in view of Seo (US20220013419A1; hereinafter Seo).
Regarding Claim 3 (Currently Amended), The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 1.
The combination of Nose, Hanada, and Uno does not disclose “wherein one of the plural inspection pads is formed in a central portion of the front surface of the semiconductor chip.”
In a similar art, Seo discloses a semiconductor package including a semiconductor chip 100, [0002], [0026].
Seo discloses measurement connection electrode 130 may include first and second center measurement connection electrodes 130C1 and 130C2 respectively, that are disposed in the center region CR, FIG. 1A, [0033].
The combination of Nose, Hanada, Uno, and Seo disclose: wherein one of the plural inspection pads (Seo: 130C1, 130C2) formed in a central portion of the front surface of the semiconductor chip (Nose: 1).
Seo discloses that a semiconductor device as taught enables easy and accurate detection of a connection failure between a semiconductor chip and a substrate [0098]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose, Hanada, and Uno’s device in order to easily and accurately detect connection failures as disclosed by Seo [0098].
Regarding Claim 15, (New) The combination of Nose, Hanada, Uno, and Seo discloses the semiconductor device according to claim 3.
The combination of Nose, Hanada, and Uno does not disclose “wherein only a single inspection pad among the plural inspection pads is formed in the central portion of the front surface of the semiconductor chip.”
Seo discloses measurement connection electrode 130 may include first and second center measurement connection electrodes 130C1 and 130C2 respectively, that are disposed in the center region CR, FIG. 1A, [0033].
The combination of Nose, Hanada, Uno, and Seo discloses: wherein only a single inspection pad (Seo: 130C1, [0033]) among the plural inspection pads is formed in the central portion (Seo: CR) of the front surface of the semiconductor chip (Nose:1).
It would be obvious to try modifying the device by forming only a single center inspection pad instead of first and second center inspection pads because selecting the number of center inspection pads involves choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success.
Seo discloses that a semiconductor device as taught enables easy and accurate detection of a connection failure between a semiconductor chip and a substrate [0098]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to detect connection failures easily and accurately as disclosed by Seo [0098].
Regarding Claim 19, (New) The combination of Nose, Hanada, Uno, and Seo discloses the semiconductor device according to claim 3.
The combination of Nose, Hanada, and Uno does not disclose “wherein the one of the plural inspection pads formed in the central portion is connected to one of the adjacent inspection pads by another line.”
Seo discloses measurement connection electrode 130 may include first and second center measurement connection electrodes 130C1 and 130C2 respectively, that are disposed in the center region CR, FIG. 1A, [0033].
Seo discloses: wherein the one of the plural inspection pads (130C1) formed in the central portion (CR) is connected to one of the adjacent inspection pads (130E1) by another line (114), FIG. 1A, [0034].
Seo discloses that a semiconductor device as taught enables easy and accurate detection of a connection failure between a semiconductor chip and a substrate [0098]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to detect connection failures easily and accurately as disclosed by Seo [0098].
Claims 4 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Uno, still further in view of Chang et al. (US20150109013A1; hereinafter Chang).
Regarding Claim 4, (Currently Amended) The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 1.
The combination of Nose, Hanada, and Uno does not disclose “wherein a resistive component is connected between two of the adjacent inspection pads.”
In a similar art, Chang discloses a semiconductor device and a method of testing the same [0002].
Chang discloses the first resistance pattern RPb1 may be connected to the first and second probe test pads PPb1 and PPb2, the second resistance pattern RPb2 may be connected to the third and fourth probe test pads PPb3 and PPb4, and the i-th resistance pattern RPbi may be connected to the n−1th and n-th probe test pads PPn-1 and PPn, FIG. 6, [0067].
Uno [0007] discloses a semiconductor chip 10 having four corner probing pads 14 and four elongated wiring portions 15. As shown in FIG. 12 each wiring portion 15 electrically connects adjacent probing pads 14 located at adjacent corners of the semiconductor chip.
The combination of Nose, Hanada, Uno, and Chang discloses: wherein a resistive component (Chang: RPb1, RPb2, RPb3, RPb4, FIG. 6, [0067]) is connected between two of the adjacent inspection pads (Uno: adjacent probe pads 14).
Chang discloses that a semiconductor device as taught provides an efficient method of testing the reliability of the semiconductor device [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose, Hanada, and Uno’s device, in order to provide an efficient method of testing the reliability as disclosed by Chang [0003].
Regarding Claim 16, (New) The combination of Nose, Hanada, Uno, and Chang discloses the semiconductor device according to claim 4.
The combination of Nose, Hanada, and Uno does not disclose “wherein the resistive component is connected between two of the plural lines.”
Uno [0007] discloses a semiconductor chip 10 having four corner probing pads 14 and four elongated wiring portions 15. As shown in FIG. 12 each wiring portion 15 electrically connects adjacent probing pads 14 located at adjacent corners of the semiconductor chip.
Chang [0062] discloses the first resistance pattern RPa1 may be connected to the first and second probe test pads PPa1 and PPa2, and the second resistance pattern RPa2 may be connected to the first and third probe test pads PPa1 and PPa3 in the first probe test group PG1. Chang FIG. 5 shows the resistance pattern RPa1 is connected between a conductive line associated with PPa2 and another conductive line associated with PPa1.
The combination of Nose, Hanada, Uno, and Chang discloses: wherein the resistive component (Chang: RPa1) is connected between two of the plural lines (Uno: two of the wiring portions 15, FIG. 12, [0007]).
Chang discloses that a semiconductor device as taught provides an efficient method of testing the reliability of the semiconductor device [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide an efficient method of testing the reliability as disclosed by Chang [0003].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Uno, still further in view of Suwa et al. (WO9612296A1; hereinafter Suwa).
Regarding Claim 5, (Currently Amended) The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 2.
Uno discloses: wherein the plural lines (wiring portion 15) are formed along an outer circumference of the front surface of the semiconductor chip (10), FIG. 12, [0007].
The combination of Nose, Hanada, and Uno does not disclose “further comprising a printed substrate on which the multi-layer substrate is mounted; and the lower-surface electrode connected to any one of the plural inspection pads is connected to a GND terminal of the printed substrate.”
In a similar art, Suwa discloses a semiconductor device with a face-down semiconductor chip, [0020].
Suwa discloses: further comprising a printed substrate (wiring board 22, [0074]) on which the multi-layer substrate (tape 4, [0046]), FIGS. 16A, B, [0091].
The combination of Nose, Hanada, Uno, and Suwa disclose: the lower-surface electrode (Hanada: pattern of wiring 26e) connected to any one of the plural inspection pads (Hanada: inspection pad 181, [0023]) is connected to a GND terminal (Hanada: ground external connection terminal 161, FIGS. 1, 2, [0022], [0027],) of the printed substrate (Suwa: wiring board 22, [0074]).
Hanada [0023] discloses wiring 26e is communicated to the inspection pad 181 formed on the one surface side of the substrate through the through hole 191. Hanada [0022], [0027] discloses wiring 26e is electrically connected to ground wiring 26a, which is connected to ground external connection terminal 161.
Suwa discloses that a semiconductor device as taught improves signal transmission characteristics and improves manufacturing yield [0023], [0096]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose, Hanada, and Uno’s device, in order to improve signal transmission characteristics and improve manufacturing yield as disclosed by Suwa [0023], [0096].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Uno, still further in view of Liao et al. (US20080277777A1; hereinafter Liao).
Regarding Claim 6 (Original), The combination of Nose, Hanada, and Uno discloses the semiconductor device according to claim 1.
The combination of Nose, Hanada, and Uno does not disclose “comprising a heat sink die-bonded to a back surface of the semiconductor chip, and a mold resin sealing the multi-layer substrate, the semiconductor chip, and the heat sink, wherein an upper surface of the heat sink is exposed from the mold resin.”
In a similar art, Liao discloses a semiconductor package that integrates with a heat dissipation member [0002].
The combination of Nose, Hanada, Uno, and Liao discloses a semiconductor device comprising a heat sink (Liao: heat dissipation member 43) die-bonded to a back surface of the semiconductor chip (Liao: semiconductor chip 41) and a mold resin sealing (Liao: encapsulant 44) the multi-layer substrate (Nose: wiring substrate 2, FIG. 2, [0061]), the semiconductor chip (Liao: 41), and the heat sink (Liao: 43), wherein an upper surface of the heat sink (Liao: 43) is exposed from the mold resin (Liao: 44, FIG. 4E, [0032]).
Liao discloses that a semiconductor package as taught improves heat dissipation of the package [0004]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Nose, Hanada, and Uno’s device, in order to improve heat dissipation as disclosed by Liao [0004].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Nose in view of Hanada, further in view of Uno, still further in view of Seo, yet still further in view of Chang.
Regarding Claim 18, (New) The combination of Nose, Hanada, Uno, and Seo discloses the semiconductor device according to claim 3.
The combination of Nose, Hanada, and Uno does not disclose “wherein a resistive component is connected between the one of the plural inspection pads that is formed in the central portion and one of the adjacent inspection pads.”
Seo discloses measurement connection electrode 130 may include first and second center measurement connection electrodes 130C1 and 130C2 respectively, that are disposed in the center region CR, FIG. 1A, [0033].
Chang discloses the first resistance pattern RPb1 may be connected to the first and second probe test pads PPb1 and PPb2, the second resistance pattern RPb2 may be connected to the third and fourth probe test pads PPb3 and PPb4, and the i-th resistance pattern RPbi may be connected to the n−1th and n-th probe test pads PPn-1 and PPn, FIG. 6, [0067].
The combination of Nose, Hanada, Uno, Seo, and Chang discloses: wherein a resistive component (Chang: RPb1) is connected between the one of the plural inspection pads that is formed in the central portion (Chang: 130C1 in the center region CR) and one of the adjacent inspection pads (Chang: 130E1).
Chang discloses that a semiconductor device as taught provides an efficient method of testing the reliability of the semiconductor device [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide an efficient method of testing the reliability as disclosed by Chang [0003].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights