Prosecution Insights
Last updated: July 17, 2026
Application No. 18/343,653

ARRAY SUBSTRATES, DISPLAY PANELS, AND METHOD FOR MANUFACTURING ARRAY SUBSTRATES

Non-Final OA §103§112
Filed
Jun 28, 2023
Priority
Feb 23, 2023 — CN 202310168253.9 +1 more
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Guangzhou China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
3 (Non-Final)
60%
Grant Probability
Moderate
3-4
OA Rounds
9m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
422 granted / 701 resolved
-7.8% vs TC avg
Strong +21% interview lift
Without
With
+21.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
48 currently pending
Career history
769
Total Applications
across all art units

Statute-Specific Performance

§103
89.4%
+49.4% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 701 resolved cases

Office Action

§103 §112
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 7-8, 10-11 and 17-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the specification for the claimed limitation of “the size of the lower-end of the third trapezoidal structure is equal to the size of the upper-end of the second trapezoidal structure”, as recited in claims 1 and 11. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 9-11, 19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (8,273,657) in view of Ota (2019/0137832) or Philipp (2011/0279398).Regarding claims 1 and 11, Harada et al. teach in figure 17C and related text an array substrate comprising: a base substrate 201/208/203 (see figure 2), which comprises a semiconductor chip 203; and a protection layer 208 and 11/22 disposed on the base substrate and covering the base substrate, the protection layer having one or more through-holes 14 (see figure 14F) for discharging moisture, and the one or more through-holes being disposed close to the semiconductor chip, wherein the protection layer comprises a second passivation layer 22, a film (another 22), and a first passivation layer (still another 22) stacked sequentially on the base substrate, each of the one or more through-holes comprises a first via hole (part of 14) formed in the second passivation layer, a second through-hole (another part of 14) formed in the polymer film, and a third through-hole (still another part of 14) formed in the first passivation layer, the first via hole does not extend through the second passivation layer (chosen as such), and the first via hole, the second through-hole, and the third through-hole are in communication with each other and in a cross-sectional view of the array substrate, in a direction toward the base substrate, the first via hole, the second through-hole, and the third through-hole respectively form a first trapezoidal structure, a second trapezoidal structure, and a third trapezoidal structure, wherein a size of an upper-end of each of the first trapezoidal structure, the second trapezoidal structure, and the third trapezoidal structure away from the base substrate is larger than a size of a lower-end of each of the first trapezoidal structure, the second trapezoidal structure, and the third trapezoidal structure close to the base substrate, and Harada et al. do not teach that the base substrate comprises a thin film transistor layer having a channel region, and do not explicitly state that the size of the lower-end of the third trapezoidal structure is equal to the size of the upper-end of the second trapezoidal structure. Ota teaches in figure 3 and related text a display panel comprising an array substrate comprising: a base substrate, which comprises a thin film transistor layer TFT having a channel region 15. Ota furth teaches in figure 3 and related text that the protection layer comprises a second passivation layer 17, a polymer film 18, and a first passivation layer 21 stacked sequentially on the base substrate. Harada et al. and Ota are analogous art because they are directed to through-holes and one of ordinary skill in the art would have had a reasonable expectation of success to modify Harada et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the base substrate comprises a thin film transistor layer TFT having a channel region, and wherein the film comprises a polymer material, such that the protection layer comprises a second passivation layer, a film, and a first passivation layer stacked sequentially on the base substrate, as taught by Ota, in Harada et al.’s device, in order to enhance the capabilities of the device, and in order to adjust and optimize the device characteristics, respectively. Regarding the claimed limitations of “each of the one or more through-holes comprises a first via hole formed in the second passivation layer, a second through-hole formed in the polymer film, and a third through-hole formed in the first passivation layer”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. The formation of a through-hole, as depicted in figure 4 of the present application, by forming first, second and third through-holes does not produce a structure which is different from a structure which is formed by forming only a through hole in one etching steps. Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear. In the alternative, Philipp teaches in related text (see e.g. claim 22) that the passivation layers can comprise polymer. Harada et al. and Philipp are analogous art because they are directed to passivation layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Harada et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the base substrate comprises a thin film transistor layer TFT having a channel region, and to form the passivation layers in Harada et al.’s device of the same material used by Philipp, such that the protection layer comprises a second passivation layer, a film, and a first passivation layer, in order to provide better protection to the structure. Regarding claim 10, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of each of the one or more through-holes in a horizontal direction and a height of each of the one or more through-holes in a vertical direction are greater than or equal to 7 microns, in prior art’s device in order to adjust the device characteristics based on moisture dissipation. Regarding claim 19, Ota, and thus prior art’s device, teaches in figure 3 and related text a counter substrate 12 and a liquid crystal layer LC, wherein the counter substrate 12 is disposed opposite to and spaced from the array substrate (the top part of element AR), and the liquid crystal layer is disposed between the counter substrate and the array substrate. Regarding claim 21, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the polymer film is made fromsoluble polyfluoroalkoxy, and the first passivation layer and the second passivation layer are made from a moisture-resistant insulating material, in prior art’s device in order to adjust the device characteristics based on moisture dissipation. Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (8,273,657), Ota (2019/0137832) and Philipp (2011/0279398), as applied to the claims above, and further in view of Su et al. (10,439,163). Regarding claims 7 and 17, prior art teaches substantially the entire claimed structure, as recited in claim 1, except wherein each of the one or more through-holes is filled with a water-absorbing material configured to prevent external moisture from entering the array substrate. Su et al. teach in figure 2a and related text that the material of the filling layer 31 can be either resin or water-absorbing material. Harada et al., Su et al., Ota and Philipp are analogous art because they are directed to resin layers and one of ordinary skill in the art would have had a reasonable expectation of success to modify Harada et al. et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a water-absorbing material, as taught by Su et al., to fill the first through-hole in prior art’s device, in order to prevent further moisture in the device. Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al. (8,273,657), Ota (2019/0137832) and Philipp (2011/0279398), and further in view of Tsujimura et al. (6,815,270). Regarding claims 8 and 18, prior art teaches substantially the entire claimed structure, as recited in claim 1, except having the one or more through-holes comprises a plurality of through-holes disposed close to the channel region. Tsujimura et al. teach in figure 3 and related text one or more through-holes comprises a plurality of through-holes 33 disposed close to the channel region. Harada et al., Tsujimura et al., Philipp and Ota are analogous art because they are directed to through-holes and one of ordinary skill in the art would have had a reasonable expectation of success to modify Harada et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the one or more through-holes comprises a plurality of through-holes disposed close to the channel region, as taught by Tsujimura et al., in prior art’s device in order to improve the moisture dissipation capabilities of the device. Response to Arguments Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 7/6/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Jun 28, 2023
Application Filed
Oct 06, 2025
Non-Final Rejection mailed — §103, §112
Dec 15, 2025
Response Filed
Dec 31, 2025
Final Rejection mailed — §103, §112
Mar 27, 2026
Request for Continued Examination
Apr 02, 2026
Response after Non-Final Action
Jul 08, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+21.1%)
3y 9m (~9m remaining)
Median Time to Grant
High
PTA Risk
Based on 701 resolved cases by this examiner. Grant probability derived from career allowance rate.

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