DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicant's arguments filed 04/07/2026 have been fully considered but they are not persuasive. Regarding independent claims 1, 10, 13, and 18, the Applicant has explained on pages 8-10, 14-15, 19-20, and 25-26 that Lopez et al. (US 20240096771) herein referred to as Lopez, does not meet the limitations “a metallization structure over the semiconductor body; and a conductive terminal, the metallization structure including a top level having neighboring first and second top metal structures that extend in a plane of orthogonal first and second directions, the first top metal structure electrically coupled to the conductive terminal, the conductive terminal extending over a portion of the first top metal structure and away from the plane along a third direction that is orthogonal to the first and second directions, and the first top metal structure spaced apart from the second top metal structure in the plane by a spacing distance of 60 µm or more.” The Examiner respectfully disagrees.
Shown below is the Annotated Lopez Fig. 1A: metallization structure (110) over semiconductor body (102) and conductive terminal (104), the metallization structure (110) including a top level having neighboring first and second top metal structures that extend in a plane of orthogonal first direction (x direction) and second direction (y direction), the first top metal structure electrically coupled to the conductive terminal (104), the conductive terminal extending over a portion of the first top metal first top metal structure and away from the plane along a third direction that is orthogonal to the first and second directions. Extending away is by matter of perspective dependent on your frame of reference. Therefore, the 35 USC § 103 rejection of independent claims 1, 10, 13, and 18 is upheld.
PNG
media_image1.png
282
931
media_image1.png
Greyscale
Nonetheless, assuming the Applicants arguments are persuasive, the device (100) is a package. “[0016] FIGS. 1, 1A, and 1B illustrate a packaged electronic device 100 with a semiconductor die 102 flip chip attached to a silicon wafer based multilevel metallization structure 110.” Therefore, it is obvious if not inherent, that a bump or other conductive terminal, can be attached to the underside (114) of the device (100), so as to attach a motherboard for example, such that the limitations of claims 1, 10, 13, 18 and the respective dependent claims, are still met. See bottom annotated plane in the Lopez Fig. 1A shown above. Therefore, the 35 USC § 103 rejection of independent claims 1, 10, 13, and 18 is upheld.
As to the Applicants argument on pages 10-12,16-18, 21-24, and 27-28 regarding the limitation “the spacing between the first top metal structure and the second top metal structure of 60 µm or more”, the Examiner respectfully disagrees. Finding the optimal spacing of 60 µm involves only routine skill in the art. Spacing between neighboring structures is crucial to prevent electrical leakage and short circuits, manage heat dissipation, and avoid parasitic capacitance/inductance. Proper spacing ensures high performance, reduces interference, and allows for reliable manufacturing within a tiny area. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have the spacing between the first top metal structure and the second top metal structure of 60 μm or more, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. Nonetheless, May et al. (US 20240329333) teaches an optimal spacing between components. [0042] “At least some of RDL metallization features 282 are to electrically bridge together two or more IC dies, preferably with the finest metallization line: space feature pitch that can be directly patterned (e.g., <3 μm lines and spaces) as limited by the flatness of the starting substrate 210”. Thus, 35 USC § 103 rejection of independent claims 1, 10, 13, and 18 is upheld.
Regarding the amended claim 18, as explained on pages 28-31, the Examiner agrees that component (104) does not “extend through” component (114). However, component (106) forms a protective overcoat layer over the metallization structure (110). See Lopez [0016]. “The electronic device 100 includes a package structure 106 that encapsulates or otherwise encloses the semiconductor die 102 and portions of the multilevel metallization structure 110 to form a quad flat no-lead QFN shape.” The conductive terminal (104) is electrically coupled to the first top metal structure and extends through the protective overcoat layer (106) over a portion of the first top metal structure and away from the plane along a third direction that is orthogonal to the first and second directions. Extending “away” is by matter of perspective. (See Lopez annotated Fig. 1A) Thus, 35 USC § 103 rejection of independent claim 18 is upheld.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
Claim(s) 1-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lopez et al. (US 20240096771) herein referred to as Lopez. Figs. 1A or 13A in view of May et al. (US 20240329333), herein referred to as May.
Regarding claims 1, 10, and 13 Lopez discloses an electronic device, and a system, comprising: a circuit board ([0031] printed circuit board (PCB not shown) ) comprising:
a semiconductor die ([0003] semiconductor die 102) having: a semiconductor body (Annotated semiconductor body Fig. 1A/13A);
a metallization structure ([0003] metallization structure 110) over the semiconductor body (Annotated semiconductor body Fig. 1A/13A); and
a conductive terminal ([0025] conductive terminals of 104), the metallization structure (110) including a top level having neighboring first and second top metal structures ([0003] multilevel metallization structure 110) that extend in a plane of orthogonal first (x direction) and second directions (y directions) ([0016] See orthogonal directions in Fig. 1A),
the first top metal structure ([0017],[0034] first level along first side 113/1313, Fig 1A or Fig 13A) electrically coupled to the conductive terminal ([0016] “The conductive features 104 of the semiconductor die 102 are mechanically and electrically coupled to conductive metal pads of the multilevel metallization structure 110) ,
the conductive terminal ([0025] conductive terminals of 104) extending over a portion of the first top metal structure and away from the plane along a third direction (z direction) that is orthogonal to the first and second directions ([0022] …”the thickness along the third direction Z of the conductive features of the leads 112 in one example is sufficiently thick to accommodate desired lead side wall heights of the finished packaged electronic device 100…”), and
the first top metal structure ([0017],[0034] first level along first side 113/1313, Fig 1A or Fig 13A) spaced apart from the second top metal structure ([0017],[0034] level along the second side 111/1311, Fig. 1A or Fig. 13A) in the plane ([0017], [0034] “the illustrated example includes further levels between the first level and the final level, and other implementations can have any integer number intermediate levels between the first and final levels.”)
a package structure ([0016] package 100) that at least partially encloses the semiconductor die (102). (See Annotated Fig. 1A/13A)
PNG
media_image2.png
266
1035
media_image2.png
Greyscale
Lopez does not appear to expressly disclose “the first top metal structure spaced apart from the second top metal structure in the plane by a spacing distance of 60 µm or more” (obvious).
However, May et al. (US 20240329333) teaches an optimal spacing, also in the µm range, between meatal components. See [0042] “At least some of RDL metallization features 282 are to electrically bridge together two or more IC dies, preferably with the finest metallization line: space feature pitch that can be directly patterned (e.g., <3 μm lines and spaces) as limited by the flatness of the starting substrate 210”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the spacing in the Lopez device as in the May device by making the spacing between the first top metal structure and the second top metal structure of the Lopez device, 60 µm or more. Optimizing the separation between metal layers is critical for ensuring signal integrity, maintaining performance, and enabling multi-layer routing, so as to use an industrially tested and accepted device.
Furthermore, the Applicant has not shown that a spacing of 60 µm between the first and second top metal structure is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the spacing between the first and second top metal structure, so as to minimize parasitic capacitance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
Regarding claims 2 and 14, The Lopez/May combination discloses the electronic device of claim 1 and the system of claim 13, respectively as discussed above and further discloses wherein,
the second top metal structure ([0017], [0034] level along the second side 111/1311) is the nearest top metal structure to the first top metal structure ([0017], [0034] first level along first side 113/1313 ) in the top level of the metallization structure (110).
Regarding claims 3, 15, and 19 The Lopez/May combination discloses the electronic device of claim 1, the system of claim 13, and the method of claim 18, wherein respectively as discussed above
Lopez does not appear to expressly disclose “the spacing distance is 80 µm or more” (obvious).
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the spacing between the first top metal structure and the second top metal structure of the Lopez device, 80 µm or more. Optimizing the separation between metal layers is critical for ensuring signal integrity, maintaining performance, and enabling multi-layer routing so as to use an industrially tested and accepted device.
Furthermore, the Applicant has not shown that a spacing of 80 µm between the first and second top metal structure is novel and would not have been found through routine experimentation. Nonetheless, it would have been obvious to one having ordinary skill in the art at the time the invention was made to optimize the spacing between the first and second top metal structure, so as to be able to minimize parasitic capacitance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.
Regarding claims 4, 16, and 20, The Lopez/May combination discloses the electronic device of claim 3 and the system of claim 15, respectively as discussed above and further discloses wherein:
the first top metal structure ([0017], [0034] first level along first side 113/1313 ) overlaps all lateral edges of the conductive terminal (104) by a non-zero overlap distance (Fig. 1A).
Regarding claim 5 and 21, The Lopez/May combination discloses the electronic device of claim 4, and the method of claim 20, as discussed above and further discloses wherein:
the first top metal structure has a thickness along the third direction ([0016] “The electronic device 100 is shown in an example three-dimensional space including a first direction (e.g., X in the illustrated orientation), an orthogonal second direction (e.g., Y), and a third direction (e.g., Z) that is orthogonal to the first and second directions X and Y.”); and
the overlap distance is greater than the thickness (overlap x- direction greater than thickness z-direction, Fig. 1A).
Regarding claim 6, The Lopez/May combination discloses the electronic device of claim 1, as discussed above and further discloses wherein:
the first top metal structure (side 1313) overlaps all lateral edges of the conductive terminal by a non-zero overlap distance (overlap x- direction greater than thickness z-direction, See Annotated Fig. 1A).
Regarding claims 7 and 11, The Lopez/May combination discloses the electronic device of claim 6, and the electronic device of claim 10 as discussed above and further discloses wherein:
the first top metal structure has a thickness along the third direction; and
the overlap distance is greater than the thickness (overlap x- direction greater than thickness z-direction, See Annotated Fig. 1A) ([0016] “The electronic device 100 is shown in an example three-dimensional space including a first direction (e.g., X in the illustrated orientation), an orthogonal second direction (e.g., Y), and a third direction (e.g., Z) that is orthogonal to the first and second directions X and Y.”).
Regarding claims 8, 12 and 17 The Lopez/May combination discloses the electronic device of claim 1, the electronic device of claim 10, and the system of claim 13 respectively as discussed above and further discloses wherein:
the conductive terminal is soldered ([0004] conductive features of the semiconductor die soldered to respective conductive metal pads of the multilevel metallization structure, forming a package structure that encloses the semiconductor die and a portion of the multilevel metallization structure) to a conductive feature of a package substrate ([ 0016] conductive feature soldered to package); and
the package structure ([0016], [0033] Fig. 1A package structure 106/1306) at least partially encloses the package substrate ([0035] Fig. 13A, substrate1320).
Regarding claim 9, The Lopez/May combination discloses the electronic device of claim 1, as discussed above and further discloses wherein
the spacing distance between is controlled at least partially according to a die location in a given packaged electronic device design ([0020] “The wafer-based multilevel metallization structure 110 allows support for reduced semiconductor die terminal spacing and increased die terminal count as well as improved routing capabilities compared with conventional interconnect substrates or packages, and the multilevel metallization structure 110 facilitates fine lines and spacing to allow routing of leads and interconnect substrate lines to the semiconductor die bumps or terminals 104.”).
Regarding claim 18, The Lopez/May combination discloses a method of fabricating an electronic device, the method comprising:
forming a metallization structure ([0003] metallization structure 110) over a semiconductor body ([0003] metallization structure 110), including forming a top level having neighboring first and second top metal structures ([0017],[0034] level along the second side 111/1311, Fig. 1A or Fig. 13A) in a plane of orthogonal first and second directions,
the first top metal structure ([0017],[0034] first level along first side 113/1313, Fig 1A or Fig 13A) spaced apart from the second top metal structure ([0017],[0034] level along the second side 111/1311, Fig. 1A or Fig. 13A) in the plane by a spacing distance of 60 µm or more (obvious) ;
forming a protective overcoat layer (encapsulation 106 [0016] Fig. 13A, “The electronic device 100 includes a package structure 106 that encapsulates or otherwise encloses the semiconductor die 102 and portions of the multilevel metallization structure 110 to form a quad flat no-lead QFN shape.”) over the metallization structure ([0003] metallization structure 110); and
forming a conductive terminal ([0025] conductive terminals of 104) electrically coupled to the conductive terminal ([0025] conductive terminals of 104) and extending through the protective overcoat layer (encapsulation 106) over a portion of the first top metal structure ([0017],[0034] first level along first side 113/1313, Fig 1A or Fig 13A) and away from the plane along a third direction that is orthogonal to the first and second directions.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
Prosecution Insights