Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The formal drawings filed on 6/29/2023 have been approved by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “ METHOD OF FABRICATING MUTIPLE SEMICONDUCTOR PACKAGE ASSEMBLIES ON A LEAD FRAME ”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9-11, 16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Hor et al. (EP 3786857).
With respect to Claims 1 and 2, Hor teaches providing a metallic lead frame fabricated from a metal sheet 206 having a first longitudinal dimension and a second longitudinal dimension. The lead frame composed of a plurality of die paddles 218 forming at least one die paddle column oriented in the first longitudinal dimension and a plurality of terminals (i.e. at the leads end 202) forming at least one terminal column oriented in the first longitudinal dimension. Attaching a plurality of semiconductor die components 216 to each of the plurality of die paddles 218 by adhesive bonding. Connecting the semiconductor die components with the plurality of terminals. Encapsulating 212 the plurality of semiconductor die components 216 by covering at least one pair of the at least one die paddle column and the at least one terminal column with the terminal parts at least partly exposed with dielectric material 212. Thereby forming a single encapsulation block 212 after cutting the device into a plurality of packages) for each pair consisting of the at least one die paddle column and the at least one terminal column. Singulating semiconductor packages by cutting the at least one single encapsulation block in the second longitudinal direction into at least two single semiconductor packages. The cutting line 224 lays at least between the at least two semiconductor die components. Trimming (i.e. creating holes 202) the exposed terminal parts (see paragraphs 20-34; 2a, 2b, 3,and 5b-5e).
With respect to Claims 3 and 10, Hor teaches adhesive bonding, eutectic bonding and solder bonding (see paragraphs 11 and 12).
With respect to Claims 4, 11, and 16, Hor teaches any one of steps a) to f) is
preceded with a step selected from the group consisting of: a surface treatment, a coating with tin, a plating, and a galvanizing step (see paragraphs 12 and 15).
With respect to Claim 9, Hor teaches step f is performed by a method
selected from the group consisting of laser cutting, mechanic sawing, and rotating blade sawing (see paragraph 32).
With respect to Claim 20, Hor teaches wherein at least one side wall of the semiconductor package orientated parallel to the second longitudinal dimension has substantially flat surface that is perpendicular to a bottom or a top side of the semiconductor package (see Figs. 2a and 5e).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-8 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hor et al. (EP 3736857) as applied to claim 1 above, and further in view of Yoshikawa et al. (US 2011/0080928) and Jin et al. (US 11,450,534).
With respect to Claims 6, 7, 13, and 14, Hor discloses the claimed invention except for using injection molding of thermoplastic polymer.
However, Yoshikawa discloses using injection molding of thermoplastic polymer or thermos-curable resin for protecting a semiconductor device (see paragraphs 54, 58, and 90). Thus, Hor and Yoshikawa have substantially the same environment of a chip encapsulated and mounted to a lead frame. Therefore, one skilled in the art before the effective filing date of the claimed invention to substitute am injection molding of thermoplastic polymer for the process of Hor, since the injection molding of the polymer would facilitate in protecting the semiconductor device from outside contaminant as by Yoshikawa.
With respect to Claims 8 and 15, Hor-Yoshikawa discloses the claimed invention except for using a ceramic material for encapsulating a semiconductor.
However, Jin discloses using a ceramic material for encapsulating a semiconductor (see col. 5 lines 55-60). Thus, Hor-Yoshikawa and Jin have substantially the same environment of a chip encapsulated and mounted to a lead frame. Therefore, one skilled in the art before the effective filing date of the claimed invention to substitute a ceramic material for the material of Hor-Yoshikawa, since the ceramic would facilitate in protecting the semiconductor device from outside contaminant as by Yoshikawa.
Allowable Subject Matter
10. Claims 5, 12, and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record does not teach or suggest the combination of at least two single semiconductor packages are separated by less than 3 mm viewed in the second longitudinal direction in claims 5 and 12.
At least two single semiconductor packages are separated by a range of 0.03-0.35 mm in claim 17.
At least two single semiconductor packages are separated by a range of range of 0.12-0.18 mm in claim 18.
At least two single semiconductor packages are separated by 0.15 mm in claim 19.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
11. Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number
for the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/March 4, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897