DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/16/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 5-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elsherbini et al. (US Patent Application Publication No. 2020/0273839) (“Elsherbini”).
Regarding Clam 1, Elsherbini teaches a microelectronic assembly (see Figure 1), comprising: a first layer of a substrate (Figure 1, item 102) including a first material having a cavity (Figure 1, item 108) and a conductive pad (Figure 1, item 146) at a bottom of the cavity; a first microelectronic component (Figure 1, item 114-1) having a first surface and an opposing second surface, the first microelectronic component is at least partially nested in the cavity (see Figure 1, note 114-1 is in 108) and the first surface of the first microelectronic component is electrically coupled to the conductive pad at the bottom of the cavity (see Figure 1, note 114-1 is connected to 146); a second layer of the substrate (Figure 1, item 127) on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component (see Figure 1, note location of item 127), wherein the second material includes an organic dielectric material that is a photoimageable dielectric (PID) or a non-photoimageable dielectric (non-PID) (¶0048); and a second microelectronic component (Figure 1, item 114-2) electrically coupled to the second surface of the first microelectronic component by conductive pathways (Figure 1, item 130-1)through the second layer of the substrate.
Regarding Claim 3, Elsherbini further teaches the substrate includes a third surface and an opposing fourth surface (see Figure 1, top and bottom of item 114-2), wherein the second layer of the substrate is at the fourth surface of the substrate (see Figure 1, note 127 at the top of item 114-2), and the microelectronic assembly further comprising: the second material at the third surface of the substrate (see Figure 1, note 127 at the bottom of item 114-2).
Regarding Claim 5, Elsherbini further teaches a metal ring at a perimeter of the bottom of the cavity (see Figure 15).
Regarding Claim 6, Elsherbini further teaches the substrate further comprises: a glass layer (Figure 22, item 136, ¶0095); and a via (Figure 22, item 134), through the glass layer, electrically coupled to the conductive pad at the bottom of the cavity (see Figure 22, note connection of vias to conductive pads at the bottom of the cavity).
Regarding Claim 7, Elsherbini further teaches the substrate further includes conductive pathways (see Figure 1, items 146), and wherein the second microelectronic component is electrically coupled to the conductive pathways in the substrate (see Figure 1, note connection of 114-2 to 146).
Regarding Claim 8, Elsherbini further teaches the substrate includes a third surface and an opposing fourth surface (see Figure 1, top and bottom of item 131), and the microelectronic assembly further comprising: a package substrate electrically coupled to the third surface of the substrate (see Figure 1, note connection of 133 to 131).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini.
Regarding Claim 9, Elsherbini teaches a microelectronic assembly (Figure 1), comprising: a substrate (Figure 1, item 102) including a conductive pathway (Figure 1, items 146+) through a dielectric material (Figure 1, item 127) and having a first hybrid bonding region electrically coupled to the conductive pathway, wherein the first hybrid bonding region includes first metal contacts (Figure 1, item 146 at the bottom of the recess) and an organic dielectric material (Figure 1, item 127) between adjacent ones of the first metal contacts; and a microelectronic component (Figure 1, item 114-1) surrounded by the dielectric material (Figure 1, item 127) of the substrate and having a second hybrid bonding region, wherein the second hybrid bonding region includes second metal contacts and the organic dielectric material between adjacent ones of the second metal contacts (see Figure 1, note 130-1), wherein the microelectronic component is coupled to the conductive pathway of the substrate by interconnects (see Figure 1), and wherein the interconnects include individual first metal contacts in the first hybrid bonding region coupled to respective individual second metal contacts in the second hybrid bonding region (see Figure 1,note connection between layers in individual chips).
Elsherbini does not specifically teach the interconnects having a pitch of between 2 microns and 70 microns between adjacent interconnects. However, Elsherbini does teach varying the amount of pitch between different interconnects (¶0055). It would have been obvious to one of ordinary skill in the art at the time the invention was made to optimize the pitch between the interconnects, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 10, Elsherbini further teaches wherein the organic dielectric material is a photoimageable dielectric (PID) or a non-photoimageable dielectric (non-PID) (¶0048).
Regarding Claim 11, Elsherbini further teaches a material of the first metal contacts and the second metal contacts includes copper (¶0094).
Regarding Claim 12, Elsherbini further teaches a material of the first metal contacts and the second metal contacts includes tin (¶0051).
Regarding Claim 13, Elsherbini further teaches a material of the first metal contacts includes copper and a material of the second metal contacts includes tin (¶0051).
Regarding Claim 14, Elsherbini further teaches a material of the first metal contacts includes tin and a material of the second metal contacts includes copper (¶0051).
Regarding Claim 15, Elsherbini further teaches the first hybrid bonding region further includes an adhesive material between adjacent ones of the first metal contacts (see Figure 1, note location of 127).
Regarding Claim 16, Elsherbini further teaches the second hybrid bonding region further includes an adhesive material between adjacent ones of the second metal contacts (see Figure 1, note location of 127).
Regarding Claim 17, Elsherbini teaches a microelectronic assembly (see Figure 1), comprising: a substrate including a first conductive pathway (Figure 1, item 146 on right side) and a second conductive pathway (Figure 1, item 146 on left side) through a dielectric material, a first hybrid bonding region (Figure 1, item 150-3) electrically coupled to the first conductive pathway, and a second hybrid bonding region (Figure 1, item 150-2) electrically coupled to the second conductive pathway, wherein the first hybrid bonding region includes first metal contacts (Figure 1, item 150-3) and an organic dielectric material (Figure 1, item 127) between adjacent ones of the first metal contacts, and the second hybrid bonding region includes second metal contacts (Figure 1, item 150-2) and the organic dielectric material (Figure 1, item 127) between adjacent ones of the second metal contacts; a first microelectronic component (Figure 1, item 114-1) surrounded by the dielectric material of the substrate and having a third hybrid bonding region (Figure 1, item 150-1), wherein the third hybrid bonding region includes third metal contacts (Figure 1, item 150-1) and the organic dielectric material (Figure 1, item 127) between adjacent ones of the third metal contacts, wherein the first microelectronic component is coupled to the first conductive pathway of the substrate (see Figure 1) by first interconnects, and wherein the first interconnects include individual first metal contacts in the first hybrid bonding region coupled to respective individual third metal contacts in the third hybrid bonding region (see Figure 1); and a second microelectronic component (Figure 1, item 114-2) having a fourth hybrid bonding region (Figure 1, item 130-1), wherein the fourth hybrid bonding region includes fourth metal contacts (Figure 1, item 130-1) and the organic dielectric material (Figure 1, item 127) between adjacent ones of the fourth metal contacts, wherein the second microelectronic component is coupled to the second conductive pathway of the substrate (see Figure 1) by second interconnects, and wherein the second interconnects include individual second metal contacts in the second hybrid bonding region coupled to respective individual fourth metal contacts in the fourth hybrid bonding region (see Figure 1).
Elsherbini does not specifically teach the interconnects having a pitch of between 2 microns and 70 microns between adjacent interconnects. However, Elsherbini does teach varying the amount of pitch between different interconnects (¶0055). It would have been obvious to one of ordinary skill in the art at the time the invention was made to optimize the pitch between the interconnects, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 18, Elsherbini further teaches wherein the organic dielectric material is a photoimageable dielectric (PID) or a non-photoimageable dielectric (non-PID) (¶0048).
Regarding Claim 19, Elsherbini further teaches a material of the first metal contacts, the second metal contacts, the third metal contacts, and the fourth metal contacts includes copper (¶0094).
Regarding Claim 20, Elsherbini further teaches a material of the first metal contacts, the second metal contacts, the third metal contacts, and the fourth metal contacts includes tin (¶0051).
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Elsherbini as applied to Claim 1 above.
Regarding Claim 2, Elsherbini teaches Claim 1 as indicated above. Elsherbini does not specifically teach the second material includes a non-PID, and the microelectronic assembly further comprising: a third layer of the substrate on the second layer of the substrate, the third layer including a third material, wherein the third material includes a PID. However, Elsherbini teaches using both PID and non-PID materials as insulating layers in the device (¶0036). It would have been obvious to a person having ordinary skill in the art at the time of effective filing to use the known materials described in Elsherbini as functional dielectric layers because it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960). MPEP § 2144.07.
Regarding Claim 4, Elsherbini further teaches the substrate includes a third surface and an opposing fourth surface (see top and bottom of device in Figure 1), wherein the third layer of the substrate is at the fourth surface of the substrate (see Figure 1), and the microelectronic assembly further comprising: the third material at the third surface of the substrate (see Figure 1).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Elsherbini et al. (US Patent Application Publication No. 2019/0385977)
Hsieh (US Patent No. 12,476,177)
Hu et al. (US Patent No. 11,239,205)
Liff et al. (US Patent No. 11,049,791)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK W TORNOW whose telephone number is (571)270-7534. The examiner can normally be reached M-Th 6:30-4:30 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARK W. TORNOW
Primary Examiner
Art Unit 2891
/MARK W TORNOW/Primary Examiner, Art Unit 2891
Prosecution Insights