DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed November 10, 2025, with respect to the rejection(s) of claim(s) 1,5,7,8,12 under 35USC102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Tang et al. (US 20210183794 A1; Tang).
Upon further review of claims 2 and 9 it is determined the Tang in fact discloses, “wherein the 3D IPD structure comprises one or more of, a 3D capacitive IPD structure, and a 3D resistive IPD structure.” Examiner interpreted the limitation to include a plurality of 3d devices rather than the claimed one or more. US-10433425-B1 discloses a plurality of 3DIPD structures in a molding layer.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,5,7,8,12 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Tang et al. (US 20210183794 A1; Tang).
8/10/22
Regarding claim 1, Tang discloses a wafer-level packaging structure, comprising a molding layer (Fig. 2A, 242; ¶71), and a 3D IPD (Integrated Passive Device) structure (Fig. 2A, I-1; ¶64) fabricated in the molding layer, wherein the molding layer includes a first surface (top or bottom) and a second surface (bottom or top) opposite to the first surface, wherein the 3D IPD structure comprises one or more of a 3D inductive IPD structure (¶64), a 3D capacitive IPD structure, and a 3D resistive IPD structure.
Regarding claim 5, Tang discloses the wafer-level packaging structure according to claim 1,further comprising a first rewiring layer (Fig. 2A, 244; ¶64) formed on the first surface (bottom) of the molding layer and a second rewiring layer (Fig. 2A, 144; ¶64) formed on the second surface (top) of the molding layer, wherein the first rewiring layer includes a first dielectric layer (Fig. 2A,250; ¶64) and a first wiring metal layer (Fig. 2A, S3/CL2/V2; ¶62) formed in the first dielectric layer, and wherein the second rewiring layer includes a second dielectric layer (Fig. 2A, 150; ¶64) and a second wiring metal layer (Fig. 2A, S1/CL1/V1; ¶67) formed in the second dielectric layer and connected to the 3D IPD structure. (Fig. 2A, I-1; ¶64)
Regarding claim 7, Tang discloses the wafer-level packaging structure according to claim 5, wherein the wafer-level packaging structure is an RE ASIC wafer-level packaging structure, and further comprises: an RE ASIC chip (Fig. 2A, 126; ¶97), formed on a surface of the second rewiring layer (Fig. 2A, 144; ¶64) and connected to the second wiring metal layer (Fig. 2A, S1/CL1/V1; ¶67); and solder balls (Fig. 2A, 264; ¶62), formed on a surface of the first rewiring layer (Fig. 2A, 244; ¶64) surface and connected to the first wiring metal layer. (Fig. 2A, S3/CL2/V2; ¶62)
Regarding claim 8, Tang discloses a method for preparing a wafer-level packaging structure , including: preparing a molding layer (Fig. 2A, 242; ¶64); and forming a 3D IPD structure (Integrated Passive Device) (Fig. 2A, I-1; ¶64) inside the molding layer, ,wherein the 3D IPD structure comprises one or more of a 3D inductive IPD structure (¶64), a 3D capacitive IPD structure, and a 3D resistive IPD structure..
Regarding claim 12, Tang discloses the method according to claim 8, further comprising: forming a first rewiring layer (Fig. 2A, 244; ¶64) on a first surface of the molding layer and a second rewiring layer (Fig. 2A, 144; ¶64) on a second surface of the molding layer, (Fig. 2A, 242; ¶64) wherein the first rewiring layer includes a first dielectric layer (Fig. 2A, 250; ¶64) and a first wiring metal layer, (Fig. 2A, S3/CL2/V2; ¶62) wherein the second rewiring layer (Fig. 2A, 144; ¶64) includes a second dielectric layer (Fig. 2A, 150; ¶64) and a second wiring metal layer (Fig. 2A, S1/CL1/V1; ¶67) formed in the second dielectric layer and connected to the 3D IPD structure. (Fig. 2A, I-1; ¶64)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 20210183794 A1; Tang) in view of Liu et al. (US 10433425 B1; Liu).
Regarding claim 4, Tang discloses the wafer-level packaging structure according to claim 1, but is silent on wherein the 3D capacitive IPD structure comprises at least one pair of metal layers formed in the molding layer, wherein the at least one pair of metal layers are spaced apart and parallel to each other, wherein said one pair of metal layers are perpendicular to one of the first and second surfaces of the molding layer.
Liu discloses a 3D capacitive device structure (Fig. 6, 610b; column 7 lines 58-67) that comprises at least one pair of metal layers (Fig. 6, 615ab; column 7 lines 58-67) formed in the molding layer (Fig. 6, 605; column 7 lines 58-67), wherein the at least one pair of metal layers are spaced apart and parallel to each other, wherein said one pair of metal layers are perpendicular to one of the first and second surfaces of the molding layer.
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to combine a 3d capacitor with a 3d inductor structure for forming a high quality mobile radio frequency chip.
Claim(s) 6,13,14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US 20210183794 A1; Tang) in view of Lai et al. (US 20230137691 A1; Lai).
Regarding claim 6, Tang discloses the wafer-level packaging structure according to claim 5, wherein the wafer-level packaging structure is a fan-out wafer-level packaging structure, and further comprises: metal connection pillars (Fig. 2A, 216; ¶64), formed in the molding layer (Fig. 2A, 242; ¶64) and connected to the first wiring metal layer (Fig. 2A, S3/CL2/V2; ¶62)
and the second wiring metal layer (Fig. 2A, S1/CL1/V1; ¶67); but is silent on chips soldered to the second rewiring layer and connected to the second wiring metal layer; and solder balls, formed on a surface of the first rewiring layer and connected to the first wiring metal layer.
Tang discloses chips connected to the second wiring layer but is silent on using solder.
Lai discloses a package comprising an IPD structure (Fig. 1k, 54; ¶59) between two wiring layers, (Fig. 1k, 470/420; ¶61,37) and chips (Fig. 1k, 701-703; ¶66) connected to a second wiring layer by solder balls. (Fig. 1k, 490; ¶67)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the chips by the known method of solder balls for efficient alignment during the coupling process.
Regarding claim 13, Tang discloses the e method according to claim 12, further comprising: forming metal connection pillars (Fig. 2A, 216; ¶64) in the molding layer(Fig. 2A, 242; ¶64, wherein the metal connection pillars are connected to the first wiring metal layer (Fig. 2A, S3/CL2/V2; ¶62) and the second wiring metal layer; (Fig. 2A, S1/CL1/V1; ¶67)… and forming solder balls (Fig. 2A, 264; ¶62) on a surface of the first rewiring layer, (Fig. 2A, 244; ¶64) wherein the solder balls are connected to the first wiring metal layer (Fig. 2A, S3/CL2/V2; ¶62), thereby forming a fan-out wafer-level packaging structure.
Tang is silent on soldering chips to the second rewiring layer, wherein the chips are connected to the second wiring metal layer;
Tang discloses chips connected to the second wiring layer but is silent on using solder.
Lai discloses a package comprising an IPD structure (Fig. 1k, 54; ¶59) between two wiring layers, (Fig. 1k, 470/420; ¶61,37) and chips (Fig. 1k, 701-703; ¶66) connected to a second wiring layer by solder balls. (Fig. 1k, 490; ¶67)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the chips by the known method of solder balls for efficient alignment during the coupling process.
Regarding claim 14, Tang discloses the method according to claim 12, further comprising:, wherein the RF ASIC chip (Fig. 2A, 126; ¶33,97) is connected to the second wiring metal layer (Fig. 2A, S1/CL1/V1; ¶67); and forming a solder ball (Fig. 2A, 264; ¶62) on a surface of the first rewiring layer (Fig. 2A, 244; ¶64) , wherein the solder balls are connected to the first wiring metal layer (Fig. 2A, S3/CL2/V2; ¶62), thereby forming an RF ASIC wafer- level packaging structure.
Tang is silent on soldering an RF ASIC chip to the second rewiring layer
Tang discloses RF ASIC chips connected to the second wiring layer but is silent on using solder.
Lai discloses a package comprising an IPD structure (Fig. 1k, 54; ¶59) between two wiring layers, (Fig. 1k, 470/420; ¶61,37) and chips (Fig. 1k, 701-703; ¶66) connected to a second wiring layer by solder balls. (Fig. 1k, 490; ¶67)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to connect the chips by the known method of solder balls for efficient alignment during the coupling process.
Allowable Subject Matter
Claims 3 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The art of record discloses IPD comprising capacitors, inductors, and resistor. The art discloses IPDs combining 3D capacitors with 3D inductors. The art appears to be silent on combining 3D resistors with 3D capacitors and 3D inductors. 3D resistors are distinct from typical resistors, which can be as simple as film of resistive material.
Regarding claim 3, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " first metal solder pads, formed inside the molding layer and extending inwards from the first surface of the molding layer”, as recited in Claim 3, with the remaining features.
Regarding claim 10, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " forming first metal solder pads on a surface of the release layer, forming metal pillars over ends of the first metal solder pads: forming a molding layer over the release layer to cover the metal pillars and the first metal solder pads, and thinning the molding layer and the metal”, as recited in Claim 10, with the remaining features.
Regarding claim 11, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " forming a molding layer on a surface of the release layer; etching the molding layer to form at least one pair of parallel openings exposing the release layer, filling the openings with metal materials to form at least one pair of metal layers are spaced apart and to each other”, as recited in Claim 11, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
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/LAWRENCE C TYNES JR./ Examiner, Art Unit 2899