DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 29, 2023 is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-13) in the reply filed on November 6, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 10, and 12-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2021/0233929). Claim 1, Lee discloses (Fig. 2) a semiconductor structure, comprising: an alternating stack (300, mold structure, Para [0032]) of insulating layers (304, insulating layer, Para [0038]) and electrically conductive layers (302, second semiconductor layer is conductively doped, Para [0039]); a memory opening (opening where CS is formed, hereinafter “opening”) vertically extending through the alternating stack (opening extends through 300); and a memory opening fill structure (CS, channel structure, Para [0041]) located in the memory opening (CS is located in opening) and comprising a memory film (404/406/408, second blocking insulation film/charge storage film/tunnel insulating film, Para [0061] –[0062], hereinafter “mem”), a vertical semiconductor channel (412, channel semiconductor, Para [0042]), and an aluminum nitride layer (400, anti-oxidation film may include AlN, Para [0058]) that laterally surrounds the memory film (400 laterally surrounds mem). Claim 2, Lee discloses (Fig. 2) the semiconductor structure of Claim 1, wherein the memory opening fill structure (CS) further comprises an aluminum oxide layer (402, first blocking insulation film may be AlO, Para [0059]) located between the aluminum nitride layer and the memory film (402 is between 400 and mem). Claim 10, Lee discloses (Fig. 2) the semiconductor structure of Claim 2, wherein: the aluminum nitride layer (400) is in contact with sidewalls of a plurality of the insulating layers (400 is in contact with a plurality of inner sidewalls of 304); and the aluminum nitride layer is in contact with sidewalls of a plurality of the electrically conductive layers (400 is in contact with a plurality of inner sidewalls of 302). Claim 12, Lee discloses (Fig. 2) the semiconductor structure of Claim 2, wherein the aluminum oxide layer (402) contacts an inner sidewall of the aluminum nitride layer (402 contacts inner sidewall of 400) and contacts an outer sidewall of the memory film (402 contacts outer sidewall of mem). Claim 13, Lee discloses (Fig. 2) the semiconductor structure of Claim 12, wherein the memory film (mem) comprises a vertical stack of memory elements (406 are considered vertical stack of memory elements) located at levels of the electrically conductive layers (406 are located at levels of 302), and a tunneling dielectric layer (408) in contact with the vertical semiconductor channel (408 is in contact with 412).
Allowable Subject Matter
Claims 3-9 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Lee (US 2021/0233929), Lee (US 2024/0096415), Kim (US 2025/0254880), Kim (US 2025/0316597), Choi (US 2025/0275145), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 3 (from which claims 4-7 depend), wherein each of the electrically conductive layers comprises a metallic nitride barrier layer that is in contact with a respective cylindrical segment of an outer sidewall of the aluminum nitride layer.
Regarding Claim 8 (from which claim 9 depends), wherein each of the electrically conductive layers comprises: a boron containing nucleation layer that is in contact with a respective cylindrical segment of an outer sidewall of the aluminum nitride layer
Regarding Claim 11, wherein the aluminum oxide layer comprises a nitrogen doped aluminum oxide layer in which an atomic concentration of nitrogen atoms decreases with increasing distance from the aluminum nitride layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2024/0096415) discloses (Fig. 5) a charge blocking layer 321 comprising AlN surrounding memory layer 322. Lee does not qualify as prior art.
Kim (US 2025/0254880) discloses (Fig. 3) a charge blocking layer 128 comprises aluminum nitride. Kim does not qualify as prior art.
Kim (US 2025/0316597) discloses (Fig. 14) a first charge blocking layer 1280 may be aluminum nitride and is between a charge trap layer 1260 and electrode 1310. Kim does not qualify as prior art.
Choi (US 2025/0275145) discloses (Fig. 2) an aluminum nitride layer CB1 between a charge storage 125 and a channel CH, but Choi does not qualify as prior art.
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/G.G.R/Examiner, Art Unit 2812