DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 10/30/2025, without traverse to prosecute the claims of Invention II, claims 9-20 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 7/20/2023, 10/25/2024, 11/25/2024, and 2/2/2026 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 107424919 A, given in IDS) in view of Wong (US 20210257475 A1, given in IDS).
Re Claim 9 Wang teaches a method of fabricating a transistor device, the method comprising:
providing a semiconductor substrate (1, page 4 par 5);
forming a first dielectric layer (8, page 6 par 4 “8 is Al2O3.”) on the semiconductor substrate (1);
forming a second dielectric layer (6, page 6 par 4 “6 is Si3N4,”) on the first dielectric layer (8);
forming a gate channel by:
performing a patterned dry etch (page 6 par 5 “dry etching the passivation layer 6 in the step (4) is as follows: using inductive coupling plasma ICP etching apparatus, plasma formed by sulphur hexafluoride SF6 gas dry etching passivation layer 6 Si3N4”) to form a first opening in the second dielectric layer (opening in 6, FIG. 6); and
performing a first wet etch (page 7 par 1 “wet etching barrier layer Al2O3.”) to form a second opening in the first dielectric layer (opening in 8, FIG. 7);
forming a gate structure (7, page 7 par 2) disposed at least partially in the gate channel and in contact with surfaces of the semiconductor substrate (7 is in mechanical contact with 1 since both are directly attached to layers 2 & 3) and the second dielectric layer (6, FIG. 3)
Wang does not teach forming dielectric spacer structures in the gate channel; and
the gate structure in contact with the dielectric spacer structures.
Wong teaches forming dielectric spacer structures (19a [0137] & 18a [0042]) in the gate channel (FIG. 4E); and
the gate structure (20) [0051] in contact with the dielectric spacer structures (FIG. 4F).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wong into the structure of Wang since Wong teaches a high electron mobility transistor.
The ordinary artisan would have been motivated to modify Wong in combination with Wang in the above manner for the motivation of ideally integrating the gate spacers into the transistor to achieve an optimal gate profile. [0003] states, “In the RF applications, the gate profile of a HEMT may affect the frequency characteristics and/or performance of the HEMT.”
Re Claim 10 Wang in view of Wong teaches the method of claim 9, wherein forming the dielectric spacer structures comprises:
forming a first layer (Wong, 19) over the semiconductor substrate (10) [0032] and in the gate channel (FIG. 4B);
forming a second layer (18) on the first layer (FIG. 4C); and
etching to remove portions of the first layer (19, FIG. 4E) [0145] and portions of the second layer (18, FIG. 4D) [0142].
Re Claim 11 Wang in view of Wong teaches the method of claim 10, wherein the first layer (Wong, 19) comprises oxide material [0137] and the second layer (18) comprises nitride material [0042].
Re Claim 12 Wang in view of Wong teaches the method of claim 10, wherein etching to remove portions of the first layer (Wong, 19) and portions of the second layer (18) comprises:
performing a dry etch [0143] to remove the portions of the second layer (18); and performing a second wet etch [0145] to remove the portions of the first layer (19).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 107424919 A, given in IDS) in view of Wong (US 20210257475 A1, given in IDS) and further in view of Li et al. (CN 112614777 A), Cheng et al. (US 20210118995 A1), and Lin et al. (DE 102022113066 A1).
Re Claim 13 Wang in view of Wong teaches the method of claim 10, wherein performing the patterned etches to remove portions of the first layer and portions of the second layer comprises:
performing a dry etch (Wong, [0143]) to remove the portions of the second layer (18, FIG. 4C/4D);
Wang in view of Wong does not teach forming a first patterned photoresist layer over the semiconductor substrate having a third opening; and
forming a second patterned photoresist layer over the semiconductor substrate having a fourth opening.
Li teaches forming a first patterned photoresist layer (30, page 5 par 3) over the semiconductor substrate (1, page 5 par 3) having a third opening; and
forming a second patterned photoresist layer (31, page 5 par 3) over the semiconductor substrate (1) having a fourth opening (FIG. 4-2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Wang in view of Wong since Li teaches semiconductor process integrating stacked photoresist masks to process a gate structure.
The ordinary artisan would have been motivated to modify Li in combination with Wang in view of Wong in the above manner for the motivation of using stacked photoresist masks to build an optimal gate structure to help the semiconductor device the maximum power and current gain. Page 2 par 3 states, “In the RF power amplifier device, important is to optimize the gate structure, to maximize the power gain (fmax) and the current gain…”
Wang in view of Wong and Li does not teach the patterned photoresist layer openings overlapping the gate channel.
Cheng teaches a patterned resist layer (1150) [0091] with an opening (mask covers the top of the device with the exception of the gate opening) overlapping the gate channel (1052) [0091] (FIG. 11A, the process can be repeated of forming an additional mask over the first mask)
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Cheng into the structure of Wang in view of Wong and Li since Cheng teaches a semiconductor process using a mask to assist in processing the device’s gate region.
The ordinary artisan would have been motivated to modify Cheng in combination with Wang in view of Wong and Li in the above manner for the motivation of using a mask to help form the gate region to help reach a low threshold voltage for the device. The abstract states, “…gate structures configured to provide ultra-low threshold voltages…”
Wang in view of Wong, Li, and Cheng does not teach after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the portions of the first layer.
Lin teaches after forming the first patterned photoresist layer (150, page 9 par 1 “…150
comprises a material such as a photoresist…”) and the second patterned photoresist layer (process can be repeated to stack a second mask on 150), performing a second wet etch to remove the portions of the first layer (1331, page 10 par 3 states, “…1331 of the first gate spacer layer 133' is removed with a selective etch process. The etching process can be a dry etching process…”, FIG. 1D/E).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Wang in view of Wong, Li, and Cheng since Lin teaches using a wet etch to form the gate structure.
The ordinary artisan would have been motivated to modify Lin in combination with Wang in view of Wong, Li, and Cheng in the above manner for the motivation of using a wet etch to form the gate spacers since their profile can help improve the electrical performace of the device. Page 2 par3 states, “…gate spacers with different bottom widths for improving electrical performance…”
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 107424919 A, given in IDS) in view of Wong (US 20210257475 A1, given in IDS), Li et al. (CN 112614777 A), Cheng et al. (US 20210118995 A1), and Lin et al. (DE 102022113066 A1) and further in view of Green et al. (US 20130341678 A1, given in IDS).
Re Claim 14 Wang et al. (CN 107424919 A, given in IDS) in view of Wong, Li, Cheng, and Lin teaches the method of claim 13, but does not teach:
forming an interlayer dielectric layer on the gate structure and the second dielectric layer; and
forming a field plate over the interlayer dielectric layer, wherein at least a portion of the field plate overlaps the gate structure.
Green teaches forming an interlayer dielectric layer (bottom 140) [0037] on the gate structure (120) [0030] and the second dielectric layer (124) [0028]; and
forming a field plate (142) [0037] over the interlayer dielectric layer (bottom 140), wherein at least a portion of the field (142) plate overlaps the gate structure (120, FIG. 1).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Green into the structure of Wang in view of Wong, Li, Cheng, and Lin since Green teaches a gate structure integrates in an opening in dielectric layers.
The ordinary artisan would have been motivated to modify Green in combination with Wang in view of Wong, Li, Cheng, and Lin in the above manner for the motivation of using a field plate to help stabilize the current in the semiconductor device. [0005] states, “Field plates have been used to reduce the electric field at the gate edge. The reduction in the electric field in that region may address issues of device degradation and current collapse.”
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (CN 107424919 A, given in IDS) in view of Wong (US 20210257475 A1, given in IDS) and further in view of Li et al. (CN 112614777 A) and Li et al. (CN 115602708 A), Li2 hereafter.
Re Claim 19 Wang in view of Wong teaches the method of claim 9, but does not teach forming the gate structure comprises:
forming a first patterned photoresist layer over the semiconductor substrate having a third opening; and
forming a second patterned photoresist layer over the semiconductor substrate having a fourth opening;
Li teaches forming a first patterned photoresist layer (30, page 5 par 3) over the semiconductor substrate (1, page 5 par 3) having a third opening; and
forming a second patterned photoresist layer (31, page 5 par 3) over the semiconductor substrate (1) having a fourth opening (FIG. 4-2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li into the structure of Wang in view of Wong since Li teaches a semiconductor process integrating stacked photoresist masks to process a gate structure.
The ordinary artisan would have been motivated to modify Li in combination with Wang in view of Wong in the above manner for the motivation of using stacked photoresist masks to build an optimal gate structure to help the semiconductor device the maximum power and current gain. Page 2 par 3 states, “In the RF power amplifier device, important is to optimize the gate structure, to maximize the power gain (fmax) and the current gain…”
Wang in view of Wong and Li does not teach the patterned photoresist layer openings overlapping the gate channel; and
depositing metal over the semiconductor substrate, a first portion of the metal being deposited through the third opening and the fourth opening to form the gate structure, and a second portion of the metal being deposited on surfaces of the first patterned photoresist layer.
Li2 teaches the patterned photoresist layer (400, page 13 par 2, Li2 teaches 1 photoresist, but the process can be repeated to form a second photoresist over the first photoresist) openings overlapping the gate channel (310, page 13 par 3, FIG. 12B); and
depositing metal (730, page 14 par 4) over the semiconductor substrate (100, page 10 par 2, shown in FIG. 2), a first portion (use trenches between and lower and 400) of the metal (730) being deposited through the opening to form the gate structure (730), and a second portion (730 level with and above 400) of the metal being deposited on surfaces of the first patterned photoresist layer (400, FIG. 13B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Li2 into the structure of Wang in view of Wong and Li since Li2 teaches a semiconductor process integrating a gate structure using a photoresist.
The ordinary artisan would have been motivated to modify Li2 in combination with Wang in view of Wong and Li in the above manner for the motivation of optimally forming a gate structure to achieve ideal capacitance in the semiconductor device. Page 1 last par states, “A plurality of air bridge structures are formed between the gate and the groove wall of the gate groove. The embodiment of the invention claims an HEMT device with air bridge structure, because of setting a plurality of air bridge structure, reducing the parasitic capacitance of the device, and further reducing the noise of the HEMT device, improving the response speed of HEMT device under the high frequency.”
Re Claim 20 Wang in view of Wong, Li, and Li2 teaches the method of claim 19, further comprising:
removing the second portion of the metal via concurrent removal of the first patterned photoresist layer (Li, 30) and the second patterned photoresist layer (31, FIG. 4-5, Page 5 par 3 states, “using Liftoff process to peel the first photoresist layer 30; the second photoresist layer 31…”).
Allowable Subject Matter
Claims 15-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/13/26