Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on July 20, 2023, October 25, 2024, & November 25, 2024 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention II and Species A1 (claims 9-14) in the reply filed on 12/03/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9, 11-12 are rejected under 35 U.S.C. 103 as obvious over Zhu et al. (Pub. No.: US 2023/0197839 A1) in view of Kinzer (Pub. No.: US 2016/0086938 A1).
Regarding Claim 9, Zhu et al. discloses a method of fabricating a transistor device, the method comprising: providing a semiconductor substrate (Par. 0023; Fig. 2 – semiconductor substrate 102);
PNG
media_image1.png
662
974
media_image1.png
Greyscale
forming a first dielectric layer on the semiconductor substrate (Par. 0029; Fig. 2 – first dielectric layer 115 (field plate dielectric) is formed of silicon oxide or aluminum oxide); forming a second dielectric layer on the first dielectric layer (Par. 0029; Fig. 2 – second dielectric layer 142 is formed of silicon nitride); forming a gate channel and a field plate channel by: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer (Par. 0029; Fig. 2 – step 210; a patterned reactive ion etch process 214 is performed to form first opening 216 and second opening 218); and performing a first wet etch to form a third opening Par. 0037; Fig. 2 – step 220; an wet etch process 224 is performed to form a third opening); Par. 0039; Fig. 2 – gate structure 130); and forming a field plate overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate channel (Par. 0042; Fig. 2 – field plate 150).
Zhu et al. does not disclose a method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel.
However, Kinzer discloses a method of fabricating a transistor device, the method comprising: forming a first dielectric layer on the semiconductor substrate (Par. 0039, 0071; Fig. 5B – first dielectric layer 160); forming a gate channel and a field plate channel by: performing a first etch to form a third opening and a fourth opening in the first dielectric layer (Par. 0071; Fig. 5B);
PNG
media_image2.png
106
1030
media_image2.png
Greyscale
forming a third dielectric layer directly on the first dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening (Par. 0073; Fig. 5D – third dielectric layer 180); and removing a first portion of the third dielectric layer from the gate channel (Par. 0073; Fig. 5D).
PNG
media_image3.png
102
1024
media_image3.png
Greyscale
In summary, although the end structure taught by Zhu et al. is the same as that taught in the instant application, there are some differences in the methods employed by the two. Whereas the instant application forms the gate structure and the field plate by i) first removing a portion of the first dielectric layer and a portion of the second dielectric layer from the gate channel region and the field plate channel region to expose a top surface of the substrate; ii) depositing a third dielectric layer in both the gate channel and the field plate channel; and iii) removing the third dielectric layer only from the gate channel region before depositing the gate structure in the gate channel, Zhu et al. omits the step of depositing the third dielectric layer entirely. Now, Kinzer teaches, similarly to the instant application, that a third dielectric layer may be deposited after the previously existing dielectric layers are removed from the gate channel region and the field plate channel and then, after such deposition, only a portion of the third dielectric layer located in the gate channel region is removed. Clearly, both methods are viable and commonly practiced ways of making the device, each having its own advantages and disadvantages. Zhu et al. discloses the claimed invention except for a method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to adapt the method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel, since it has been held to be within the general skill of a worker in the art to employ/use a known technique to improve similar devices (methods, products) in the same way is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 11, modified Zhu et al., as applied to claim 9, discloses the method, further comprising: forming an interlayer dielectric layer on the gate structure and the third dielectric layer, wherein the field plate is disposed over the interlayer dielectric layer (Zhu et al. – Par. 0040; Fig. 2 (in light of rejection of claim 9) – dielectric layer 144, under BRI, could be considered as the interlayer dielectric layer).
Regarding Claim 12, modified Zhu et al., as applied to claim 11, discloses the method, further comprising: performing a second patterned dry etch to form a seventh opening in the interlayer dielectric layer through which a portion of the third dielectric layer is exposed (Zhu et al. – Par. 0041; Fig. 2 (in light of rejection of claim 9) – in the device of Zhu et al. modified by Kinzer, the third dielectric layer 180 of Kinzer would be (Fig. 5D) sandwiched between the interlayer dielectric layer 144 and the first dielectric layer 115; so when the second patterned dry etch is performed to form a seventh opening in the interlayer dielectric layer in step 250, a portion of the third dielectric layer will get exposed).
Claims 10 are rejected under 35 U.S.C. 103 as obvious over Zhu et al. (Pub. No.: US 2023/0197839 A1) and Kinzer (Pub. No.: US 2016/0086938 A1), as applied to claim 9, further in view of Hua et al. (Patent No.: US 5288660 A).
Regarding Claim 10, modified Zhu et al., as applied to claim 9, does not explicitly disclose the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel; and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel, wherein removing the first portion of the third dielectric layer from the gate channel comprises: after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer.
However, Hua et al. teaches the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 – first patterned photoresist layer 76); and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 – second patterned photoresist layer 78); wherein removing the first portion of the third dielectric layer from the gate channel comprises:
PNG
media_image4.png
174
370
media_image4.png
Greyscale
after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 –dielectric layer 72 could be considered as the third dielectric layer).
PNG
media_image5.png
204
370
media_image5.png
Greyscale
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Hua et al. to adapt the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel of modified Zhu et al.; and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel, wherein removing the first portion of the third dielectric layer from the gate channel comprises: after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer in order to perform a clean gate electrode lift-off
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Green et al. (Pub. No.: US 2013/0341678 A1) –This prior art teaches a method of fabricating a transistor device, the method comprising: providing a semiconductor substrate (104); forming a first dielectric layer (130) on the semiconductor substrate ; forming a second dielectric layer (124) on the first dielectric layer; forming a gate channel by: performing a first patterned dry etch (step 614) to form a first opening in the second dielectric layer; and performing a first wet etch (step 616) to form a third opening in the first dielectric layer; forming a gate structure disposed at least partially in the gate channel and in contact with surfaces of the semiconductor substrate (step 618), the first dielectric layer, and the second dielectric layer; and forming a field plate overlapping the gate structure (step 628) (Figs. 6-8).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
01/27/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893