Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on February 02, 2026, and February 19, 2026 were in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9, 11-12 are rejected under 35 U.S.C. 103 as obvious over Zhu et al. (Pub. No.: US 2023/0197839 A1) in view of Kinzer (Pub. No.: US 2016/0086938 A1).
Regarding Claim 9, Zhu et al. discloses a method of fabricating a transistor device, the method comprising: providing a semiconductor substrate (Par. 0023; Fig. 2 – semiconductor substrate 102);
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forming a first dielectric layer on the semiconductor substrate (Par. 0029; Fig. 2 – first dielectric layer 115 (field plate dielectric) is formed of silicon oxide or aluminum oxide); forming a second dielectric layer on the first dielectric layer (Par. 0029; Fig. 2 – second dielectric layer 142 is formed of silicon nitride); forming a gate channel and a field plate channel by: performing a first patterned dry etch to form a first opening and a second opening in the second dielectric layer (Par. 0029; Fig. 2 – step 210; a patterned reactive ion etch process 214 is performed to form first opening 216 and second opening 218); and performing a first wet etch to form a third opening Par. 0037; Fig. 2 – step 220; an wet etch process 224 is performed to form a third opening); Par. 0039; Fig. 2 – gate structure 130); and forming a field plate overlapping the gate structure, wherein at least a portion of the field plate is disposed in the field plate channel (Par. 0042; Fig. 2 – field plate 150).
Zhu et al. does not disclose a method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel.
However, Kinzer discloses a method of fabricating a transistor device, the method comprising: forming a first dielectric layer on the semiconductor substrate (Par. 0039, 0071; Fig. 5B – first dielectric layer 160); forming a gate channel and a field plate channel by: performing a first etch to form a third opening and a fourth opening in the first dielectric layer (Par. 0071; Fig. 5B);
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forming a third dielectric layer directly on the first dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening (Par. 0073; Fig. 5D – third dielectric layer 180); and removing a first portion of the third dielectric layer from the gate channel (Par. 0073; Fig. 5D).
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In summary, although the end structure taught by Zhu et al. is the same as that taught in the instant application, there are some differences in the methods employed by the two. Whereas the instant application forms the gate structure and the field plate by i) first removing a portion of the first dielectric layer and a portion of the second dielectric layer from the gate channel region and the field plate channel region to expose a top surface of the substrate; ii) depositing a third dielectric layer in both the gate channel and the field plate channel; and iii) removing the third dielectric layer only from the gate channel region before depositing the gate structure in the gate channel, Zhu et al. omits the step of depositing the third dielectric layer entirely. Now, Kinzer teaches, similarly to the instant application, that a third dielectric layer may be deposited after the previously existing dielectric layers are removed from the gate channel region and the field plate channel and then, after such deposition, only a portion of the third dielectric layer located in the gate channel region is removed. Clearly, both methods are viable and commonly practiced ways of making the device, each having its own advantages and disadvantages. Zhu et al. discloses the claimed invention except for a method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to adapt the method of fabricating a transistor device, the method comprising: performing a first wet etch to form a fourth opening in the first dielectric layer; forming a third dielectric layer directly on the second dielectric layer and directly on surfaces of the semiconductor substrate exposed through the third opening and the fourth opening; and removing a first portion of the third dielectric layer from the gate channel, since it has been held to be within the general skill of a worker in the art to employ/use a known technique to improve similar devices (methods, products) in the same way is obvious. KSR International Co. v Teleflex Inc., 550 U.S.__, __, 82 USPQ2d 1385, 1395-97 (2007)
Regarding Claim 11, modified Zhu et al., as applied to claim 9, discloses the method, further comprising: forming an interlayer dielectric layer on the gate structure and the third dielectric layer, wherein the field plate is disposed over the interlayer dielectric layer (Zhu et al. – Par. 0040; Fig. 2 (in light of rejection of claim 9) – dielectric layer 144, under BRI, could be considered as the interlayer dielectric layer).
Regarding Claim 12, modified Zhu et al., as applied to claim 11, discloses the method, further comprising: performing a second patterned dry etch to form a seventh opening in the interlayer dielectric layer through which a portion of the third dielectric layer is exposed (Zhu et al. – Par. 0041; Fig. 2 (in light of rejection of claim 9) – in the device of Zhu et al. modified by Kinzer, the third dielectric layer 180 of Kinzer would be (Fig. 5D) sandwiched between the interlayer dielectric layer 144 and the first dielectric layer 115; so when the second patterned dry etch is performed to form a seventh opening in the interlayer dielectric layer in step 250, a portion of the third dielectric layer will get exposed).
Claims 10 are rejected under 35 U.S.C. 103 as obvious over Zhu et al. (Pub. No.: US 2023/0197839 A1) and Kinzer (Pub. No.: US 2016/0086938 A1), as applied to claim 9, further in view of Hua et al. (Patent No.: US 5288660 A).
Regarding Claim 10, modified Zhu et al., as applied to claim 9, does not explicitly disclose the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel; and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel, wherein removing the first portion of the third dielectric layer from the gate channel comprises: after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer.
However, Hua et al. teaches the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 – first patterned photoresist layer 76); and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 – second patterned photoresist layer 78); wherein removing the first portion of the third dielectric layer from the gate channel comprises:
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after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer (Col. 4; L 58 – Col. 6, L 8; Fig. 4-14 –dielectric layer 72 could be considered as the third dielectric layer).
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It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings of Hua et al. to adapt the method, further comprising: forming a first patterned photoresist layer over the semiconductor substrate having a fifth opening overlapping the gate channel of modified Zhu et al.; and forming a second patterned photoresist layer over the semiconductor substrate having a sixth opening overlapping the gate channel, wherein removing the first portion of the third dielectric layer from the gate channel comprises: after forming the first patterned photoresist layer and the second patterned photoresist layer, performing a second wet etch to remove the first portion of the third dielectric layer in order to perform a clean gate electrode lift-off
Allowable Subject Matter
Claims 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicants’ arguments filed on 04/23/2026 have been fully considered but they are not found to be persuasive.
The Applicants argue “Applicant respectfully submits that Zhu is not prior art to the Present Application under 35 U.S.C. 102(a)(1), at least because Zhu falls under the prior art exceptions set forth in 35 U.S.C. 102(b)(1)(A): … In the present case, Zhu was filed December 20, 2021. Zhu was published on June 22, 2023. Zhu and the Present Application share a common inventor: Congyong Zhu. The effective filing date of the Present Application is June 29, 2023. Because the effective filing date of the Present Application falls within 1 year of the publication of Zhu and further because of the common inventor (Congyong Zhu), such that the publication of Zhu was made by a joint inventor, Zhu is not prior art under 35 U.S.C. 102(a)(1)” (emphasis added by the Examiner).
The Examiner’s Rebuttal: The Examiner respectfully disagrees with the Applicants assertion that Zhu is not a prior art under 35 U.S.C. 102(a)(1). The 35 U.S.C. 102(b)(1)(A) exception partly reads “A disclosure made 1 year or less before the effective filing date of a claimed invention shall not be prior art to the claimed invention under subsection (a)(1) if (A) the disclosure was made by the inventor or joint inventor or by another who obtained the subject matter disclosed directly or indirectly from the inventor or a joint inventor”. The reference in question Zhu et al. (Pub. No.: US 2023/0197839 A1) has three inventors, 1) Congyong Zhu; 2) Bernhard Grote; and 3) Bruce McRae Gilbert Green. The instant application (18/344,363) has five inventors, 1) Congyong Zhu; 2) Philippe Renaud; 3) Darrell Glenn Hill; 4) Gregory David Hale; and 5) Colby Greg Rampley. So, the instant application and the prior art reference Zhu et al. (Pub. No.: US 2023/0197839 A1) has only one common inventor Congyong Zhu, as noted by the applicant. Under AIA , the term “inventor” means the sole inventor or all of the joint inventors. So, the “inventor” of the Zhu reference is different from the “inventor” of the instant application. In other words, the disclosure of the Zhu reference was not made by the inventor or joint inventor of the instant application. Hence the exception does not apply.
Applicant may overcome the rejection by invoking either the 102(b)(1)(A) and/or 102(b)(2)(A) exception with an affidavit or declaration under 37 CFR 1.130(a) establishing that the subject matter disclosed was obtained directly or indirectly from the inventor or a joint inventor of the application AND providing a reasonable explanation of the additional joint inventor/author in the reference to overcome the rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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05/07/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893
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